The bottom of the cryostat contains a chamber where the main components of the experiment will be contained. This space is cylindrical in nature with heighth = 5.6cm and diameter = 13cm. In addition, the cylinder has two inner lips which create an inner diamter = 11.4cm. Furthermore, hole spacing for the screws that will attach the apparatus to the cryostat is approximately 1cm.
Also, we are working with a square window through which a laser will pass. The opening is an embedded circle with diamter 2.7cm and the square itself having length = 5.5cm.
I include comsol models of 6 different eigenfrequencies for a certain silicon flexure. In addition, the expected graphs of the thermoelastic noise and phonon-phonon loss are also presented for the various mode shapes.
I opened the chamber and spent half afternoon tweaking the fiber feed-through. This thing is extremely unreliable.
At the end I was able to get back a reasonable level of power, even not the maximum.
I also checked that the blades are not rubbing anywhere and that the shadow sensors are close to mid range. Nevertheless, after closing again, I'm still unable to drive at 800 cts.
I started a set of measurements at 600 counts.
The goal is to start crackling noise data taking before the end of the week.
Activities to do
We decided to downconvert the "broadband" output of the ultrasonic microphones (the ones actually sampled at 64k) using Double Balanced Mixers and a Local Oscillator.
In order to have the cleanest possible L.O. signal, we built a breadboard with a 5MHz TTL xtal oscillator (model MX045-3C-5M0000) followed by two 74LS90, each dividing x10.
The output of the last 74LS90 (=50kHz) is sent to a power buffer (BUF634), then splitted in two 50 ohm signals to drive the L.O. port of the mixers with about +7dBm level.
The next step wiil be to complete the setup adding D.B. mixers on the bench
Last night we left the acoustic emission test bed running, with an excitation that gave us about 210 um peak to peak motion of the blade tip. As before, we collected one-hour-long alternating stretches of data, with drive on and off. The difference with respect to before is that microphone 2 has been moved further up the blade.
Both microphones signals still show wider distribution when the blade is driven with respect to when it's not driven. However, microphone 2 (the one further up the blade) shows a smaller increase in the distribution width. We don't have a good explanation for this just yet. The following plots show the histograms of the microphone signal RMS at 4kHz.
To improve the analysis, we considered only the driven data, and tried to correlate the distribution width with the force we were applying to the blade. The force is estimated using the DAC output, in coils. We haven't calibrated it in netwon.
The following plot is a bidimensional histogram: the color gives the number of times the microphone was at a given value while the DAC was at given value. For each bin of the DAC value, we normalized the microphone histogram to the total number of points. In this way we can get rid of the different number of points that have given DAC values (in other words, the DAC value, being a sinusoid, stays more at the extreme than at the center, and we have to compensate for this effect in out histogram, otherwise we can't compare the microphone signal distributions at different DAC values).
The colorscale is hihly saturated to show the tails of the distribution, and the colorscale is logarithmic. It's apparent that the wider distribution that we saw in the first plot are there only when the drive is close to the maximum values. So we have an increase of the microphone noise when the absolute value of the oscillating force we are applying is large. We can't conclude that this is crackling noise, but it's a step in the right direction, even though we were expecting to see an increase of noise when the force derivative was larger.
Background: The design of the DAC noise monitor is in the PCB design stage - I am trying to put the circuit on the PCB board in Altium. We use three power voltages to drive the op amps in the circuit: -15 V. +15 V. We also need power ground and signal ground. This circuit is going to replace a part of a big PCB board with other existing circuits.
Question: What are the layers used by the existing design? The DAC noise monitor needs to fit with other parts, so they have to share the same layers. Is there a PCB layout file for the existing design?
In case of absence, I will start with a signal layer, a -15V power layer, a +15V power layer, a power ground, and a signal ground. I googled a bit and they say the cost will be high and five layers might be more than what we want. Besides, I am not sure about the sequence of the layers either. I will start with this in order to proceed in Altium before we figure out what we need to do:
How much sense does it make?
I proceeded as described below. The routing is completed. All the signal routing is completed. One thing worries me is that I am afraid the signal ground and power ground is yet separated. I do have two internal planes for signal ground and power ground. Should they be connected to the same power input (so that they are just two planes with the same source)? Altium treats all the ground as one net GND. If the answer to the question is yes, I need to figure out how to get Altium separate them. In Altium, you can specifiy which net you connect to, but I did not figure out how to specify which layer. (Maybe I need to create a separated GND net, like PGND/SGND for that?)
Here is a summary file with the schematics and PCB design: NoiseMonitor.pdf
Also, this is the link to the Wiki page, with more details about this work: https://wiki-40m.ligo.caltech.edu/Electronics/NoiseMonitor
As per Chris's suggestions, I replaced the capacitors with surface mount ceramic capacitors, doubled the trace width to 0.5mm and adjusted the routings accordingly. New PCB layout is attached.
I forgot to connect the outputs of U1 and U2. It is fixed. I also run the design rule check and verified that all the connections are made. I separated the power ground and signal ground as well. The summary PDF is updated below.
Progress: the board and components arrived and assembled. Some obvious mistakes are fixed on the next version in Altium.
Next: how to test the board? i.e. How to connect the test instruments (such as spectrum analyzer, DC power supply) to the board? We need connector converters (from BNC to headers female & from BNC to 9 pin D shape male). Or do we have better ways to test it?
Note: Altium footprints for WIMA capacitors are created. Altium test point component is created. These might be useful in the future.
Progress: The reason why the board from oshpark did not work is found. The board has 6 layers, but Oshpark only make 2 or 4 layer boards. They just ignored two layers (the two ground layers) so there is no ground at all on the board.
Some known issues is fixed in the new board (capacitor footprint, connector in the wrong direction). The new board will arrive next Wednesday.
Some good quality connectors are made - next board will be ready to test once arrived.
Next: I plan to put other components into Altium by Wednesday.
The new board arrived this afternoon. I tried the connections - it has enough layers and is grounded. I will assemble the board tomorrow.
In the meanwhile, I have put other unchanged components on the board into Altium, not quite finished (put them in schematics but not PCB, gives me error when importing changes). I will prioritize assembling the new board.
A picture of the board is attached.
1. Board assembled
2. One design error found and fixed in the instrumental amplifier. Now the instrumental amplifier is working
Noise above 100Hz (pass band 20-100Hz), as shown in the transfer function in the picture.
The noise comes from the last stage of the circuit: the low pass sallen key filter. The first two high pass stages works well.
(structure of the circuit: differential input - passive filter - instrumental amplifier - high pass - high pass - low pass - output)
I have tried
1. Checking the connections - the connections are good
2. Replacing the opamp - did not work
Here is a full version of the noisemon, with four channels and the power regulator. I did the routing again since the previous routing 1) did not leave enough space for connectors/other components; 2) Altium does not transfer properly from the schematics to the PCB layout when expanding to 4 channels.
The reason for this problem was found. The gain of the sallen key filters was too high. There is an intrinsic limit of the sallen key filters - they cannot have a gain more than a certain value. Otherwise, they will be unstable. See this TI document for details.
It seems there can be multiple reasons for an op amp to oscillate. I wanted to identify the nature of the oscillation.
I want to isolate one stage and see what is going on. I used the extra empty board and assembled the last stage on it. Putting in nothing at all (the input is GND), I get a signal of 5.792MHz, 321mV at the output.
Now that the problem is even more clear, I will keep looking into this.
After a few days of struggling (and essential help from Chris), mystery is resolved. Fortunately, the oscillation does not have much to do with my circuit design. It is caused by the RLC resonance formed by 1) the inductance of the parallel wires + 2) capacitance of the signal ground plane and the power ground plane.
As is seen in the picture, I twisted the two grounding wires together (reduce the inductance) and the oscillation is gone.
You can also connect the planes on the board (removing the capacitance) and the oscillation will disappear as well.
Two more oscillations problems are resolved, and there is no more oscillations. In the time series (the inputs are terminated), we see only the 60Hz noise.
- Some big bypass capacitors are used to regulate the power.
- A small capacitor is attached to the negative feedback loop in the second HP filter.
New board/components arrived. I will assemble and test them immediately.
# SR785 Measurement - Timestamp: Jan 20 2019 - 15:50:18
#---------- Measurement Setup ------------
# Start frequency (Hz) = 5.000000
# Stop frequency (Hz) = 1000.000000
# Number of frequency points = 200
# Excitation amplitude (mV) = 10.000000
# Settling cycles = 1
# Integration cycles = 10
#---------- Measurement Parameters ----------
# Measurement Group: "Swept Sine" "Swept Sine"
# SR785 Measurement - Timestamp: Jan 20 2019 - 15:04:29
#---------- Measurement Setup ------------
# Start Frequency (Hz): 0.000000
# Frequency Span (Hz): 1600.000000
# Frequency Resolution: 400
# Number of Averages: 100
# Averaging Mode: RMS
# Window function: BMH
#---------- Measurement Parameters ----------
# Measurement Group: "FFT" "FFT"
Duo's noisemon has been in the EE shop/cryo lab for testing. It is a drop-in replacement for the existing monitor board, including both noisemon and Vmon/Imon/RMSmon circuits for all four channels.
Duo is still working on a log entry summarizing the performance of the new board vs simulation. This entry shows some measurements of the performance of the new board vs the old board.
Based on the test results posted, I did the following analysis:
1. Compared measured transfer function to the LISO calculations. Attachment 4 and 6. The transfer functions match well with LISO.
2. Compared measured noise at the output to the LISO calculations. Attachment 1 and 3. The noise is more than LISO calculations by roughly a factor of 2, but I think it is expected - there is coil driver noises (amplified more than 300 times). Also, LISO uses ideal resistors, considering that the noise here is dominated by resistor noise. We also have plots of the noise spectrum with DAC noises injected. In this case, the noise in the passband (20 - 100Hz) is much more, suggesting that the board noise is dominated by the DAC noise.
3. Compared input-referenced measured noise to DAC noise. Attachment 2 and 5. We divided the noise by the transfer function and compare it directly with the DAC noise model. We can see that, in the passband, the board noise is about a factor of 10 less than the DAC noise (channel 2 and 4 has more noise; the signal is polluted by the ADC).
4. A simple calculation based on the transfer function comparing the ADC noise and the amplified DAC noise.
DAC noise > 300nV/rtHz. Passband amplification > 50dB > 300. Amplified DAC noise in the passband > 90uV/rtHz, compared to ADC noise 4uV/rtHz.
FYI: 1. I cannot attachment PDF plots directly since it will stuck the elog server. I put some PNG plots, but PDF plots can still be found in the compressed files.
2. Also, channel 2 is more noisey. It comes from ADC not the noisemon.
Some clean up work on the noisemon is done.
1. Added compensate capacitor.
2. Added mounting holes.
3. Added DCC number. https://dcc.ligo.org/LIGO-D1900052
4. Renumbered the components.
5. Added 0 ohm resistor between power ground and signal ground.
6. Added more test points for the voltage monitor and current monitor.
7. Increased schematics font size.
Next I will create the Bill Of Materials. I need to assemble the manufacturer information and put meaningful and consistent descriptions for the components.
Attachment: new PCB schematics with all the changes made.
We (Chris and I) had a conversation with Rich last week and the following work on the noisemon board has been suggested:
1. Name of power nets: +VCC to +15, -VCC to -15. +V to +18; -V to -18, making it clearer what the power is.
2. Fix the off-grid problems of the schematics.
3. Draw the circuits on the schematics in the standard way. (Rich gave me a bunch of snippets that shows the standard way to draw the circuits, like how to draw a sallen key filter)
4. Ground the shells of the D connectors.
5. Add 1 Ohm resistors at the inputs of the power regulators
6. Use polymer tantalum with at least 35V rating. Previously we are not using polymer ones. Rich said the ones (non-polymer ones) we were using burn and explode sometimes.
7. Add "No error checking" for those pins not being used (e.g. unused op amp pins)
8. Disassemble the "repeat()" in the sheet symbol. Making four sheet symbols and connect them directly to the connectors.
9. Change the outputs of the current monitor, noise monitor and the voltage monitor to differential. Previously we had one of the pins of the D connectors pairs grounded. Now we add a differential driver at the end. It doubles the gain and the range.
Rich said my PCB routing was OK, so all the changes can be reflected on the schematics. I have made all the changes on the schematics (I do have the previous version). The current schematics is attached.
However, "#9 change the outputs to differential" requires a lot more space and the current PCB routing does not have enough free space between the components. Thus, this requires routing the whole PCB again, which is what I am working on now.
We added differential drivers at the outputs of all the monitors. After that the routing becomes impossible at the output connectors.
I replaced the signal ground with an additional signal layer, and reversed the order of the channels on the layout.
Having exhausted all the possible routing tricks, I finally managed to connect the whole board.
We ordered the board from Screaming Circuits and chose to provide the component ourselves. However, the parcel we ordered from Verical was lost by Fedex on its way to Screaming Circuits. The original delivery date was delay from late May to June 13.
Once the board arrives, we will test the board - TF, noise etc. Any others?
I connected the DAC to ADC direclty (picture 1) and send a sine signal into the DAC. However, I did not get the sine signal back from the ADC. I sent the signal in X1:CRY-DITHER_W_MOD_EXC, channel 9 of DAC and expect the signal from X1:CRY-E_REFLDC_IN1, channel 16 of ADC. However, picture 2 shows what I get: a constant signal around 4400 counts.
Noisemon installed in ITMX at L1. I pulled the 1-coherence data. trying to compare with Valery's measurement: https://alog.ligo-la.caltech.edu/aLOG/index.php?callRep=43240.
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I calculated the noise based on L1 data. My calculation is
(1-coherence) * drive = noise in DAC counts
noise in volts = noise in DAC counts * 20 / 2^16
Is this correct?
Increase avg to 1000. We are going to calculate the DAC noise from this.
L1 noisemon data for all four channels.
Will compare ITMX with ETMY.
Going to see if # of average makes any difference.
The formula used to calculate the noise is
Noise = Sqrt[1 - coherence] * drive
ETMY is about the same as ITMX.
More avg - more smoothiness but the shape of the noise curve is the same.
Trying to see if I can reproduce https://alog.ligo-la.caltech.edu/aLOG/uploads/43363_20190213151300_subtraction_offset.png when I use average of 10.
No. Did not reproduce it. Attachment 3 is the same plot without restrictions on the y axis range.
The result is lower when I change the window but still not the same as alog post. A factor of 2 larger at 30Hz.
The bin size was 1Hz. I changed it to 0.1Hz. Now we get some real data.
Can't tell what's going on. Pleaese make the plots readable and describe in the elog what precisely is being calculated.
This is the DAC noise of ITMY PUM coil driver in L1. The data is from September 25, 2019 00:00:00 UTC. I did not subtract the ADC noise and the noisemon noise since I did it for ITMX. The noisemon noise is far below the total noise, and the ADC noise only dominates high frequency. After subtraction, the mismatch above 500Hz will disappear.
There are some lines around 65Hz. I checked the data a few days arounds 9/25. I see them in all the data. I do not understand why yet.
Spectra of the PUM drive signal is attached in 3, noisemon output in 4. I do not see anything at 65Hz in those channels.
ADC noise and Noisemon noise are subtracted in attachment 5.
I checked these data
9/23 00:00, 8:00, 20:00
The 65Hz harmonics stays there.
I checked time domain for 9/15. It is not saturating. (Attachment 6&7)
Attachment 8 is a check on the output of the noisemon signal when L1 is down. It is from 9/24 1600. Surprisingly, I see the 65Hz harmonics in UL spectrum while I cannot see it when the interferometer is online. I do not see the harmonics in the other three channels.
In attachment 9, I checked ITMX from the same time (9/24 1600, interferometer down). The 65Hz harmonics is there in all channels, and the UL output is higher.
Noisemon has been installed at L1 for a while. Now we have it on ITMX and ITMY. ITMX was installed first and ITMY was installed on September 11.
Recently, after it was installed at ITMY, we were trying to check the functionality of the circuit - if it measures DAC nosie properly between 20 - 100Hz. When we were doing that, we encountered some strange harmonics of 65Hz in UL channel. It is shown in attachment 6, data from 9/25 ETMY.
We traced back to where it was installed at ETMY, 9/11, and we still see the lines there (attachment 5).
Then we went to check ITMX, since the data was consistent when it was first installed. However, when we use 9/25 data, we see attachment 4. The UL channel measurement is way above the other three channels. Tracing back the dates, we found in ITMX it started 9/10 (attachment 3), comparing to 9/9 (attachment 2) when it was still good.
All the data and scripts are in attachment 1.
Notes (in case you read about noisemon for the first time):
All the plots are
It is suppose to be DAC nosie + Noisemon noise + ADC noise, which DAC noise being dominant between 20 - 100Hz. The purple curves are DAC noise model. The measurements are expected to be close to it between 20Hz and 100Hz.
Although L1 has been down since the beginning of October, I checked the spectrum at the output of the nosiemon at L1 ITMY. It looks like the UL channel, as we have seen before, still has the lines,
I checked the October 25 data at L1. The drive signal is zero, according to the bottom plot in attachment 1 and 2. The fastimon channel has a lot of lines. Noisemon still has the 65Hz harmonics.
I also checked the Nov 7 noisemon and fastimon data. We still see the harmonics on Nov 7. Also, one channel is completely dysfunctioning. The fastimon is similar to Oct 25.
Attachment 1: Oct 25 noisemon. We still see the harmonics in the noise.
Attachment 2: Oct 25 fastimon. Two channels are messy.
Attachment 3,4,5: Nov 7 noisemon data. Analyzed in attachment 4. Data in attachment 5.
Attachment 6: Nov 7 fastimon data. Similar to Oct 25 - a lot of lines.
Noisemon has been installed in LLO ITMY station. Its LL channel starts to saturate at 10/30 00:00:00. I checked the noisemon output at that time (attachment 1).
The first noisemon board was installed at the ETMY station. It was a prototype board that we brought to LLO and installed there since then. I checked the data today (11/14) and its LL channels is not working.
I checked the time series in the attachment 2 and 3. There are some problem causing the circuit to saturate.
I checked the drive signal below 10Hz in attachment 4. The drive signals across all channels are the same.
I checked the behavior of noisemon in the three stations where they are installed. It is consistent that there is always one channels that is saturating and one channel that has excess noise. However, they are not always the same channels.
ETMY, attachment 1, LL saturating, UL excess noise (UR a little more noise)
ITMY, attachment 2, LL saturating, UL excess noise
ITMX, attachment 3, UL saturating, UR excess noise
Saturation occurs suddenly after running for hours without problem.
I tracked it since the drive was turned on (around 00:36:18) and found that it has been running ok for hours before this happens (attachment 1). Around 3:04:51, the LL channel saturated and then dropped back to normal level. After that, this kept happening and crashed the LL channel (attachment 3).
Attachment 2 is data corresponding to attachment 1.