40m QIL Cryo_Lab CTN SUS_Lab TCS_Lab OMC_Lab CRIME_Lab FEA ENG_Labs OptContFac Mariner WBEEShop
  ATF eLog  Not logged in ELOG logo
Entry  Sat Jan 8 19:52:24 2011, Alastair, Electronics, GYRO, PD board design PCB_drawing_RFPD.pdfRFPD_schematic.pdf
    Reply  Mon Jan 10 15:18:24 2011, Alastair, Electronics, GYRO, PD board design 
       Reply  Mon Jan 10 16:08:04 2011, Alastair, Electronics, GYRO, PD board design 
Message ID: 1238     Entry time: Mon Jan 10 16:08:04 2011     In reply to: 1237
Author: Alastair 
Type: Electronics 
Category: GYRO 
Subject: PD board design 

Quote:

Quote:

 Here is the latest schematic for the PDs along with the board layout.  I'm going to check over the routing one last time but it will probably require checking by someone with more RF experience too.  The pcb drawing doesn't show all the features in the pdf.  It uses split internal planes to distribute the power for the diode bias and also the +/-5v for the opamp.  I've kept a full ground plane as the first one down, so there is a continuous ground plane directly underneath the tracks on the surface.

 There are quite a few rule violations that I've just noticed when running the design rule checker.  They're mostly clearance issues between the silk screen layer and various pads, but I want to get rid of them all at this stage.

The PD design is on the svn under gyro_electronics.

 Okay, so most of these violations seem trivial. I've gone into the rule manager and set it up to use the same rules as Rich had on the other RFPD board and all the trivial violations have now gone.  I've fixed all of them except one, which is a maximum hole size.  We are using 195mil for the holes for the stand-offs.  I'll need to check if there is a reason for that  being there (ie is there some limit from the manufacturer) before I remove the rule or change the hole size.

ELOG V3.1.3-