I've taken a look at what we can do to the pdh boxes when we put them back to their 1/f^2 configuration.  We checked the datasheet for the LF356  that's used on the second stage and there is no mention there of problems with gains of <1.

If we leave the second stage as it is then it has a pole at 100Hz and a zero at 98kHz, with the switchable integrator to move the bottom pole down to zero hz.

The first stage is more of a question to me.  Here are the options that I see:

1) Put back the 3.3uF capacitor.  This leaves the upper zero of this stage at 5kHz instead of 98kHz.  Plots 1 and 2 below show the full TF for both stages using this design, with integrator off and on

2) Move the zero frequency of the first stage up by decreasing the capacitor (we probably don't want to decrease the resistor on this one since it's already only 10ohms).  If we go to 160nF that puts the upper zero at 98kHz.  If we leave the parallel resistor at 1k then we get plots 3 and 4.  The pole is now at ~1kHz which is higher than we want.

3) The last option is that we do the same as in 2) but we also change R30 to a higher value to move the pole down.  As Zach predicted setting things up like this will push us really close to 180 degrees of phase if we push the pole right back down to 50Hz (figs 5 and 6), particularly when we put the boost on.  We could move it part of the way back down using some in-between value.

From the plots it looks like fig2 and fig3 have similar gain at low frequency.  Fig 4 does give slightly more phase margin at higher frequency.