I prepared the cavities for bonding: All relevant surfaces were prepared with clear first contact. I 3D-printed some parts to help me identify the orientation of the wedge and center the first mirror on the spacer, but I made the tolerances a little too tight. I'm having new versions printing overnight and will attempt the first round of bonding tomorrow.

Based on the pictures shown in elog 1985, I have identified mirrors 1,2,5, and 6 as the ones I want to make into cavities. I will bond mirrors 1 and 5 first, and then figure out a good way to make a cavity and bond the second mirror in place while monitoring the cavity loss. I have as basic idea but need to print out some more parts to see if it works that way.

measured the Si cavity dimensions. All the mechanics was/is designed for a 2"x4" cavity, but the cavity is smaller and we might have to modify things...

D=1.9"
L=3.93"
hole at optical axis: 0.53"
venting hole: 0.25"

I wanted to give a visual outline of the process that we have been using to do silicon fab at the KNI.

Until now, we have been performing this process on individual rectangular sections of Si (recall that we sent two 6" wafers out to be diced a while back---see CRYO:1250). The first and second prototypes (CRYO:1260 and CRYO:1264, respectively) showed some imperfections in both 1) the etch pattern (i.e., the 2D pattern that defines the end blocks of the cantilever) and 2) the etch depth uniformity (i.e., the final surface roughness of the etched region). We suspected that either one or both of these are the result of cleanliness issues while handling the individual rectangles. After talking with Shiuh Chao from Taiwan, it seems that a better option is to perform almost all of the process on an entire wafer, then mechanically scribe out the individual cantilevers just before the main etch. There will be more details on that at the end of this entry.

The following is a photo walkthrough of a test run I did on a practice wafer on Friday. This wafer is just a single-side polish 3" wafer that was given to me by a KNI staff member, and the mask I used (see below) was the one Justin and I made for the individual rectangles. I did not cut the sections out before etching, so this run was never going to make usable cantilevers; instead, I just wanted to test out the "whole wafer at a time" scheme and see how it affected the etch quality. For this, I only chose to etch from the top (polished) side, as opposed to our standard, double-side etch.

Spin and bake

This is the step during which the photoresist is applied to the wafer. Beforehand, the wafer is cleaned using a 1:1:40 solution of ammonium hydroxide, hydrogen peroxide and water.

To date, we have been using a photoresist called ProTEK, which is actually a new-ish product that was designed to eliminate some steps with traditional wet etching (more on that later). To use this, a special primer must first be applied before the actual photoresist. In each case, the wafer is placed on a "spinner", which holds the center of the wafer via vacuum seal, the primer or photoresist is pipetted onto the central region, and then the wafer is spun at 2000 rpm for 1 minute, in our case:

After each application of either the primer or the photoresist on a side, the wafer must be baked on a hot plate. The primer requires a 1-min bake at 110 C followed by a 5-min bake at 220 C; the photoresist requires a 2-min bake only at 110 C. Since, per the standard procedure, the wafer must physically be placed on a hotplate (with a sacrificial wafer in between if so desired), I chose to apply the coatings in the following order:

1. Top (polished) side primer
2. Bottom side primer
3. Bottom side photoresist
4. Top side photoresist

I felt that was the best way to protect the more crucial top surface. Here are a couple photos of baking. On the left, the bottom side is up with the primer baking (top side is face down on the sacrificial wafer with its already-baked primer protecting it); on the right, the top side photoresist is baking. You can see some thin-film interference from the minute thickness variations.

Exposure

After both sides are coated with photoresist, the wafer is ready for photolithography. This is accomplished on a Karl Suss MA6 mask aligner machine. This device aligns a photomask to the wafer (with sub-micron precision, if necessary), and then performs controlled UV exposure on the aligned system to define the etch profile.

So far, we have been using a high-resolution transparency print as our mask. This is a common technique in prototyping, and there is a glass blank in the lab that is used to hold the transparency (with scotch tape). The mask is loaded onto a holder and held with vacuum:

The holder is then slid into the machine, and then a drawer underneath holds the wafer, also via vacuum (there are different holders for each wafer size, and there are also adapters to hold smaller chips). The wafer, which is not yet installed, is held within the orange circular region on the plate below:

After loading, various parameters are set, including the contact type (in our case, the mask and wafer are brought into brief contact, then backed off 30 um) and the exposure type (we use 40 seconds of 365 nm exposure at the standard luminosity, which is fixed). Then, a microscope is used to adjust the position of the wafer under the mask via micrometers with 3 degrees of freedom (i.e., X, Y and theta). This is usually a very precise process, but in our case we can actually get by just looking at the alignment by eye. After everything is aligned, the exposure is run. For this, the microscope caddy moves out of the way and the UV source slides in and does its business. Here's a shot of the whole machine:

After exposure, the lithography pattern is only barely visible to the eye under certain light.

Development

To complete the process, the exposed wafer must then be developed to remove the photoresist from the regions where etching is desired. This is done by swashing the wafer in ethyl lactate repeatedly for 10 seconds at a time, blow drying with an N2 gun in between. Four or five cycles is usually enough, and after this is done the pattern is clearly visible:

It is not clear to me what the gunk is in the regions to be etched (these are the central rectangles here). Repeated washing in the developer does not remove it any further, and it may somehow be related to the final etch quality. More on that later.

Etching

Now the wafer is ready for etching in KOH. When I did this with Justin, we set up a beaker on a hotplate with a magnetic stirrer, but the KNI has a full immersion etch bench that is much more convenient. The wafer is held in a wafer holder and dipped into the bath, which is heated to around 80 C and pumped to keep flow:

The etch proceeds at a rate of around 50 um/hour, perhaps faster if the solution is at a higher temperature. For this test, I let it run for about 2.5 hours before coming back to pull it out.

Results

After etching, the photoresist must be removed using a piranha etch, which is just a concentrated solution of sulfuric acid and hydrogen peroxide. I think I didn't perform this at a high enough temperature, so in the following pictures there is still some photoresist on the wafer.

As you can see, the 2D etch definition is much better than in the first two prototypes I made with Justin (see the links at the top of this post). That is, the rectangular regions for the blocks at the end and for the thin cantilever section are very well defined, as compared to those previous trials with the individual rectangular pieces of silicon. So, I am concluding that those imperfections were the result of cleanliness/handling issues with the small pieces, and that they will not be present if we work with a whole wafer at a time.

On the other hand, the etch uniformity (final surface roughness) is still very bad. It is about as bad as the first prototype, and actually much worse than the second one (which itself was bad). From the 2nd pair of photos above, you can see that the unetched regions---though discolored from the remaining photoresist that still needs to be removed---have maintained their optical polish, while the etched regions are dull, even in areas that seem macroscopically uniform. This leads me to think that this is a problem with the actual etch process. It's interesting to note that the very-nonuniform-etch areas don't really correspond to the gunky areas I saw immediately post-development (see above).

In the last pair of photos, you can see some regions of the backside that were unintentionally etched. This is probably due to some photoresist having clung to a surface on which it was resting during any part of this process.

Conclusions

The conclusions are thus: 1) Working with a whole wafer solves a lot of problems, and 2) our etch process is not good.

A major caveat is that, apparently, the ProTEK photoresist was expired. It could therefore be that, with fresh ProTEK, we'll be in good shape. However, we may be better off cutting our losses and just going with the traditional oxide/nitride mask. This is the method used by Shiuh Chao's group in Taiwan, which has produced nice cantilevers, and is a straightforward process that I can develop quickly at the KNI. This process is summarized in this PDF:

I have discussed this with Melissa Melendes, the KNI staff member who has been helping me, and we can begin this on Tuesday. There are only two pieces of machinery that I need to get accustomed with to perform this process:

1. The low-pressure chemical vapor deposition (LPCVD) machine, in order to deposit the oxide and nitride layers for masking, and
2. The mechanical scriber, to cut out the individual cantilevers just prior to etching.

In addition, I'll need to make a new mask (one that has an array of identical cantilever patterns on a single wafer). I can make another transparency, which involves making another image and going to a printshop to have a high-resolution transparency printed, or I can just go ahead and make a nice glass chromium mask, if I know what I want. I'm told this can be done relatively easily using a mask maker at the KNI, though I will need to get some training on it.

For now, I will probably use another practice wafer and test out the oxide/nitride scheme to see how the etch improves. On the plus side, I performed the entire process you see here in a single afternoon by myself, so my proficiency is increasing. It will take a little time to learn to use the machines mentioned above, and having to use them in the process will make the whole fab take a little longer, but not by too much. Stay tuned...

 Edmund Optics has some Si optics (lenses and windows) which we can buy for doing some simple testing of polished surfaces (~120$ ea.):

http://www.edmundoptics.com/optics/defense-optics/cots-lenses/silicon-plano-convex-pcx-lenses/3368

I saw these, but had been avoiding them b/c of the cost. I'll go ahead and buy a handful (6) for testing. If I don't use them, we can probably find a use down the road.

(purchased)

The most recent measurements on the Taiwan-sourced Glasgow-style cantilver (see CRYO:1213) are encouraging, but the best Q measurement at low temperature is still a couple orders of magnitude worse than what is theoretically achievable, and about one order of magnitude worse than our conservative clamp loss estimates. Also, I've done some measurements on other modes (that have different expected clamp loss contributions due to the relative strain energy ratios) to try and sort out what is going on, with little success. Finally, some modes---including the 2nd bending mode at ~650 Hz---exhibited very low Q for no known reason.

One thing I thought about is that, since the Taiwan cantilever did not fit in the groove that was built into the block for the Glasgow-style cantilevers and therefore is just sandwiched between the two large pieces making up the clamp (see CRYO:1211), the clamp is likely pushing down at somewhat of an angle, which could lead to all sorts of non-idealities. Since the other Si samples we have lying around are roughly the size of the clamping region of this cantilever (~300-500 um), I opened up the cryostat today and reclamped the cantilever using a spare broken-off 300-um-thick cantilever piece as a spacer on the other side:

Pumping it all back down, I immediately measured Qs a bit higher than what we saw last time around at room temperature. The last measurement I made before leaving was tau ~ 135 s ==> Q ~ 46000, though it had been increasing up to that point, likely from the residual pressure, which was at ~10^-3 Torr when I left. Compare this with the Q of ~14000 from the last time around, though admittedly I did not record the pressure at which this was measured.

I went into the lab with Justin today to make our second prototype resonator. I am writing the procedure down here from memory. I will correct/update this as we continue.

Note: of all the steps below, only the photolithography is done at KNI. The rest are done within the Painter labs.

Initial prep

1. Peel specimen from the adhesive packaging it is attached to by the dicing company.
2. Rinse with acetone and isopropanol.

Photoresist "spin and bake" (must be done twice: once per side)

1. Pre-treatment.
   1. Soak specimen in weak solution of H₂O₂ and NH₄OH for around a minute.
   2. Dry.
2. Primer.
   1. Attach specimen to spinner (with suction).
   2. Apply primer solution with disposable pipette using designated pump. Apply evenly over surface, enough so that the meniscus nearly reaches the edges.
   3. Spin at 3000 rpm for 1 minute.
   4. Bake at 110 ºC for 1 minute. (All bake cycles are in air on a hot plate.)
   5. Bake at 220 ºC for 5 minutes.
   6. Allow to cool before proceeding to photoresist.
3. Photoresist
   1. Attach specimen to spinner (with suction).
   2. Apply photoresist solution with disposable pipette using designated pump. Apply evenly over surface, enough so that the meniscus nearly reaches the edges.
   3. Spin at 3000 rpm for 1 minute.
   4. Bake at 110 ºC for 2 minutes.
   5. Allow to cool before proceeding to photolithography.
4. Until controlled exposure (photolithography) and development, protect the sample from light by wrapping the holder in foil.

Photolithography (this must also be done once for each side)

1. Mask preparation (only needed when using transparencies, as we are currently)
   1. Place transparency with mask pattern on square glass blank. Center as best as possible to ensure that you'll be within the alignment actuator ranges later.
   2. Slice a piece of scotch tape into thin sections.
   3. Tape the transparency to the glass blank in all four corners, with the transparency as flat against the blank as possible (to avoid diffractive aberrations).
2. Mounting the mask
   1. Turn on external suction pump.
   2. Install blank with transparency attached to it onto the sliding palette. Transparency should be face up, since the palette will be flipped upon installation into the instrument.
   3. Engage suction.
   4. Flip palette and slide into the instrument.
3. Mounting the specimen
   1. Use 2" wafer holder.
   2. Install "chip holder" adapter. This blocks most suction holes that would be used for a full 2" wafer, leaving only a few near the center to hold a smaller chip. (This works for our 50-mm-long cantilevers, but we will have to use a different method to hold anything longer.)
   3. Place, align, and center specimen as best as possible onto the holder, then slide into the instrument. Through the window, one should now see the inverted mask held in place above the specimen.
4. Alignment and exposure
   1. Set exposure type. Some high-resolution lithography requires the mask to be in direct contact with the specimen; we don't need such resolution, so we choose keep a ~50-um gap between the mask and the specimen.
   2. The instrument now fully engages the specimen against the mask (vertically, from below), then backs off the appropriate amount.
   3. Choose an appropriate microscope objective and locate the mask and/or specimen edge on the viewer screen.
   4. Find a good edge for alignment, then align the specimen (movable) to the mask (fixed) in both angle and position with the knobs. Scan the viewer around to ensure good alignment.
   5. When satisfied with alignment, engage exposure. We used 40 seconds at 365 nm, but this depends on the photoresist. The viewer will retract and the illuminator will engage for the designated time, then it retracts and the viewer reengages.
5. Clean up after yourself and leave instrument as you found it.

Development

1. Dip the specimen in the developing solution and swash for 10 seconds.
2. Remove and blow-dry with N₂ gun rapidly.
3. Repeat (1) and (2) until desired pattern is very clear (this is the first point in the process where the pattern should be visible to the eye). The un-exposed regions should be a clean Si surface, while the exposed regions should appear slightly darker.

Etch (to be continued...)

We want our input coupling mirrors to have the same coatings as the mini-mirrors that will be attached to the cantilevers. So, I have sent six blank silicon substrates to John Tardif at Coastline so that he can include them in the coating run.

These are 1-m concave / plano 1" silicon mirrors. They were originally provided by Coastline and they are still in their original packaging.

[Johannes, Zach]

With the necessary parts in hand, we succeeded in getting the SiFi table floating last night.

We followed the instructions in the TMC setup guide. The air supply configuration is as designated there:

Of note is that this system uses special tubes that have restricting orifices inside between each valve and isolator. These short, black tubes are marked with a red rubber band around each, and are located in the setup as prescribed above. There are 4 in all.

I couldn't take a new measurement last night because the cavities were swinging like crazy, but I should have one soon. I'm not sure what to expect, but it would be great if there was some extra isolation of environmental noise in the target (mid-audio) band.

Cryo lab and QIL cymacs have been running without glitches since before the holidays on the SiLabs 5340 timing boards.

QIL was unstable at first, until a DS345 was added to regenerate the 10 MHz reference at the far end of the cable.  (We have plenty of DS345s on the shelf now, but if we ever wish to free this one up, we could apply some of the tips in LT design note 514 at the Si5340 input.)

For future reference, this is what was done to the boards:

• Short across C15, C17 to DC couple output 0.
• Set jumper JP1 for I2C, and connect I2C wires on J17.  (The SiLabs boards are normally programmed over USB using ClockBuilder, a Windows application.  It's not documented how to do this from Linux.  However, a documented I2C interface is provided.  Driving that from a python script on a Raspberry Pi lets the boards start up without any Windows dependency.)
• Short jumpers JP14, JP16 to set power supplies for 3.3V.  (The supplies are USB-configured otherwise.)

The input is a 10 MHz and ~14 dBm sinusoid.  (This is derived from the CMOS clock output of the Jackson Labs LC_XO GPS disciplined oscillator using a tee network suggested by Wenzel, then fanned out by a Symmetricom/Datum 6502 chassis.)  Outputs are two complementary 65536 Hz 3.3V LVCMOS clock signals (sufficient to trigger the TTL inputs of the General Standards ADC and DAC).

The ClockBuilder-generated register configuration is attached and python scripts are in the QIL CDS target directory under qil-timing.

[dmass, Rich]

We need to get the beat readout rebuilt now that we have changed (fixed) the alignment the alignment in the cryostat.

Nic and myself noticed that one of the paths (laser diode 68 a.k.a. West path) was much harder to lock than the others.

Investigating further, the error signal for this cavity was tiny (~10x) smaller than the error signal for the other cavity.

I followed this for a while, and found that we were back in the state where: WHEN WE STRESS THE BOARD WHICH IS ATTACHED TO THE BUTTERFLY MOUNT, THE MODULATION DEPTH DRASTICALLY CHANGES.

Rich discovered / theorized that the capacitors on the little PC boards (SMA to butterfly pins) which go to the diode were cracked. It was difficult to not stress the board given the construction, so he replaced the 1nF and 3nF SM capacitors with leaded caps. The modulation depth shot through the roof.

I am trying to take Rana's advice to give myself some sort of manly gamma for my sidebands.

I have a broadband EOM from Thorlabs:

• V(pi/2) = 350V
• C=12.8 pF  // Rseries = 1 Ohm (measured with 4195 @ Downs w/ R.Abbs help)

Using the ZHL RF amp (one of the heatsunk ones) from R.abb, I could get ~24 dBm into the EOM, which gave me gamma~0.02.

It looks like I need some sort of resonant circuit to do better, so I am taking Zach's circuit (ATF elog#1248) and cleaning it up so that it works for my application.

Components in hand:

Transformers:

• ?
• ?
• PWB-16-BL

2 x tunable inductors

1 x small inductor (3.3 uH measured on the 878A LCR meter with pokey-probes)

Going hunting for a 1.62 uH inductor from R.Abbot (This would give me 35 MHz resonant frequency)

Why do you have to change the circuit and don't use it as is? You said you can choose basically any frequency and Zach used also a Thorlabs EOM so it should work right out of the box.

The circuit was very breakable when I got it - the trim pot snapped off almost immediately. My (meta)physical path, in temporal order:

• Took the rest of the circuit apart to rebuild it with some sort of sturdiness
• Took my EOM to downs to measure the impedance (R=1Ohm C=12.8pF fits well)
• Got some input from R.Ab about the circuit -
  • He was confused why we would do something that seems so complicated, and asked why I didn't just use a simple "tapped L" circuit
• Read up on tapped-L design, simulated it in spice, got it to work with pretend perfect components, didn't get it to work when I loaded real components from coilcraft component lib (this adds series and parallel resistance - see "figure b" in http://mouloudrahmani.com/images/untitled20.jpg)
• Went back to the "known working" model (using transformers to perform a voltage division)
• Caused R.Ab to silently die a little inside when he saw how I was going to stuff the pomona box
• Tried to use some of his premade-transmission line strip stuff instead, with some of the components they had at downs
  • Minicircuits 16-1 transformers (x2)
  • Coilcraft 1008CS-182 inductor
• Spent Wed in downs trying to get some sort of resonance with an inductor and a capacitor in place of the EOM
  • Mickey Moused
• Went to 40m, talked to Koji and Kiwamu about wtf I was doing - Kiwamu showed me a useful webpage about info on what he did.
• Threw the cloogey mickey mouse looking circuit back together in hopes that I can get it to work, since it seems to have at least been *close* to working under Zach
  • * I was unable to find any info in the ATF elog about what the final gain at the EOM was after the numerous tweaks - ~10dB is the highest measured value I saw

Will post more when I make some measurements that aren't stupid

Made resonant circuit for EOM.

Collaborated with R.Ab to keep from nonconsentualizing the canine.

Got something which seems like it will work - impedance matched to 50Ohms, gain of ~3 with a theoretical max of ~4. Should be able to get (\Gamma=0.1) sidebands with this.

Want to revisit when I have a real setup which I understand and is locked, will move on with locking for now.

Here since 11AM yest, so elog must be brief for now.

 I put everything together and "measured" the error signal slope. The value was ~70x too low, though the sweep was noisy as hell. If I swept too slowly, the RMS noise from the error signal on the timescale of sweeping through the cavity was too high. If I swept too fast, the signal looked odd (I think because the light didn't have enough time to build up inside the cavity). I suspect that the high noise artificially

I found the sidebands in transmission on a PD.

• Vcarrier = 1.42V
• Vsideband = 16.2 mV
• Vdark = 6 mV

Adding these all together, I get:

• sqrt(Ps) = gamma/2*sqrt(Pc)
• gamma^2 = 4*Ps/Pc
• gamma = 2*sqrt(Ps/Pc) = 2*sqrt((16.2e-3 - 6e-3)/(1.42 - 6e-3))
• gamma = 0.17

THIS SEEMS HIGH BY A FACTOR OF 2 (I expect gamma ~0.7 - 0.9...I wonder if I screwed up a factor of 2 somehow). However, it is just an estimate and the cavity sweeps are noisy. This makes me believe that the modulation depth is of the right order, and not 70x too low.

FOR NOW, I WILL USE GAMMA = 0.1 RADIANS

UPON CLOSER EXAMINATION, SOMETHING SCREWY IS GOING ON WITH MY 1811.

• I measure a maximum reflected value of 6.4 mV
• I measure a power incident on the PD of 800 uW (with the thorlabs power meter)
• [800e-6 Watts] x [1A / Watt] x [1V / mA] x [1000 mA / A] = 0.8 Volts
• There is a 3 order of magnitude discrepency here
• I think my sidebands are OK, and the PD is either bad, or misaligned somehow

reason: Does it make sense to use silicon substrates for 1064nm coated cavity mirrors?

some plots i've found (nothing for cryo temps so far):

Is the X-axis of the third figure wavelength in nm?

yep, sorry 

Carrier density fluctuations are negligibly small for the cryo cavity beat: It shows up at the ~5e-4 Hz/rtHz level at 10 kHz, and goes down in frequency below that

If we wanted to make an experiment sensitive to this noise, we could just make a cavity with HR on the outside, and AR on the inside, and "win" by the cavity finesse

Resource(s):

• The noise coupling in question: "Free Carrier Driven Noise in Transmissive Semiconductor Optics" - Heinert et al - DCC #P1400084
• Heinert GWADW talk
• Si dopant band gaps (slide 12 of Nic's GWADW talk)
• Virginia Semiconductor stock list (this is where we bought the spacers)
• Doping vs resistivity calculator

 Estimate (summary):

1. Use equation 16 in Heinert paper to get scaling of apparent mirror length fluctuations (valid at \omega >> D/r0^2 - call \omega ~ D/r0^2 the "corner frequency")
2. Plug in ratios of experimental parameters to get our high fourier frequency scaling
3. Scale their results in figure 1 to get apparent mirror length fluctuation in transmission, since this is where they plugged in numbers and showed the actual scaling
4. Scale to intra-cavity length fluctuation for cryo setup

Estimate (details):

Relevant parameters from equation 16:

• H = mirror thickness
• r0 = waist size / sqrt(2)
• n = carrier density
• corner frequency

Mirror thickness is straightforward:

• Heinert: H = 1cm 
• Cryo cavity: H = 

Waist size also straightforward:

• Heinert paper: w0 = 0.5 cm
• Cryo cavities: w0 = 340 um

Carrier density is a little more complicated, but the scaling is the most forgiving to uncertainty (n^1/6) - assumptions are explicitly discussed:

• Heinert paper: phosphorous doping of 1e12 / cm^2
• Cryo cavity: Boron doping level between 7e14 and 2e19 / cm^2 **
  • The resistivity of the substrates, which were purchased from Coastline, is not specced.
  • Substrates are p-type and (100), which probably means they are Boron doped - since this is the most common p-type dopant I saw when trying to buy the cavities
  • Boron has the same magnitude of band gap as Phosphorous (which happens to be 45 meV - so assuming holes and carriers behave the same way, we can treat phosphorous and boron identically)
  • Since we didn't ask for expensive F-Z grown silicon substrates (which is pricier), we can assume they are Cz
  • The Boron doped Cz silicon which virginia sells has a resistivity range of 0.005 to 20 Ohm-cm - they have a fairly comprehensive stock so we assume our substrates fall within this range
  • Using the online calculator (above) we find this corresponds to a density of 7e14 to 2e19 / cm^2
  • ** The noise level in ASD scales as the sixth root of density, so the huge uncertainty is not so scary here

Corner frequency:

Calling corner frequency \omega = D/r0^2, where D is the thermal diffusion coefficient (see table 1 in Heinert paper)

• Heinert paper: \omega = De / r0^2 (since n-type)
  • De(120K;Si) = 35 (cm^2/s)
  • \omega = 2*pi*f = 97 [cm^2/s] / (0.5 [cm]/ 1.41)^2
  • f = 120 Hz
• Cryo cavities: \omega = Dh / r0^2 (since p-type)
  
  • Dh(120K;Si) = 97 (cm^2/s)
  • \omega = 2*pi*f = 35 [cm^2/s] / (0.034 [cm]/ 1.41)^2
  • f = 9 kHz

Parameter Comparison Table: 

Functional form:

Looking at figure 1 from the Heinert paper, we see that above the corner frequency the ASD slope is 1/f

Below the corner frequency the slope is f^(-1/10)

This is very close to a simple pole, so we will treat it as such

Plugging in numbers above the corner frequency and convert to phase noise in the usual way (2*pi/1.55um rad/m)

ASD of Heinert paper @ 100 kHz = 3e-19 m/rtHz

ASD of Cryo / ASD of Heinert = (520 to 2800)

Approximate ASD of phase noise from beat transmission mirror:

G / (1+f / 9kHz)

G = 6.5e-9 rad/rtHz to 3.4e-8 rad/rtHz

Taking the higher noise level and convert to frequency noise:

Approximate ASD of frequency noise at beat due to carrier density fluctuations

If you recall the thermal noise level (elog:1084) - it is clear we can ignore the carrier density noise. This is not surprising as the noise is outside the cavity (seen in transmission as phase noise)

I was giving the cryo poster at the LV meeting, and one of our references wandered up (Ronny Norwaldt). He asked me what type ofsilicon we were going to use, and I had no idea, so I turned to wikipedia. It seems there are potentially 3 types of Silicon (different fab processes) we might use for the cavity spacer.

Two are monocrystalline:

• Czochralski Process
• Float-Zone Silicon higher purity than Czochralski

One is monocrstalline:

• Siemens Process (1/2 way down)

Siemens process Silicon has ~10^-9 purity. Frank says that the Q is bad for this stuff. Ronny agreed. Reference?

I asked light machinery for quotes for a 4x2 reference cavity out of the Czochralski and the Float-Zone stuff, so we'll see what they say they can do.

the Q-measurements were done with doped Cz-grown silicon (see thesis) so i don't see why we should go for the super-expensive, super-pure FZ-grown stuff.

According to literature the linear thermal expansion coefficient is identical for all crystal orientations [100], [110] and [111] as the structure is cubic (e.g. see here).
So regarding the zero CTE point we can use any orientation. However, the Q is different for different orientations, but i think high enough in all cases (but should recalculate noise model for worst case values).

Just to put the nail in the coffin, I redid the carrier density and thermorefractive calculations in Heinert et al. using the cryo cavity parameters (this includes using the hole parameters in table I rather than the electron parameters). I assumed a carrier density of 2×10¹⁹ cm⁻³, which is the most extreme end of David's estimate.

Got the mirrors today. I've scanned all the test data provided. We got 3 sets of data, for mirror #1, #4 and #15. However we didn't get mirror #15. I've listed the actual serial numbers we got on the main page.

So i called Coastline and they told me that they do 10% testing for the entire batch. They made 40 and got 30 good ones (10 rejects). So they fully characterized 3 of them, so they simply sent us all the data they have.
Copy can be found on the svn in /docs/datasheets/Coastline_silicon_mirrors/

Attached the scans ( careful, large file ! ):  

This morning, Johannes and I went to the clean room in Downs and attempted some optical contacting of silicon. For this first attempt we used the pieces on the edge of the wafers that were not complete squares. To clean them, we first used the ion gun to blow off any large particles from the surface, then we wiped the pieces down with acetone and then methenol three times. We checked the cleanliness of the surfaces with a flashlight (figure 1). When we were satisfied that the surfaces were clean enough, we made a right angle with two blocks and put one silicon piece flush against the corner and then placed the second piece (clean side down) on top of it (figure 2). We pushed down on the two pieces to form the bond. 

Our first attempt went very well, the pieces were well aligned and had a storng bond. The second attempt did not work because our first alignment wasn't good, and so we slid the pieces against eachother a lot which weakend the bond. We also noticed that there were some small deformities on the edge of these wafers, possibly from the diamond cutter that was used to cut the pieces. We wanted to see if we could make a stack of three wafers, so we cleaned one of the single wafers and stacked it on top of the first two pieces that we already bonded. This seemed to work well. When we tried to add a fourth wafer onto the stack of three, the bond on the bottom of the stack broke as we were pressing down. We are not sure if it was the first or second bond we made, in the future we will mark the pieces in the order we bond them in. We were ultimately able to make a stack of three, well-aligned wafers after some sliding around (figure 3). I will use this sample in the cryostat today to take an initial measurement of heat flow. 

Today, I wanted to verify if the absorption of silicon is really at the 30% level for 632nm light. We intend to use this laser for our experiment until we find that heating of the substrate causes some significant effect on our mechanical loss measurements.

I used the HeNe in the cryolab to check this on the uncoated wafers that we currently have. The set-up was the laser, a silicon wafer mounted in clips and the summing port of the QPD.

Laser --> QPD sum : 468 mV

Laser --> Silicon wafer --> QPD sum : 140-192 mV

• I can't quite pin down why there is a ~50mV variation on the readout. It doesn't have anything to do with scanning across the surface of the wafer (i.e. some edge effect). My suspicion is that the angle of incidence on the QPD changes and that is why there is the variation. There doesn't appear to be any modulation of that amount with the laser itself.

From this measurement, I conclude that the reflectivity is at 29%-41% for this laser.

I was looking for a temperature dependent Poisson's ratio measurement for silicon to put in to the COMSOL model, and got tangled up in crystal orientations.

My understanding is that the <111> orientation has a uniform poisson's ratio for either parallel or perpendicular orientations (where $// \neq \perp$ in general). See: http://www-mtl.mit.edu/researchgroups/mems-salon/sriram_Si-111-better.pdf

The <100> orientation has a directional dependence, but elogs such as this tell me that the Q are different for different orientations. I couldn't find another entry that actually showed which orientation has the highest Q, but I assume it is <100> since this is what we use? Could someone point me to a reference for this? I don't really understand why the Q should vary for different modes (other than a vague statement like that it's because the material parameters are different). 

For the purposes of modeling for now I have used isotropic material parameters and fixed the Poisson's ratio at the value parallel to the <111> plane. Probably at some point it would be good to add directional dependence.

I don't have a great answer for you, but here is some information: 

I have always used the <100> orientation, as that is what the other cantilever guys seem to use. For example, see Shiuh Chao's slides here: G1200849. I admit that I have no personal justification for why this should be the case.

In fact, here is a paper from Ronny Nawrodt back in 2008 that has some Q vs. T data for some samples of bulk silicon, also looking at the difference between <100> and <111>. Somewhat surprisingly based on the above, there actually seems to be a slight improvement in Q on <111> with respect to <100>, at certain temperatures. This is only a small effect, though, and at most temperatures the Q appears to show no difference between orientations.

I wanted to do some intensity feedback testing, for two reasons:

1. Just to get used to using the fiber amplitude modulators
2. While I wait for the machined parts for the 1064nm M2 ISS testing on the old gyro table, I might as well use this basically perfect setup to do some initial runs with the M2 at 1550nm

So that I can have as much power as possible, I removed the fiber phase modulator and installed the amplitude modulator in its place. To generate the PDH sidebands, I simply drove into the laser bias tee with the 30 MHz oscillator signal and increased the amplitude until I got the same modulation depth as I measured with the modulator. I also had to readjust the demod phase via cable lengths, but after that the cavity locked just as before (and with an identical OLTF---not shown here). I don't claim that this locking technique is as good as using a phase modulator, in light of possible RFAM effects, but it is likely fine for intensity testing.

I also tried to increase the DC drive current of the laser, but it kept stalling after I tried to increase it above ~115 mA (the output power would increase in accordance with the plot on the datasheet, but then would suddenly crash and not return if the current was lowered until the driver output ON/OFF was cycled---not sure what gives here). So, I set it to 100 mA, where it seemed stable. The output of the laser head at this current is ~12 mW, so the max-transmission output of the amplitude modulator is about 6 mW (due to the 50% insertion loss). Adding a slight DC offset to the modulator, I reduced the output to ~92% to get some linear actuation strength for feedback.

I then tried to create an AC-coupled loop with an SR560, but had problems with stability on the low end. Eventually, I gave up and used the A-B function to subtract the measured DC level of around 4 V from the TRANS PD signal. I then put a pole at 300 Hz and scaled up the gain until I saw oscillations up near 100 kHz, and then slightly back down. Using this offset-subtracted DC-coupled loop, I was able to get solid in-loop performance, obtaining a UGF near 100 kHz and suppressing fluctuations to the dark noise level (consistent with the PDA255's noise) over a wide band.

The next step will be to use my low-noise readout optoelectronics and try out the Chachi servo.

I changed the geometry, material properties, and temperature of my model to more closely mimic the cavity and vacuum tube in the lab downstairs.

I've now saved all of my comsol models, images, and text files to the SVN in case anyone wants to look at or fiddle with them.

File title: 6-29_cavity_vactube
    •    2D axisymmetric model
    •    Materials
         ⁃    295 K fused silica cavity (Corning 7940, solid, NIST SRM 739 Type I)
         ⁃    295 K stainless steel vacuum tube (UNS S30400, solid, polished)
    •    Geometry
         ⁃    cavity diameter = 2"
         ⁃    cavity length = 8"
         ⁃    vacuum tube diameter = 8"
         ⁃    vacuum tube length = 22" (this is not counting flanges)
         ⁃    vacuum tube thickness = 0.12"
    •    Physics
         ⁃    surface-to-surface radiation
              ⁃    ambient temp: 295 K
              ⁃    no heat flux from boundaries
              ⁃    strain reference temperature: T
         ⁃    conduction within cavity and shield
              ⁃    both cavity and shell initially at 295 K
         ⁃    boundary step function
              ⁃    outside of tube set to 295.1 K at time t = 0
    •    Results: time-dependent
         ⁃    probing temp of inside of cavity
         ⁃    Time constants:
                  1) Conduction through vac tube: 5 seconds
                  2) Radiation to cavity: 2 hours

It looks like this at time t = 0: 

Videos, demonstrating conduction through vacuum tube and radiation between tube and cavity

• Video #1 (First 8 seconds show heat propagating through stainless steel vacuum tube.)
• Video #2 (All 30,000 seconds of simulation, showing heat  propagating to inner cavity from outer tube.)

I probed the temperature evolution of the point at the very center of the inner cavity. I fit it to an exponential on Igor Pro and got the following fit:

T(t)=T_0-A*exp[-t/tau] with

• T_0 = (295.10000 +- 0.00005) K
• A = (-0.10268 +- 0.00008) K
• tau= 7180 +- 15 s

Here's the plot (bottom curve, blue dots) and fit (red line) with residuals plotted up top (also blue dots).

My next task is to find a function that fits better, that takes into account the conduction through the stainless steel and fused silica.

Notes on materials:

• Corning 7940 is the only kind of fused silica in the COMSOL model library.
• NIST SRM 739 Type I is one of many orientations/variations for Corning 7940. I don't know which, if any of the options, is the kind we're using.

 Update: More exciting video (by which i mean the same video with some Bach music added and a slightly faster frame rate)

I made a simplified cryogenic model.

This is a 2D axisymmetric model. The inner cavity is silicon and the outder shields are both aluminum.

The dimensions are the same as those in the drawings for the physical cryogenic cavities being built.

I wanted to see how long the inner radiation shield took to cool to the temperature of the outer shield, first first with no conductive links between the cavity and either of the shields.

I set the entire system to 120K initially except for the outer edge of the outer radiation shield, which is set to 125K at time t=0. The cavity and inner shield cool to 120K during the duration of the simulation. 

The inner radiation shield has changed by 1-1/e of the temperature step after 3.0 x 10^5 s or 83 hrs. 

The cavity interior hadschanged by 1-1/e of the temp step after 4.25 x 10^5 s or 118 hrs.  

This further supports Frank's finding that if time constants of the thermal coupling in this system are to be on the order of an hour, the dominating form of heat transfer will be conduction through the links between the shields and the cavity. 

It makes sense that this system I have modeled would have two radiative poles. Fitting this on matlab may allow for identifying them separately from one another.

My next step in modeling is to add a conductive link and run the same simulation. Since I'm working in 2D axisymmetric mode, the link will be a thin disk. To account for the added cross-sectional area through which heat can flow, I'll decrease the thermal conductivity of the material accordingly. 

PSOMA hardware inventory

I located the materials for stage 1 PSOMA on the West optics table. I recorded what we have in the hardware inventory, and what we don't have is flagged for purchase. I start by cleaning up the electronics rack, removing anything I think is not in use.

Electronics rack

• Both laser current drivers are D1500207
• The E laser has a TED 200 C temp controller. The W laser is not plugged in to TEC, but there is a spare ITC 502 combination controller on the rack, and cryo cavs has a additional ITC 510.
• There are three universal PDH servo boxes on the W rack: 1x D0901351 and 2x D1700219-v1. All of the boxes need lids and proper rack mount hardware.
  • Innards
    • Inside the *1351, the board matches the front panel DCC number (serial number 1437)
    • Both the *0219 have matching boards: D1700192-v2, D1700195-v2, D1799182-v2, D1700131-v2
  •  
• Power supplies
  • The +- 15V power strip is currently unplugged. I don't see a low noise DC supply on this rack, but there is a Tenma 72-6615 on the ground. The closed-ring connector of the power strip is incompatible with this supply, so likely it was powered off of something else.
  • There's a NewFocus 1901 +- 15V supply on the W table itself. I think this should be located not on the table? The outputs are 0.1 A max to banana, plus 2x 0.3A max to a coax cable. The NewFocus was only supplying the PDs on the table. 
  • Cryo cavs has a dedicated rack for its power supplies (2x Sorensen DCS33-33E), separated from the laser control and PDH electronics. Is this an important choice, and should we also move our power supplies?
  • On the bottom of the rack, there's a Mech-Tronics NIM power supply. Seems out of use, only a PD power supply and readout board is plugged in, but this has no corresponding PD. 
  • I found on the elog that Chris moved the two Sorensens from the cryo cantilevers (W) rack to the cryoaux (central, rolling) rack after the supplies Johannes bought in 2017 died (fans not running). Do these usually die right after their 2 year warranty expires, or were we especially hard on them?
    • sidenote, great to see a potential solution to cryo lab timing woes, and that the overheated Sorensens were causing cominaux hard drive failures. Thanks Chris!
    • I've added 2x Sorensen supplies to our purchase list for PSOMA
  • For now, I moved all existing power supplies onto the electronics rack, and power the strip with the Tenma. In the future, we can discuss a remote location for power supplies, and will buy 2x additional Sorensens.
• Misc
  • a bunch of old and open circuit boards, in cases compatible with the NIM supply. One power amp II; one PDH2 servo board (D1100996); 2 channel low noise amplifier (contains D1101396-v2 and another hand made board); a general filter board claiming to be from the gyro experiment. 
  • There were a few loose minicircuits components connected to the OCXO preamp (D1500064). These were providing 33.59 and 32.7 MHz modulation to Zach's experiments. I removed these from the preamp so we can give them a more permanent box later.

W optics bench

• vacuum pump
  • I don't see the pumping station that used to be by the W optics bench. I don't remember using it elsewhere, and don't find any elog mentioning it being borrowed or moved. Has anyone seen this pump? It's one of the HiCube all-in-ones; it should have LIGO property tag C21832.
  • Similarly, what happened to the IR labs cryostat that housed the cantilever Q measurement (property tag)? I see maybe the glint of a cantilever in the short gryo vacuum can, and I have the cantilever Q HV driver and feedthrough, but no cryostat.
• Photodiodes
  • PDA50B (Ge, 800-1800 nm)
  • 2x PDA255
  • Found 2 loose (unmounted) photodiodes wrapped in foil near the "optical contact razorblade test" setup (SE corner of W table).
  • NewFocus 1811, 1611
  • 1 home brewed QPD and breakout board, (PN on the circuit board is 10-00146 rev 1)
• Put away or onto the workbench any loose optics, unused optomechanics, and most cables. Anything that wasn't a stock part I placed in a clear plastic box labeled 'Cryo Cantilevers' in the projects cabinet (2-part wooden cabinet on S wall). Stock parts went into the respective optics cabinets.

Misc

• The lab temperature is still way too high. The temperature at the particle counter is reading 78, the thermostat still reads 71 F. The filter is not leaking substantially.j
• Got the speaker working -- there was an aux adapter in the headphone port, so system was confused
• Raymond requested a CF16 blank. I couldn't find one, but gave him a CF40-to-CF25 adapter that had a CF25 blank epoxied onto it, along with a CF16 to CF40 adapter and some gaskets. Here was the disinfection procedure for sending these items to QIL:
  1. Found a large plastic bag and disinfected inside and out with Phenomenal (TM) spray
  2. Disinfected the unpackaged UHV components with 70% isopropyl alcohol and a Kim wipe, wrapped them in foil, and placed in the disinfected bag
  3. Disinfect the outside of the bag with Phenomenal spray and leave outside the door to cryo for same-day pickup.
• noted that pressure in cryo Q vacuum is 24 utorr after about a day valved off
• Emailed Jordan and Liz about anemometer, to measure air flow in cryo. If we can compute the time for air to circulate through the cryo lab, we can reduce the length of time between lab entries (currently Shruti and I are leaving 1 day between our lab uses). 
• Starting piling up seemingly unused components from W table onto the S workbench. These need a new home.
• Found some historical documents, sticky notes from Zach. Took photos of these just in case (attached, later) and placed along with the miscellany on the workbench.
• Checked with other W Bridge lab users before entering EE shop at 3:30pm. Disinfected surfaces I touched before and after use. I retrieved 3x 9V rechargeable batteries for the cryo lab multimeters.
• Found a cardboard boxed fiber polarization controller (FPC032), which I placed in the NW optics cabinet sans box. Is this safe for storage (attachment 3)? What about things like Kim wipes, are those an acceptable amount of cardboard, or should they be eliminated?
• Moved any cantilevers, etc into the silicon storage cabinet (NW corner cabinet)

I have been working on a new noisebudget for the CryoCavity experiment. It uses Chris Wipf's new SimulinkNB framework and should really streamline our NB needs. For info on SimulinkNB, read this document.

I currently have the following things working:
Optical transfer functions are all computed automatically by a new Optickle model I have made.
A rough 1/f PDH feedback servo is implemented.
Optickle calculates all the quantum noise automatically.
Adding other noise sources and servos is very straightforward.

Attached is a representative workspace. The noisebudget it produces only has a single trace in common with the old noisebudget for now (the beat PD shot noise). And mine is about an order of magnitude too low at the moment, though this is probably due to me assuming near perfect optical coupling everywhere. But the ballpark is right. There is a weird bump in mine which I think is related to how I calibrate the units.

I'll be adding more noise sources in the near future.

It's all available on the svn at: 40mSVN/CryoLab/NoiseBudget/SimulinkNB
You also need to add this (and subdirs) to the matlab path: 40mSVN/NB/aLIGO/Common/Utils <-- updated
...as well as Optickle, available on the iscmodeling cvs or here.

I have spent the last couple days working on measuring several of the Taiwan cantilever modes simultaneously using the continuous measurement system. This has been more difficult than just opening two instances of the moderinger program and filtering each instance for a separate mode. The first two modes that I'm measuring are clearly coupled: I can hold both modes at two set amplitudes, but as soon as I disengage the 1st mode's lock, the 1st mode begins to increase in amplitude as the 2nd mode feeds energy into it. This results in clearly incorrect calculations such as negative losses and Q's since energy is being pushed into the mode from a source other than the ESD drive signal. I have been playing with bandpass filtering around each drive output to successfully lessen this effect, however the coupling is still significant enough to prevent accurate Q measurements. This is an ongoing problem that I haven't been able to solve yet. ***Edit: I think I fixed it, see CRYO:1285 -Matt

I took some more ringdown and continuous measurements of the first two Taiwan cantielver modes independently (300K and gauge reads 2e-7 torr):

Both modes have a higher Q than when Dmitry and I took measurements on Saturday, and the fundamental mode has improved significantly. I think that the most likely cause is lower pressure. We left the pump on all week and the gauge isn't accurate at very low pressures so we are likely at a lower pressure than we are reading.

On a different note, we got a fresh dewar of LN2 today and Nic set up the temperature measurement system. We were able to cool the cryostat down to 160K. I set up the continuous measurement for the first mode and will be recording Q as the cryostat temperature equilibrates overnight.

Last week, Johannes and I had the idea that we could glean some new information about noise in individual cavities by beating our lasers against each other in lock. Since my noise is much higher than his, he recognized that this was of more immediate use to me, but agreed anyway ;-)

We had a long enough fiber sitting around the lab, but there was one problem: since my PDH sidebands are applied in the fiber chain, we needed a way to extract a clean, unmodulated beam for beating. To that end, we bought a 90:10 fiber splitter from ThorLabs (PN1550R2A1). It arrived yesterday, so we did the test last night.

We figured out a very non-invasive way to do the inter-experiment beat. First, the splitter was installed in one of my setups between the isolator and the phase modulator, picking off 10% of the light at that point. That pickoff was then piped over to the CryoCav table using a 10m PM fiber. Then, since only one of his cavities was necessary for the test, we simply disconnected one of his lasers and sent the light from my table into the newly freed collimation setup. After that---adjusting powers appropriately---we simply used his frontal beat setup to make the measurement. It was almost automatic.

It was even better than that, though: when we locked our cavities, there was immediately a strong beat at 100 MHz. This was remarkable, since as far as we can tell the frequencies could have been off by several GHz.

Here is a plot of the usual SiFi beat spectrum, along with SiFi-CryoCav beats with each SiFi cavity:

And a zoom of the higher-frequency section:

The point of this test was several-fold. First, I was interested in understanding the apparent sensing noise limit around 300 mHz/rtHz. For one thing, I wanted to see if this noise was coming primarily or solely from one cavity. It appears that, though the noise is marginally higher in the East cavity, it is present in both at nearly the same level.

Second, I wanted to learn the nature of the narrowband displacement-noise features being uncovered in the same band as the broadband noise has been reduced. Some of these are high-enough-Q to be reasonably interpreted as mechanical modes. These higher-Q features can also generally be rung up by banging on the table. However, there are apparently much-lower-Q features (most noticeably at ~3.2 kHz, but also barely revealed above the residual laser noise just below 6 kHz) that don't seem to behave as expected for mechanical modes. The jury is still out as to what these are, but the inter-experiment beat measurements reveal that these are actually composite features. This is most obvious from the splitting of the 3.2-kHz feature in the yellow trace---it's hard to see, but there is a similar splitting in the red trace, and it's the sum of all four closely spaced low-ish-Q modes that result in the very-low-Q composite feature in the SiFi-only beat in blue. This effect, which is also apparent in the 6-kHz feature, explains part of why the Qs are apparently so low, but even the individual features seem very low-Q for mecahnical modes.

Finally, there are some more general insights to be gained from this measurement. Most strikingly, it appears that the scattering responsible for the shelf at some tens of Hz is dominated by the East cavity. Also, more generally, one can read off features that are common to both cavities---often with rejection of ~10-30---and those that appear only in a single cavity. So far, there are no "smoking guns" indicating something optically or mechanically very wrong with just one cavity.

For the record, this test was performed with the vacuum pump on, which has been observed to add some considerable fuzziness and strong lines to the noise. I'd like to try this again with the pump off.

I want to move forward with the complementary slow DAQ using the Acromag XT series we have in the lab. I can cram as many as 12 of these units into a 2U box, but I think that may be a little overkill for how many channels we actually need. I'm planning right now to put 6 in, which will pretty much fill the front panel:

• XT1220-000 (8 differential channels analog in)
• XT1540-000 (8 differential channels analog out)
• XT1120-000 (16 channel discrete I/O with sourcing outputs)

This gives 16 analog in, 16 analog out, and 32 binary I/O channels, most of which I will package as D-SUB9, but save some channels for general purpose BNC connectors as shown in the attached front panel proposal.

The new PDH boxes have quite a few switches if we want to go this route, but alternatively we can use one of Koji's spare fast binary I/O cards for the CyMAC and put more analog channels in this chassis. The coating noise experiment would permanently occupy 4 analog outputs, up to 4 analog inputs, and binary outputs depending on the PDH boxes.

If anyone has a considerable amount of channels that would go in this one please give input.

The only thing that I can think of from CryoQ world, is that we would want perhaps 6 or 8 ish temperature sensors going in there (max).

So there is some additional wiring in the BYU circuit called the "slow start" circuit which they use as a slow ramp up switch for the current. This was omitted in the initial board build.

Sam and I are in the subbasement adding this to the boards so that we have a good way of turning on the current

I think we still need some sort of intelligent way to turn the thing off, as it stands, all the options we have are somewhat violent, and give the diode a reverse bias pulse each time.

We had the appropriate transistors, but they were old as hell and we couldn't get solder to stick to them so I ordered some more from Digikey - "slow start" circuit on a couple day hiatus

Here are the details of what I did to get the board up and running.

Relevant Photo album of work: (Picasa)

WHY?!?!

• No safe way to slowly power up the diodes as built without some external voltage source which we tune
• RIO specifies ~10mA/sec for power up to be certain to avoid mode hopping
  • Raises diode temp if we slew faster than TEC feedback
  • If diode temp goes up too much it jumps to another mode
  • There is hysteresis b/c it wants to stay at the mode its lasing at, so we don't mode hop back to "good" mode when we cool back down
• Existing filtering (a couple poles at 2.4 Hz) too high to get close to 10mA/sec

WHAT I WANT:

• Ability to switch the diodes on / off safely
• Low voltage noise input (or at least not terrible noise)
• Ability to power up the whole system safely (elog:336)

WHAT I DID:

• Added a switch and resistor in a pomona box on the input (see album above)
  • Resistor chosen so that the operating current when in steady switch-closed state is appropriate for each diode
• Added a capacitor to the board in parallel with R25
  • Used 2 10uF caps (we're out of 22uF)
  • Epoxied caps to board
  • Wired them as shown in album

HOW IT WORKS:

• Power up the driver box, switch open
• Diode is unplugged at this point
• Capacitor initially gets charge +Vreg across it
• Capacitor discharges with time constant ~10 sec (both plates at Vreg)
• Voltage across R9 should be ~0, which is the "make no current" state
• Plug in diode
  • This might be a bad idea in theory, but it seems fine in practice
• Switch closed
• Capacitor charges to some fraction of Vreg defined by the voltage divider formed with the ~65k and 100k resistors with time constant ~10 sec
• Current starts flowing into diode with same time constant as the RC on the input

TESTING IT:

• I used two generic 0.7V diodes to simulate my laser diode
  • Attached these to "output to laser" with mini clips
• Put fluke in series in current mode
• Switched switch on and off to see response on fluke
• Tested the board with a fluke while switch on / off, measured:
  • Vreg (Iout = (Vreg - Vin)/50)
  • Current out
  • Voltage of current monitor
    • Compare with Current on fluke to sanity check that my slew rate is ~ the same
  • Voltage across R9 - this should be proportional to current
  • Voltage at TP1
    • This is the output of the op-amp - I make sure it's not railed
  • Voltage at input
  • Slew rate of current monitor (now calibrated)
• Plug in diodes with switch set to off and look for transients

========================

         RESULTS

========================

 TL;DR - They work fine!

We are now at the right order of magnitude for slew rate!

To test whether or not it was a "bad thing" to plug in the diodes in the "driver on, switch off" state, I looked at the current monitor on a scope while somewhat violently plugging in and out my test diodes. I saw no detectable change in a signal of > 60 uArms on the cope (the now-calibrated current monitor output). To make uber sure I should look at TP1 to make sure i understand what the op-amp is doing when switching on / off. I will do this.

[Den, Chris, Nic, Zach]

Since my snafu before the LVC meeting (CRYO:1225), the small cryostat has been in pieces being thoroughly cleaned and aired out. Nic wanted to have the ringdown setup rebuilt so that we can demo the steady-state Q measurement technique for our visitors, so we did some work today to make that happen.

This morning, I re-lined the main chamber walls and floor with aluminum tape. This model came with some thin foil lining the walls, attached by periodic thin strips of double-sided paper tape. We have been intermittently scraping some foil off each time we cycle, and since a nasty residue was present on the floor of the chamber after the epoxy incident, I figured it was time to replace the lining. I just used aluminum tape since a.) it is stronger and will be less prone to scraping off, and b.) if and when we need to replace it again, it should come off much more easily.

This afternoon, we rebuilt the cryo package on the cold plate (clamp with Taiwan cantilever installed, ESD, and 45º mirror). Since we don't want to use epoxy to mount the power resistor anymore and we don't have any tapped holes in the clamp, we have not equipped any heat source or temperature sensor. This is fine, since we really just want to use it as a demo this time around, and room temperature should be sufficient. If we want, we can still cool it down to LN2 temperature, but we won't have any actuation or readout.

Upon pumpdown, we noticed that the pressure had stalled at around 20 mTorr after a good 20 mins of pumping, indicating that we had a leak. We checked the top seal and electrical feedthrough (which had also been freshly reattached during the rebuild), and found no issues. With nothing else to try, we decided it was most likely the seal between the chamber floor and the main section (I had to foil this with rectangular sections of tape, which I then XActo cut into a circle at the o-ring groove, so it was possible that a foil flake was blocking the seal). With everything still in place, we flipped the cryostat over and removed the bottom. We found a couple places where a tiny piece may have extended into the seal, so I re-cut the circle more conservatively. When re re-sealed, we found the pumpdown profile to be much closer to what we usually expect. The pressure was a few mTorr after ~10 minutes and showed signs of healthy decline.

We rebuilt the optical readout, then tested the MODERINGER amplitude sensing and found everything seemed to be working. We did not want to test the ESD at this high pressure. When I left, the Q was relatively low at maybe a few thousand, but gas damping was likely still a limiting factor. Also likely is that there is still some residue on the cantilever that I didn't get off, or perhaps even that some irreparable damage might have been done. We should be able to tell when the pressure is low enough.

I have officially undergone my KNI safety training and am now a lab member. Over the next couple weeks I will do specific process/instrument trianing with both KNI staff and Justin.

I had placed the expedited order for the modified cavity mounts on Tuesday last week and received them on Friday afternoon, as expected. The tapped holes on the barrel were not going to be machined by them, which was pointed out beforehand and known to me. I flattened the outsides opposing the 2-56 tapped holes for mounting the cylindrical PEEK pieces which hold the cavity for this purpose in the solidworks file, so I would be able to drill and tap the holes with reasonable precision after receiving the part. I also had to tap the 8-32 holes for the set screws which make the parts lock on to the guide rods. Basically none of the hole features in radial direction were machined due to the CNC-only machining.

After tapping a few holes successfully the tap broke off and got stuck in the part. I tried to drill it out and did free its side but is was too fused with the part for me to eject it, so I had to cut it out from the side. The result is quite a bit of cosmetic damage and that one of the PEEK mounts is only attached with one screw. There is still plenty of connecting material left to complete the ring, and due to the geometry I don't think that this compromises the mechanical stability of the part. I went ahead with the assembly, we can order a replacement part later. All other holes were tapped with no problems (I had spare taps, and half the holes were already tapped at this point, although I proceeded being extra careful).

I tested the whole assembly to see if any other modifications were needed. I was particularly worried that the holes for the guide rods were not going to line up well enough between the four parts to be joined. It turns out that they line up quite well though. After finishing the machining I cleaned the parts first with soap, then sonicated them in 60C DI water with 3% detergent (the standard stuff) for 20 minutes, followed by two 2-minute rinsing cycles in lukewarm pure de-ionized water. I included the existing parts of the mounting jig in this cleaning run, since they came in contact with the residually-oily parts during test-fitting. After drying them off I cleaned the parts with Isopropanol and placed them in the QIL baking tank. The parts were baked at 120C for >48 hours over the weekend.

The new optical breadboard was air-baked at 190 C for ~5 days total on a hot plate. The breadboard was flipped at half-time.

While setting up the locking servo, we did some calculations along the way to make sure things were acting correctly.

With 11Vpk-pk going into the EOM matching circuit, we looked at the cavity transmission while sweeping through carrier and sidebands resonances. We saw 4.48V carrier transmission and 3.12mV sideband transmission. This gives a modulation index of Gamma=0.053.

Assuming the EOM response is the manufacturer value of 4.5rad/V (where we saw 0.053rad/(11/2)V into the matching circuit) we get a gain of 2.14 for the matching circuit (expected 3?). This is at 35.5MHz.

We were also able to calibrate the frequency actuator of the laser. Sweeping through the sidebands corresponded to 1.8V, with 71MHz separation, or 39.4MHz/V. (consistent with Dmass' memory)

We had about 8mW in reflection with the cavity away from resonance. Thus the peak-peak height of the PDH horns should be about 2*8mW*Gamma. The trans-impedance of the RF diode is 700Ohm and the responsivity is slightly more than 1 (don't remember this number). Thus in terms of Volts on the reflection RF PD the peak-peak PDH signal should be about 8mW*2*0.053*~1*700 = 0.6Vpp. EDIT: these numbers don't include the signal attenuation through the mixer.

The frequency discrimination of the PDH sensor should be about (Peak-peak value)/(cavity pole). If the cavity pole is low (as measured by dmass) at 150kHz. This corresponds to 1.9V/MHz. EDIT: these numbers don't include the signal attenuation through the mixer.

We have not yet confirmed the last two numbers (PDH peak and slope) it was around here that we discovered some weird parasitic RF coupling (it was acting like there was phase modulation, but the EOM was disconnected) and futzed around trying to find it. We will start tomorrow with a different mixer, and also clean up the cabling.

The +18V Sorensen power supply in the cryocav rack was not working, which means all the CDS electronics were not powered properly. I'm not sure how long this was going on. The symptom was that the Sorensen front panel read 0 volts, and its remote operation LED was lit.

The fix: Sorensens have a connector in the back with jumpers that programs remote/local operation. After reseating that connector, the supply came back to life.

started a collection of companies/quotes for silicon mirrors :


McCarter Technology Inc
http://www.mccarteret.com

• military/ NASA contractor
• can superpolish silicon

http://optics.nasa.gov/tech_days/tech_days_2005/docs/21%20McCarter%20Single%20Crystal%20Silicon%20Mirrors.pdf

Coastline Optics Inc - QUOTE AVAILABLE
http://www.coastlineoptics.com/

• can provide a 1 Å RMS microroughness finish on a 1"Ø, 1M concave ROC, silicon substrate,
  but this would be a custom build item.
• Also provides coatings: The coating would be a low scatter Ion Beam Sputtered, TiO2/SiO2 multilayer dielectric, tailored to our requirements.
  
• A rough order of magnitude for this work would be $6500 with a lead time of 3 to 4 months.
  
• 10-20 pieces is the minimum lot size for the substrates and the cost is roughly $3,500 less the coating. 

Gooch & Housego - CAN'T DO IT
www.goochandhousego.com

• Better than 1 Å surface roughness
• Laser quality 1/10 wave flatness, 10/5 scratch dig

Reply from them:
"We offer 1"Ø 1M ROC Fused Silica Substrates, which are usually in stock. Or we
could manufacture 1"Ø 1M BK-7 Substrates, which would be a custom job. I understood
your e-mail to be 1"Ø 1M Silicon Substrates, which we are not able to manufacture."

Almaz Optics, Inc. - CAN ONLY SUPPLY BLANKS, MAYBE GOOD FOR SPACER
www.almazoptics.com

ELECTRO OPTICAL COMPONENTS, Inc - QUOTE REQUESTED
www.eoc-inc.com

• do silicon mirrors all the time for CO2 lasers, surface only >3nm rms, but could buy pre-polished substrates and let them repolish somewhere else

Umicore Laser Optics USA
also known as http://www.ulooptics.com, manufacturer of CO2 laser optics and beam delivery systems

• standard quality silicon mirrors (concave) are stock parts, e.g. 10SIS3-05
• http://www.ulooptics.com/docs/pdf/silicon_laser_mirrors_lenses.pdf
• http://www.ulooptics.com/docs/pdf/silicon_co2_supermax_laser_mirrors.pdf
  
• Surface Accuracy only  L/40 @ 10.6µm
• contact see here : http://www.ulooptics.com/docs/pdf/ulo_Si_supermax.pdf

Rocky Mountain Instrument Co.- QUOTE RECEIVED, CAN DO SPACER TOO
http://rmico.com/specifications/mirrors

• Silicon (monocrystaline- any crystal orientation) PO/CC mirror (uncoated)
• Diameter= 25.4mm +0/-0.25mm
• Edge thickness= 3mm +/-0.1mm
• ROC= 1m
• Surface figure= l/20 @10.6mm
• Surface quality= 40/20
• Surface roughness < 1nm

10 pcs : $125 ea
15 pcs : $115 ea
20 pcs : $100  ea    

Expected Delivery: 4 WEEKS ARO

Asked again what they can do in terms of surface figure and quality  if we pay more money
       

     

Updated collection of companies/quotes for silicon mirrors :


McCarter Technology Inc - QUOTE REQUESTED
http://www.mccarteret.com

• military/ NASA contractor
• can superpolish silicon

http://optics.nasa.gov/tech_days/tech_days_2005/docs/21%20McCarter%20Single%20Crystal%20Silicon%20Mirrors.pdf

Coastline Optics Inc - QUOTE AVAILABLE
http://www.coastlineoptics.com/

• can provide a 1 Å RMS microroughness finish on a 1"Ø, 1M concave ROC, silicon substrate,
  but this would be a custom build item.
• Also provides coatings: The coating would be a low scatter Ion Beam Sputtered, TiO2/SiO2 multilayer dielectric, tailored to our requirements.
  
• A rough order of magnitude for this work would be $6500 with a lead time of 3 to 4 months.
  
• 10-20 pieces is the minimum lot size for the substrates and the cost is roughly $3,500 less the coating. 

Gooch & Housego - CAN'T DO IT, ONLY FLAT/FLAT
www.goochandhousego.com

• Better than 1 Å surface roughness
• Laser quality 1/10 wave flatness, 10/5 scratch dig

Reply from them:
"We offer 1"Ø 1M ROC Fused Silica Substrates, which are usually in stock. Or we
could manufacture 1"Ø 1M BK-7 Substrates, which would be a custom job. I understood
your e-mail to be 1"Ø 1M Silicon Substrates, which we are not able to manufacture."

Almaz Optics, Inc. - - QUOTE REQUESTED
www.almazoptics.com

ELECTRO OPTICAL COMPONENTS, Inc - QUOTE REQUESTED
www.eoc-inc.com

• do silicon mirrors all the time for CO2 lasers, surface only >3nm rms, but could buy pre-polished substrates and let them repolish somewhere else

Umicore Laser Optics USA - CAN't DO GOOD SURFACE QUALITY
also known as http://www.ulooptics.com, manufacturer of CO2 laser optics and beam delivery systems

• standard quality silicon mirrors (concave) are stock parts, e.g. 10SIS3-05
• http://www.ulooptics.com/docs/pdf/silicon_laser_mirrors_lenses.pdf
• http://www.ulooptics.com/docs/pdf/silicon_co2_supermax_laser_mirrors.pdf
  
• Surface Accuracy only  L/40 @ 10.6µm
• contact see here : http://www.ulooptics.com/docs/pdf/ulo_Si_supermax.pdf

Rocky Mountain Instrument Co.- UPDATED QUOTE RECEIVED, CAN DO SPACER TOO
http://rmico.com/specifications/mirrors

• Silicon (monocrystaline- any crystal orientation) PO/CC mirror (uncoated)
• Diameter= 25.4mm +0/-0.25mm
• Edge thickness= 3mm +/-0.1mm
• ROC= 1m
• Surface figure= l/10 @1.5um
• Surface quality= 20/10
• Surface roughness < 1nm

10 pcs : $150 ea
20 pcs : $120  ea    

Expected Delivery: 4 WEEKS ARO
       

Mindrum Precision, Inc. - QUOTE REQUESTED 
www.mindrum.com

Perkins Precision Developments, LLC - QUOTE REQUESTED
www.perkinsprecision.com

I have received the first spacer quotes, they can be found on the new cavities wiki page, which I expanded with a lot of cavity design blabla.

https://nodus.ligo.caltech.edu:30889/CryoWiki/doku.php?id=documents:2nd_gen_cavities

Keeping a checklist (to become a recipe) for installing LTSpice on OS X via Wine. Some info was found here helpful hacker dude

1. Install Macports (via .dmg file for OS 10.7)
2. >  sudo port -v selfupdate      % update macports
3. check shell: bash
4. Install and update XCode (can do via app store)
5.  Build Wine
   
   • section title "Build Wine, the MacPorts way"
   •  >  sudo port install git-core wine-devel   (from "Build Wine git version, the MacPorts way"
     • Took a while installing things - ~
     • Error: org.macports.build for port wine-devel returned: command execution failed
       To report a bug, follow the instructions in the guide:
           http://guide.macports.org/#project.tickets
       Error: Processing of port wine-devel failed
     • Googled a small amount, idk what the problem is
   • sudo port install wine   (installs 1.4.1 instead)
     
     • Install seemed successful based on messages
   • sudo port -v selfupdate
     • Total number of ports parsed:    19
       Ports successfully parsed:    19
       Ports failed:            0
       Up-to-date ports skipped:    16414
   • checked ~/.profile as per instructions in above link
   • added this command to profile as per recommendation in above link:
     • export DYLD_FALLBACK_LIBRARY_PATH="/usr/X11/lib:/usr/lib:/opt/local/lib"
   •  >   if [ `sysctl -n hw.cpu64bit_capable` -eq 1 ] ; then echo "+universal" | sudo tee -a /opt/local/etc/macports/variants.conf; else echo "not 64bit capable"; fi
     • This command suggested by helpful hacker dude
     • output "+universal" -> macports knows whether or not it is good with 64 bit

   • > sudo xcodebuild -license   (agree to xcode license)
     Downloaded LTSpice.exe install file
     > wine LTspiceIV.exe
     errors came up, but installer window also came up - clicked install @ C:/program files etc...
     LTSpice opened
     error on opening LTSpice in Wine:   Dynamic session lookup supported but failed: launchd did not provide a socket path, verify that org.freedesktop.dbus-session.plist is loaded!
     Drawing things seems to work. I will play more tomorrow. Also fix the terrible formatting in this elog.
     
      sudo launchctl load -w /Library/LaunchDaemons/org.freedesktop.dbus-system.plist
      launchctl load -w /Library/LaunchAgents/org.freedesktop.dbus-session.plist
     The above tells macports to start up D-bus each time, and made that error go away
     
     
     
     

Up soon: use dropbox to get my spice topology set up and synched between my machines.