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Entry  Tue Nov 26 17:35:59 2019, Chris, Lab Infrastructure, General, CDS rebuild/upgrade 
    Reply  Fri Jan 10 14:08:57 2020, Chris, Lab Infrastructure, General, SiLabs 5340 timing ticking along Si5340-RevD-RTSCLOCK-Registers.txt.gz
Message ID: 2500     Entry time: Tue Nov 26 17:35:59 2019     Reply to this: 2501
Author: Chris 
Type: Lab Infrastructure 
Category: General 
Subject: CDS rebuild/upgrade 

The digital controls in the cryo lab have been in need of maintenance for some time.

  • The computer OS (Debian 8) was nearing end of support.
  • smartmon was warning of failing disks in the front end machine (cymac1) and slow controls/file server (cominaux).
  • File server and external network connections were sluggish because cominaux and the router lacked gigabit network interfaces.
  • Timing has been glitchy, with occasional spurious trips of the DACKILL watchdog.

In an attempt to remedy this we're implementing the following upgrades (some of which are still in progress).

  • Revised rack layout
    • Timing and front end hardware moved from rolling rack to cryocav rack, which is fixed to the floor.  Anecdotally, timing glitches were often seen when moving the rolling rack around.
    • cominaux moved to rolling rack to free up space
    • Sorensen DC supplies replaced and moved to rolling rack.  The old power supplies had broken fans and were overheating.  This was cooking cominaux, which is probably why its hard disks have been dropping like flies.  I took two working Sorensens from the cryo-cantilever rack as replacements.
  • Revised ADC/DAC timing interface boards, and rackmount enclosures for all timing hardware
  • All workstations and cominaux updated to Debian 10 (latest stable version)
  • cymac1 updated to Debian 9 (latest version confirmed to be working as front end)
  • WiFi router and cominaux upgraded with gigabit networking.  Port forwarding and DHCP address assignments were moved over to the new router, and its admin account has a standard CDS password.
  • Add a passive filter to clean up square-wave harmonics in the 10 MHz timing reference oscillator
  • Replace DS345-based timing slave with SiLabs 5340 clock generator eval board.  The ADC and DAC are supposed to be driven by two complementary clocks, which the DS345 cannot deliver.  Also, there is a slow timing drift with the DS345, due to the finite resolution of its direct digital synthesis waveform generator.  The SiLabs board solves both of these problems quite inexpensively, freeing up the DS345 for general lab use.
  • New disks in a RAID configuration for cymac1 and cominaux.
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