I set the beat back up and locked both loops with new LB1005 + zero-pole between LB and driver topology

Tuned and measured coupling, RAM offset, and modulation depends for both paths.

East:

• P_E = 1e-3 W
• Gamma_E = 2*sqrt(0.100/2.04) = 0.44
• Coup_E = 51.2/64 = 0.8
• Z_E = 600 V/W
• Err Slope = [ 2 * P * Gamma * sqrt(coup) / f_cav] * [Z_E] = [ 2*1e-3*0.44*sqrt(0.8)/40e3 W/Hz ] * [600 V / W] = 1.26e-5 V/Hz

West

• P_W = 1e-3 W
• Gamma_W = 2*sqrt(0.084/1.40) = 0.49
• Coup_E = 67/91.2 = 73.5
• Z_E = 400 V/W
• Err Slope = [ 2 * P * Gamma * sqrt(coup) / f_cav] * [Z_E] = [ 2*1e-3*0.49*sqrt(0.735)/40e3 W/Hz ] * [400 V / W] = 8.4e-6 V/Hz

Locked both paths and tuned gain to minimize error signal RMS

Measured error point of both paths w/ SR785 (see below) - divided by error slope for calibration

Both signals ~100 nVrms/rtHz at floor

Set PLL back up - used level 10 mixer, with amp on beat signal so that beat RF level = +6 dB

Measured beat at input to marconi for a couple different ranges

PLL *not* divided out:

** PLL UGF(s)***

• Vpp = 672 mV
• discriminant = [0.336 V / rad]
• 10 kHz marconi range: 10 kHz/1.41V
• loop = [ 0.336 V / 1 rad ] * [ 10e3 Hz / 1.41 V ] * [ 1 rad / f Hz] => UGF =  2.38 kHz
• 20 kHz marconi range: 10 kHz/1.41V
• loop = [ 0.336 V / 1 rad ] * [ 20e3 Hz / 1.41 V ] * [ 1 rad / f Hz] => UGF =  4.75 kHz