Noise calculation from PD in PLL: ( I actually asked Koji once and did this already, see psl:730 . The results are similar)
1) determining which setup gives the best performance:
fig1: OLG TF of PLL with different gain setup.
2) Measure electronic noise from readout system with the chosen setup. This noise will show up (after some correction) in the beat and determine what is the limitation of PLL readout technique.
The PD was blocked, the feedback signal (Vfb) to the actuator (LO) was removed and measured.
3) Block diagram
[add block diagram and calculation]
4) After Koji explained on how to calculated noise budget from electronic noise in PLL to us, here the nb with PLL noise. (note: the LO phase noise has updated to 1kHz input range)
With the electronic noise from PLL, the sensitivity of this technique will prevent us from observing coating noise above 1kHz.
I'll calculate the noise from cable delay technique later and compare which one will give us better sensitivity.