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Entry  Wed Feb 8 22:10:56 2012, frank, tara, DailyProgress, BEAT, noise budget and beat beat_2012_02_08.png
    Reply  Thu Feb 9 22:31:03 2012, frank, tara, DailyProgress, BEAT, noise budget and beat TF_gain.pngnb_2012_02_09.pngnb_2012_02_09.png
Message ID: 816     Entry time: Thu Feb 9 22:31:03 2012     In reply to: 815
Author: frank, tara 
Type: DailyProgress 
Category: BEAT 
Subject: noise budget and beat 

Noise calculation from PD in PLL: ( I actually asked Koji once and did this already, see psl:730 . The results are similar)

1) determining which setup gives the best performance:

  • Gain on SR560 = 200. This gives UGF of 33kHz with 60 degree phase margin. Gain 500 has phase margin of 18 degree, which is too low, see fig 1.
  • Tuning range on Marconi = 1kHz. Currently, we cannot go with lower range. Usually, this noise couple directly to the readout and cannot be suppressed, so the lower noise (smaller range) the better.


fig1: OLG TF of PLL with different gain setup.



2) Measure electronic noise from readout system with the chosen setup. This noise will show up (after some correction) in the beat and determine what is the limitation of PLL readout technique.

     The PD was blocked, the feedback signal (Vfb) to the actuator (LO) was removed and measured.

3) Block diagram

[add block diagram and calculation]

4) After Koji explained on how to calculated noise budget from electronic noise in PLL to us, here the nb with PLL noise. (note: the LO phase noise has updated to 1kHz input range)


With the electronic noise from PLL, the sensitivity of this technique will prevent us from observing coating noise above 1kHz.

I'll calculate the noise from cable delay technique later and compare which one will give us better sensitivity.


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