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 PSL Not logged in  Thu Aug 12 16:27:09 2010, tara, Notes, NoiseBudget, DC simulation Fri Aug 13 01:14:53 2010, Frank, Notes, NoiseBudget, DC simulation
Message ID: 277     Entry time: Fri Aug 13 01:14:53 2010     In reply to: 275
 Author: Frank Type: Notes Category: NoiseBudget Subject: DC simulation

graph?

 Quote: I used COMSOL to simulate temperature change caused by 10^-4 fluctuation from the main DC power. That is the temperature change in the substrate due to power change from Pin to Pin + Pin*10^-4.  Pin is 10mW. This should give us the upper limit of the expected frequency noise. The area under the plot of Temperature vs Depth is 1.9 * 10^-8 [meter*Kelvin].   thermal coefficient for substrate is 0.51 *10^-6 thus dL is (0.51*10^-6) * (1.9*10^-8) ~ 10^-14. Use dL/L  = df/f ;  where L is the cavity length = 0.2035m,  f = c/ lambda. df = 15 Hz. (effect from thermal expansion 1 mirror in the cavity only)

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