40m QIL Cryo_Lab CTN SUS_Lab TCS_Lab OMC_Lab CRIME_Lab FEA ENG_Labs OptContFac Mariner WBEEShop
  PSL  Not logged in ELOG logo
Entry  Mon Jul 23 18:07:14 2018, anchal, DailyProgress, ISS, Introduced zero to cancel cavity pole. Mostly final circuit. CRYO_ISS2LoopGainTF.pdfCryo_ISS2_AOMCavity_Schematic.pdfCryo_ISS2_AOMCavity_LTSpiceAnalysis.zip
    Reply  Tue Jul 24 11:04:37 2018, johannes, DailyProgress, ISS, Introduced zero to cancel cavity pole. Mostly final circuit. 
       Reply  Tue Jul 24 14:28:08 2018, johannes, DailyProgress, ISS, Introduced zero to cancel cavity pole. Mostly final circuit. Cryo_ISS3_AOMCavity_Schematic.pdfCryo_ISS3_LISO_Analysis.pdfCRYO_ISS3AOMCavityLisoAnalysis.pdf
    Reply  Tue Jul 24 13:47:48 2018, anchal, DailyProgress, ISS, Introduced zero to cancel cavity pole. Mostly final circuit. Cryo_ISS2_LISO_Analysis.pdfCRYO_ISS2AOMCavityLisoAnalysis.pdf
Message ID: 2214     Entry time: Tue Jul 24 11:04:37 2018     In reply to: 2213     Reply to this: 2216
Author: johannes 
Type: DailyProgress 
Category: ISS 
Subject: Introduced zero to cancel cavity pole. Mostly final circuit. 

By making stage 3 active you may be adding a lot of OpAmp noise, since you're amplifying it by a factor of 100 at low frequencies. It sits behind the first two gain stages so it might not matter for the input referred noise? But I don't think it's good practice. What was wrong with having that stage passive? A gain stage like this, which doesn't provide gains higher than 1 and actually attenuates over a broad range is usually better kept passive because of amplifier noise.

Did you check the circuit for stability? The AD829 in stage 3 is driving a pretty low resistance as load. Not sure if LTSpice can identify such problems.

ELOG V3.1.3-