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Entry  Mon May 28 17:36:58 2018, awade, DailyProgress, FSS, Fixing FSS binary under voltage issue 
    Reply  Thu May 31 14:17:42 2018, awade, DailyProgress, FSS, Fixing FSS binary under voltage issue 
       Reply  Tue Jun 5 16:35:54 2018, awade, DailyProgress, FSS, Monitor channels overdrawing current in output buffers 
Message ID: 2193     Entry time: Thu May 31 14:17:42 2018     In reply to: 2192     Reply to this: 2197
Author: awade 
Type: DailyProgress 
Category: FSS 
Subject: Fixing FSS binary under voltage issue 

After switching the laser fast monitor channel from the front panel FASTMON pin to the FASTM_P/FASTM_N pins I found that the PID controllers that use this channel to adjust the laser slow frequency became unstable.  After turning down the gain the oscillations of laser temperature were very difficult to tune out.

It looks like the issue is with the fact that the FSS interface board (LIGO-D040423) low passes the monitor signal with a 0.8 Hz LP filter (200kΩ wt 1 µF cap).   The narrowed bandwidth of this 'sensor' in the PID loop limits the bandwidth of the total OLG.  We could turn down the P and up the I a little bit, but this seems less good than switching out some resistors.  

I replaced four 100 kΩ resistors R99, R100, R116 and R117 with 510 Ω resistors.  This brings the LP filter on the Fast monitor channels and mixer monitor channels up to 156 Hz: the new frequency is well above the ADC 10 Hz sampling rate but should still filter very high frequencies that are not of interest to the slow loop. I'm not sure what the ideal cut off point should be wrt digitizing signal and the loop, but this seems like a good first guess.

These modifications were made to North and South FSS interfaces boards (LIGO-D040423), serial 2010:005 and 2010:00? respectively. These changes are logged in the wiki page and with a label on the box back to this post. 


Autolockers were not catching the resonances again. It turns out I had unplugged the excitation to the FSS acromag controller box that engages the binary channels.  It had been plugged back in but often fails to activate the logic because it is still being powered from a 5 V plug pack.

Decided it was time to make the switch to 9V. I installed some voltage dividers to set the excitation out to the FSS interfaces to 4.9 V with a low voltage of 0.66 V maximum (unpowered).  See PSL:2058 for the wiring, I used option D with R1 = 820 Ω  and R2 = 680 Ω.  The new wiring was tested to check the voltages were right, so I don't fry the FSS interface box again.  I also made some changes to the soft binary channels in the acromag IOC: the front medm panel Test1 and Test2 switches are now flipped (NOT operation) so they make sense from the users point of view.  Before the logic was inverted so turning TEST1 off actually activated this path in the circuit.

I also noted down the channels off the ADC card that picks off the monitors from the FSS D25 connector.  This should reduce the number of front panel BNCs as it can all be routed inside the Acromag interface controller box. These have remapped from Aidan's acromag crate into the FSS interface controller box.


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