40m QIL Cryo_Lab CTN SUS_Lab TCS_Lab OMC_Lab CRIME_Lab FEA ENG_Labs OptContFac Mariner WBEEShop
  PSL  Not logged in ELOG logo
Entry  Mon Jan 15 14:43:53 2018, awade, DailyProgress, FSS, Added cap to FSS acromag binary channel 5V supply 2018-01-14_20.24.02.jpg
    Reply  Wed Jan 24 18:29:13 2018, awade, DailyProgress, FSS, Fixing the Acromag latching issues and adding resistors to match the logic levels to FSS and PMC interface boards. Acromag-to-pullup-logic_options.pdf
       Reply  Thu Jan 25 15:34:29 2018, awade, DailyProgress, FSS, Testing and installing PMC electronics mk1 D980352-A.pdfD980352-D.pdfD980352-A_AWade20180128Mods.pdf
Message ID: 2058     Entry time: Wed Jan 24 18:29:13 2018     In reply to: 2049     Reply to this: 2060
Author: awade 
Type: DailyProgress 
Category: FSS 
Subject: Fixing the Acromag latching issues and adding resistors to match the logic levels to FSS and PMC interface boards. 

In troubleshooting binary engage interfacing between acromag XT1541 and the PSL servo board for PMC locking (see context PSL:2056) I think I've located the origin of our latching issues with the acromag cards: we're not using enough excitation voltage for the acromag's internal FET buffers to clear their on-voltage thresholds.

Acromag Binary Chanels REQUIRE 6-32 V Excitation

The XT1541 manual gives a recommended voltage range of 6-32 V for the digital excitation driving voltage.  I had been running it at 5.1V because it actually worked (most of the time) and it is a bad idea to drive a 5V level logic chip at an excess of 5 V. However, often, on a power cycle, the excitation voltage of the binary outputs isn't quite enough to push over the minimum threshold and the binary output of the cards latches off. I tried a few power cycles of the cards at binary excitation voltage at 4V, 5V, 6V etc and found that 5 V was just at the threshold where the binary outputs were responsive to modbus IOC channel changes.  6V> guarantees working.

Dealing with logic with pull up resistors

Most of the inputs for binary engage in LIGO electronics have some kind of pull up resistor on their inputs.  For the FSS it is 4.99 kΩ pull up to +5V.  In the pre-modecleaner servo boards (LIGO-D980352-D) there is a 10 kΩ pull up to +5V.  Aidan had previously come up with a solution for interfacing with the 4.99 kΩ pull up resistors in the FSS boxes input logic (see PSL:1573).  This was to add a ~810 Ω resistor in parallel with the acromag's internal 10 kΩ resistor to bring the off state voltage below the 0.8 V threshold of the HCT157D input chip (see option B in attached). This is satisfactory for ensuring that the off-state of the acromag forms a voltage divider back from the +5V rail to ground through the 810 Ω || 10 kΩ of the acromag + added resistor. It gives a value of 0.66 V at the HCT157D's input. However, as it stands, the on state is whatever the minimum of the acromag is (6V). That value exceeds the acceptable limit for the logic.

If we add one more resistor, it is possible to divide down whatever the acromag binary channels put out to 5V while also ensuring the off state is below 0.8 V.  The attached figure shows the four options for configuring a resistor network to adapt the acromags to driving the pulled-up inputs digital logic switches.

  • Option A connects the acromag directly to the digital logic.  In this case the 10 kΩ pull-down inside the acromag along with the 4.99 kΩ pull up to +5V gives an off state voltage of 3.34V (too high for 0.8V switching threshold) and an on-voltage limited to that of the source.
  • Option B  is what we use now for the FSS. This gives a useable off voltage (0.66 V for R1 = 820 Ω and Rpullup = 4.99 kΩ), but is limited to the on voltage of the source.
  • Option C is not great, you would need a really large value for R2 to bring the voltage divided between the input and +5V pullup rail close to 5 V, R1 would then need to be made very small, greatly increasing the current requirment.
  • Option D best.  In the case of the FSS interface, with a pull up voltage of +5V and Rpullup  = 4.99 kΩ, choice of R1 = 820 Ω and R2 = 164 Ω brings the on state to 5.0V (from a 6.0 excitation) and the off state falls to 0.66 V.

The current requirements for option D are also fine.  In the on state the acromag will need to source about 6.7 mA, which is fine. In the off state 0.8 mA will be sourced via the +5V pull up, which is also ok.

Here are the equations for choosing R1 and R2

R_1 = \frac{R_\textrm{pull up}}{(V_\textrm{pullup}/V_\textrm{off}-1)-R_\textrm{pull up}/R_\textrm{pull down}}

where Vpull up is the voltage of the pull up rail, Voff is the desired off state voltage, Rpull up is the pull up resistance of the input logic and Rpull down is the pull down resistance of the driving circuit. Using this value we can also find that the best series resistance is

R_2 = R_1(\frac{V_\textrm{excitation}}{V_\textrm{on}}-1)

where Vexcitation is the  high value of the driving circuit and Von is the desired on (high) voltage at the input logic.

 

Choice of pull down and series R for PMC boards

The pull ups on the PMC board logic are 10 kΩ. So to interface the acromag a good choice would be 1.79 kΩ parallel to acromag 10 kΩ and 359 Ω for the series resistances (in configuration D)

 

Small correction to above equations

Thu Jan 25 22:00:23 2018: I didn't quite include all the stuff in the above equations.  They will give good values for cases where R1<<Rpull up  and R2<<Rpull down. Here is the full equation in the case that the pull up resistor and/or pull up reistor values are comparible to the choices needed for R1 and R2​.

R_1 = \frac{R_\textrm{pull up}}{(V_\textrm{pull up}/V_\textrm{off}-1)-R_\textrm{pull up}/(R_\textrm{pull down}+R_2)}

where Vpull up is the voltage of the pull up rail, Voff is the desired off state voltage, Rpull up is the pull up resistance of the input logic and Rpull down is the pull down resistance of the driving circuit. Likewise

R_2 = \frac{R_1(V_\textrm{excitation}/V_\textrm{on}-1)}{1+(1-V_\textrm{pull up}/V_\textrm{on})R_1/R_\textrm{pull up}}

where Vexcitation is the  high value of the driving circuit and Von is the desired on (high) voltage at the input logic. As is very likely the case the pull up voltage rail is actually the same as the required on voltage and the above equation for R2 reduces to the value in the previous section.

Its a bit cicular here R1<--> R2. Just try some values, if logic pull up and source pull down are ≥5 kΩ then the equations in the second above are fine. 

 

 

Quote:

When Craig restarted the acromag IOC yesterday the North path FSS loop engage binary channel went into a permanent latch off mode.  This is a recurring problem that can be fixed by plugging the 5 V power in line to the acromag binary channels in with the FSS control boxes unplugged. Sometimes you need to plug and unplug a few times.  

It could be an issue with the way we have used 820 Ω resistors to bring the pull up 10 kΩ down to 758 Ω. It probably should be buffered somehow.  For now its good enough to get it working, once it's powered up its fine.

As an intermediate fix I soldered a 1000 µF electrolitic cap in line with the 5V supply to give it juice when first powered up.  This seems to make the latching go away most of the time (90%) when first powering up the units. So... slight improment.

 

Attachment 1: Acromag-to-pullup-logic_options.pdf  29 kB  Uploaded Wed Jan 24 21:10:55 2018  | Hide | Hide all
Acromag-to-pullup-logic_options.pdf
ELOG V3.1.3-