40m QIL Cryo_Lab CTN SUS_Lab TCS_Lab OMC_Lab CRIME_Lab FEA ENG_Labs OptContFac Mariner WBEEShop
  PSL  Not logged in ELOG logo
Entry  Sat Dec 16 16:39:31 2017, awade, DailyProgress, BEAT, Tune up: Minor PLL and FSS tuning, lowering beat note amplitude IMG_1456.JPGScreen_Shot_2017-12-16_at_6.22.03_PM.png
    Reply  Mon Dec 18 13:49:14 2017, awade, DailyProgress, BEAT, Tune up: Minor PLL and FSS tuning, lowering beat note amplitude 
       Reply  Tue Dec 19 14:30:05 2017, awade, DailyProgress, BEAT, PID control of north cavity heater, up for 24 hours 
          Reply  Mon Jan 8 14:07:06 2018, awade, DailyProgress, TempCtrl, Cavity shield heater circuit 7x
    Reply  Mon Dec 18 15:45:26 2017, rana, DailyProgress, BEAT, Tune up: Minor PLL and FSS tuning, lowering beat note amplitude 
       Reply  Mon Dec 18 19:00:47 2017, awade, DailyProgress, BEAT, Tune up: Minor PLL and FSS tuning, lowering beat note amplitude 
          Reply  Tue Dec 19 10:26:47 2017, rana, DailyProgress, BEAT, Tune up: Minor PLL and FSS tuning, lowering beat note amplitude 
             Reply  Tue Dec 19 11:28:47 2017, awade, DailyProgress, BEAT, Tune up: Minor PLL and FSS tuning, lowering beat note amplitude 
    Reply  Thu Dec 21 16:59:21 2017, awade, DailyProgress, BEAT, Tune up: FSS settings checkup 
Message ID: 2035     Entry time: Mon Jan 8 14:07:06 2018     In reply to: 2021
Author: awade 
Type: DailyProgress 
Category: TempCtrl 
Subject: Cavity shield heater circuit 

Here are notes on the heater driver circuit for the cavity shield heaters and its schematic.  Its built in a standard busboard black box on one of their generic SMT protoboards.

The build is robust within the box, but heat sinking of MOSFETs and voltage regulators onto the casing and the various solder reworkings make the casing a little difficult to dissemble and reassemble.  

Circuitry consists of a Sallen-Key 2nd order LP filter set at 159 mHz corner, followed by an op amp buffer wrapped around a IRF630 MOSFET. I used OPA827 JFET input op amps (recommended in 40m:8125), these were the ones we actually had in stock at the time. They also have very low typical offset drift, quoted as 0.5 µV/K in the spec sheet. The schematic is attached below with an estimate of the voltage noise up to the FET buffer stage. I don't have a model of the IRF630's noise, but the largest issue is actually the very low frequency drift of the op amps and input voltage from the DAC.

So heater driver box gives two channels of 0.1 A/V conversion with some low pass filtering. Input is through two BNCs.  Output is into a Sub-D 9 connector with the following pinouts:

1-6: heater on cavity (south)

4-8: heater on cavity (north)

I checked the resistance of the south path heater.  It looks like its still hooked up but has a resistance of 85.6 Ω compared to the 156.8 Ω of the north cavity heater.

Power and current limits

The voltage-to-current conversion is made using a 10 Ω ± 1 %, 1 W, wire wound 20 ppm/K resistor (Vishay RS01A10R00FE70). The maximum current, within the 1 W power spec of the resistor is 320 mA: maximum voltage is therefore also 3.2 V. It is advisable to operate well below this to ensure the resistor is not self heating too much. I considered adding zenors to crimp the input voltage, but wasn't sure if they cause unexpected noise/behavior at the time. It would be advisable to put some kind of voltage crimp on future reworks to prevent overdriving the circuit with user error.

The logic of the FET buffer is that the op amp will adjust the voltage of the gate until the source pin matches the non-inverting input of the second op amp.  Current is sourced through the heater load (~170 Ω loading) sufficient to generate voltage across the 10 Ω sensing resistor.  The exact resistance of the heater load is unimportant to the voltage to current conversion (0.1 A/V), except where resistance is so high that the source voltage overhead is not large enough to drive the set point current into the drain.

The FET is essentially adjusting the voltage divider at the output formed between the heater load and 10 Ω sense resistor.  The set point voltage at which the heater load is saturated, i.e. where driving voltage isn't high enough to provide enough current through a resistive heater, is given by

V_\textrm{set} = \frac{V_{cc}-V_{FET,GS}}{R_\textrm{load}/R_s+1}

where V_set is the max set point voltage at the non-inverting input of the op amp. Vcc is the supply voltage, V_FET,GS is the gate to source potential drop, Rload is the heater load attached to the drain pin, and, Rs is the sensing resistor.

The north cavity shield heater impedance is 156 Ω. Thus maximum drive voltage is 0.867V, this means a drive current of 87 mA.  The maximum heating is therefore P = I^2R = 1.17 W. Initially we expected cavity heating requirements to be 0.8 W, so it should be sufficient, although it might have been a good idea to have a little more overhead. Presently the heater driver is st to 0.7692 W for a 66 MHz offset of the north from the south cavity.  


The Sallen-Key low pass is only to cut off any higher frequency noise from the DAC.   Very low frequency drift in the driver circuit is another issue. From Craig's previous estimates from CTE (PSL:2027) the temperatures to cavity frequency conversion is 155 MHz/K.  The OPA827 has a typical offset voltage 75 µV with a drift of 0.5 µV/K (max 2.0 µV/K).  To first order set point voltage drift to heating power fluctuation ( due to op amps) is

\Delta P_\textrm{drift} = 2 \delta V_s V_s R_\textrm{load}/R_s^2 \approx 2.2 \delta V_s\Delta P_\textrm{drift} = 2 \delta V_s V_s R_\textrm{load}/R_s^2 \approx 2.2 \delta V_s [W/V]

Where delta V_s is the drift of the set point voltage and R_load is the heater impedance (156 Ω).  For worst case 4 µV/K drift (in op amps) we should see 8.7 µW/K change over a heating power of about 700 mW, or 12 ppm/K. 

The sensing resistor may also have small temperature drift.  Its rated to 10 Ω ± 1% with a 20 ppm/K drift. Drift in power output to first order is

\Delta P_\textrm{drift} = -2(\delta R_s/R_s)\left(Vs/R_s\right)^2V_\textrm{load} = -2(\delta R_s/R_s) \times P_\textrm{heater}

So a drift of 20 ppm/K means a heater power output change of -40 ppm/K in power or 28 µW/K over heating power of about 700 mW.

It is likely that the dominant source of very-LF drift in the heater will probably come from the input voltage from the DAC.  The Acromag XT1541 8 Ch output Ethernet module has a spec of ± 50 ppm/K output ambient temperature drift. This would make its output heating drift of order ± 110 µW/K out of 700 mW or 157 ppm/K. 

Estimating north shield temperature

At this stage we are not sure what the true temperature of the north cavity is.  The plan is to step the north heater power down by 0.2 W with the FSS locked and track the shift in the slow laser voltage overnight.  From there we can estimate the thermal settling time and temperature. The facts that we are missing is the true effective emissivity. See known heater shield properties in PSL:1737). First order heat flux as a function of temperature above vacuum can is* 

\Delta Q = \varepsilon_\texrm{Cu} \sigma A T_\textrm{can}^3\delta T

Where \varepsilon_\textrm{Cu} is emissivity of copper 0.03 to 0.1 depending on degree of polish and oxidation. \sigma is Stefan–Boltzmann constant 5.67e-8 [W/m^2/K^4] and A is the area exposed to radiative transfer. Estimating emissivity of 0.05 and vacuum can temperature of 303 K this would give 6.5e-3 W/K.  Doesn't really make sense. We need a measurement, or a sensor.

* This is ignoring cylindrical geometry.

Implementing a PID

Nope. I didn't do this.  I tried for a while to tune this over the Christmas break, but the time constants are very long (30 mins to 60 min depending on the heater step). After turning it off the PID I found that the once the heater settled, an acromag set point voltage of 0.69774 V (0.7692 W) gave a beat note of ~66 MHz drifting around in a range of 5-10 kHz over the course of 30 mins.  This is a task for the todo list: look around for an auto tuner or make a model of the plant to speed up the tuning.

Attachment 1: Basic-two-channel-heater-driver.pdf  54 kB  Uploaded Mon Jan 8 18:32:30 2018  | Hide | Hide all
Attachment 2: LISO_model_PSLlabLNHeaterUptoIRF630Mosfet.png  74 kB  Uploaded Mon Jan 8 18:34:42 2018  | Hide | Hide all
Attachment 3: DSCF3508.JPG  2.328 MB  Uploaded Mon Jan 8 18:54:21 2018  | Hide | Hide all
Attachment 4: DSCF3509.JPG  2.377 MB  Uploaded Mon Jan 8 18:54:39 2018  | Hide | Hide all
Attachment 5: DSCF3510.JPG  2.418 MB  Uploaded Mon Jan 8 18:54:51 2018  | Hide | Hide all
Attachment 6: DSCF3506.JPG  4.225 MB  Uploaded Mon Jan 8 18:55:12 2018  | Hide | Hide all
Attachment 7: DSCF3507.JPG  4.157 MB  Uploaded Mon Jan 8 18:55:39 2018  | Hide | Hide all
ELOG V3.1.3-