40m QIL Cryo_Lab CTN SUS_Lab TCS_Lab OMC_Lab CRIME_Lab FEA ENG_Labs OptContFac Mariner WBEEShop
  PSL  Not logged in ELOG logo
Entry  Fri Sep 8 00:32:20 2017, awade, Summary, FSS, Schematic block diagram FSS loops CTN_FSS_south_blockdiagram.pdf
    Reply  Thu Sep 14 21:54:26 2017, awade, Summary, FSS, FSS modifications: series resistance (R1 and R2) to monitor points on servo board D040105 
       Reply  Mon Sep 18 00:46:08 2017, rana, Summary, FSS, FSS modifications: series resistance (R1 and R2) to monitor points on servo board D040105 
          Reply  Mon Sep 18 13:34:13 2017, awade, Summary, FSS, FSS modifications: series resistance (R1 and R2) to monitor points on servo board D040105 
             Reply  Tue Oct 10 00:49:34 2017, awade, Craig, Summary, FSS, Replacing U3 on north path (2010:005) FSS servo board. 20171009_220549_Ser6_ComPathTP1toTP5_09-10-2017_175407.pdffmoenfipkniealnd.png20171009_DebuggingNorthPathServoBoard.tar.gz
    Reply  Mon Oct 2 12:30:15 2017, rana, Summary, FSS, LISO & mfil 
       Reply  Wed Oct 18 11:19:15 2017, awade, Summary, FSS, Comparing south TF to LISO model TTFSS_schematics_awades_hand_notes.pdf001.pdf20171017_South_FSSTFs.tar.gz
          Reply  Wed Oct 18 15:42:59 2017, awade, Summary, FSS, Comparing south TF to LISO model 
             Reply  Mon Oct 23 15:05:44 2017, awade, Summary, FSS, Comparing south TF to LISO model Ser7_South_MainBoard_compiledTF.pdfSer5_North_MainBoard_compiledTF.pdf2017-10-20_18.04.18.jpg
                Reply  Wed Oct 25 23:15:51 2017, awade, Craig, Summary, FSS, Comparing south and north TF to LISO model South_MainBoard_EXC-30dBm_compiledTF.pdfNorth_MainBoard_EXC-30dBm_compiledTF.pdfFSS_all.tar.gz
Message ID: 1958     Entry time: Wed Oct 25 23:15:51 2017     In reply to: 1954
Author: awade, Craig 
Type: Summary 
Category: FSS 
Subject: Comparing south and north TF to LISO model 

[awade, Craig]

Craig retook the transfer functions of both north and south boards today with 7 mVrms (-30 dBm) input signal into TP1. I've plotted and they are attached below. 

There is a sign flip in phase in the north path stage 5 due to the flipper switch being in the opposite state.  Things seem to aggree except for the EOM final stage 3.  We need to check the liso model here and also the actual components on the board.  As noted by Craig in PSL:1956, some of the capacitors in the zeros of the main op amp stages are higher value than in the schematic (twice as much).  This pushes the frequency down, we actually probably want to go in the oposite direction. We also can't see the EOM path notch in the liso model. That is a red flag.

Fil file and plots attached. The rest is commited into the ctn_noisebudget and ctn_labdata gitlabs.

 

 

Attachment 1: South_MainBoard_EXC-30dBm_compiledTF.pdf  1.212 MB  | Hide | Hide all
South_MainBoard_EXC-30dBm_compiledTF.pdf South_MainBoard_EXC-30dBm_compiledTF.pdf South_MainBoard_EXC-30dBm_compiledTF.pdf South_MainBoard_EXC-30dBm_compiledTF.pdf South_MainBoard_EXC-30dBm_compiledTF.pdf South_MainBoard_EXC-30dBm_compiledTF.pdf South_MainBoard_EXC-30dBm_compiledTF.pdf South_MainBoard_EXC-30dBm_compiledTF.pdf
Attachment 2: North_MainBoard_EXC-30dBm_compiledTF.pdf  1.209 MB  | Hide | Hide all
North_MainBoard_EXC-30dBm_compiledTF.pdf North_MainBoard_EXC-30dBm_compiledTF.pdf North_MainBoard_EXC-30dBm_compiledTF.pdf North_MainBoard_EXC-30dBm_compiledTF.pdf North_MainBoard_EXC-30dBm_compiledTF.pdf North_MainBoard_EXC-30dBm_compiledTF.pdf North_MainBoard_EXC-30dBm_compiledTF.pdf North_MainBoard_EXC-30dBm_compiledTF.pdf
Attachment 3: FSS_all.tar.gz  1 kB
ELOG V3.1.3-