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Entry  Tue Oct 3 17:53:32 2017, awade, Craig, DailyProgress, FSS, Damage to the south interface board logic and debugging FSS north interface box power issues 
    Reply  Thu Oct 5 23:19:56 2017, awade, Craig, DailyProgress, FSS, Repairs to FSS interface boxes. 2017-10-05_16.13.12.jpg
       Reply  Fri Oct 6 21:18:19 2017, awade, DailyProgress, FSS, Repairs to FSS interface boxes. 
Message ID: 1943     Entry time: Tue Oct 3 17:53:32 2017     Reply to this: 1944
Author: awade, Craig 
Type: DailyProgress 
Category: FSS 
Subject: Damage to the south interface board logic and debugging FSS north interface box power issues 

Addressing issues with south interface box digital logic

Some time last week when we reconnected the FSS boxes to the slow channel controls we realized that I had accidentally routed 24 V into the binary engage channels from the Acromag cards. The Acromag cards were ok, but the binary multiplexer chip U3 (HCT157) on the interface board ('south' serial number 2010:005) were not ok.  Pin three on U3 did not go low (0.6V) when the driving excitation voltage was off; when toggling the excitation voltage it went from about 3.6 V to 5 V (instead of 0.6 V to 5 V).  This meant that the following board logic was inoperable. Some repair work is in order.

I've ordered another SN74HCT157 SOIC chip from mouser to replace the likely fried chip.  It arrived on campus yesterday and is still working its way through Caltech logistics.

For rework jobs, like replacing this surface mount component, I also ordered a hot air iron and low melt solder flux and alloy to assist.

The north path (serial number 2010:001) logic has not been tested due to power issues detailed below.

North interface box low noise power board issues (D0901846, rev C, serial 2010:001)

Yesterday Craig and I also looked at the north FSS interface box. After a bit of poking around we found that there were no negative supplies to the chips on the north interface board. The low noise power LIGO-(D0901846-v4, revision C) generates a ±15 V from a 10V precision reference IC (LT1021-10) that is buffered and also separately inverted for driving the negative rail.  The LT1021-10 (U4) was fine and the inverted stage was also producing -10 V.  

I've traced the issue back to somewhere around U3 (an AD829 op amp) and Q1 (a PNP transistor D45H11). All voltages seem to be supplied appropriately to these sub-circuits but the output voltage is -1.77 V instead of -15 V. Its not clear what the mode of failure is here, but at least it is localized.  It also looks like there has been a little rework done before on U3. Koji tells me that he and Tara did some diagnostics of a power issue when it was previously hooked up with the wrong polarity. I can't find this in the elog either by searching the DCC number or any combination of {Low,noise,power,board} but I may be missing it.

I will have a bit more or a poke around and a think about how to point point the exact failure but will get a AD829 and and D45H11 ready to drop in as replacements.

3rd FSS box

I've also tracked down the third set of TTFSS interface + field boxes that was at the 40m.  This will be useful as a temporary replacement and reference for what the working version should do. 

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