So I had a look at your circuit to see what was going on. I found that there was a strange offset at the instrument op amp (AD620) stage AND on your two LP filter buffering op amps.
So with the AD620, it has a dedicated 'ref' pin (pin 5). This sets the offset of the op amps output and can be used to reference the amplified output to whatever voltage you like (to within the range of the voltage rails). When I looked it was connected to ground, so that seemed right. I moved the AD620 to the larger breadboard to make things easier (I moved whatever you had set up with the AD829 one row along, sorry if you needed that). Once moved it worked fine, when I terminated the input (or shorted + and - of the op amp) it gave zero offset voltage. I'm not sure what changed, but it could have been a loose connection somewhere. So that stage seems good now. If you want some offset adjustability, this is the place to add it.
The two AD743 buffers for the active LP filter where introducing an offset of their own. You had all the unused pins connected to ground. This seems sensible most of the time. However, the AD743s have two pins that are dedicated to null function. These are supposed to be tied to the negative rail by an adjustable voltage bridge. If you ground them, they might do strange things as they both have zero voltage instead of some difference between zero and the negative rail. For more info just search for null in the datasheet. I removed the links to ground and the offset went away. If you really want to fine tune the offset you can make a voltage divider there but a potentiometer is highly not recommended for this stuff, it will make noise and pain down the track and not be stable. I think leaving the pins 1 and 5 open should be fine.
I didn't look at the noise, but the transfer function loops fine to me. Its giving about the right corner frequency (0.15 Hz) the 1/f^2 slope and above 320 Hz the attenutation is -100 dB. Looks good. Maybe stick the buffer in there, take some more transfer functions and have a look at the noise, probing at each stage of the current driver circuit (i.e. after the AD620, after the LP filter and after the buffer) with the input shorted with 50Ω.
We need to make a decision in choosing a LP filter stage op amp that isn't the AD743. The frustration is that manufactures don't just quote a common set of frequencies or sets of parameters that you can plot with. Zach Korth has obsessed a lot on this subject and made a really interesting post on the subject in PSL:1752 (see lower half of post). If you read nothing else, this week, read that. Also here is an almost helpful parameter search: http://www.analog.com/en/parametricsearch/11089#/p5056=JFET . The best metric should be 0.1 to 1 Hz rms noise as that should be indicative of LF performance. However, as you see in Zach's post, the slope of the noise and corner frequency of roll up differs between types and designs of op amps. The opacity of specifications in these components is frustrating. It is almost as if they are obfuscating so they can sell less good components to people who don't know what they are doing.
The function that Zach mentions in PSL:1752 is somewhere on the 40m SVN. I think you'll find it if you poke around in SVN:/trunk/zach/tools/ .
The burning last time came from the load resistor, which wasn't rated for high power. I made a test load from resistive tape that Andrew found and a heatsink, and this worked with the BUF634 output. A picture:
The LP buffer filter is adding a DC offset of -0.5V. This happens in the first stage even if the two op amp chips are swapped, and it also happens when you just ground the input signal. This is what the output looks like:
Strangely, I know this wasn't happening the first time I built and tested the circuit using the 10uF capacitors (see elog 1768), and now it seems to be there no matter what capacitors I use.
I tried correcting for this offset in two ways.
1. First I tried to add an inverting input (from a voltage divider on the power rail) to cancel out the offset, adjusting the gain appropriately, but this added an insane amount of noise to the signal. I tried this on both the first and second stage.
2. I then tried the method outlined in the following document: http://www.ti.com/lit/an/sloa097/sloa097.pdf, but this made no difference at all.
I also realized that I had been using the wrong input resistors (1k instead of 100k) before, which is why the cutoff frequency was so high before. I put in the 100k resistors, and with the 10uF capacitors, it gives a response that kind of makes sense (cutoff around 4Hz), except the ridiculously low gain which may be due to the DC offset (which unfortunately persists).
I am thinking about other ways to cancel out the DC offset. I think adding a third stage would be even worse than attempt 1. It's possible to just correct for this offset in software (especially since this offset would probably be different amongst the different circuits), but I don't know if this would be good practice?