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Entry  Tue Nov 22 13:46:29 2016, yinzi, DailyProgress, TempCtrl, Circuit updates IMG_7137.JPGIMG_0432.JPGIMG_1824.JPG
    Reply  Tue Nov 22 20:19:42 2016, awade, DailyProgress, TempCtrl, Circuit updates: Heater driver 
    Reply  Tue Nov 22 20:19:47 2016, awade, DailyProgress, TempCtrl, Circuit updates: Heater driver 
       Reply  Wed Nov 30 15:29:06 2016, yinzi, DailyProgress, TempCtrl, Circuit updates: Heater driver moved to protoboard, some data 14x
Message ID: 1773     Entry time: Tue Nov 22 13:46:29 2016     Reply to this: 1774   1775
Author: yinzi 
Type: DailyProgress 
Category: TempCtrl 
Subject: Circuit updates 

The burning last time came from the load resistor, which wasn't rated for high power. I made a test load from resistive tape that Andrew found and a heatsink, and this worked with the BUF634 output. A picture:

The LP buffer filter is adding a DC offset of -0.5V. This happens in the first stage even if the two op amp chips are swapped, and it also happens when you just ground the input signal. This is what the output looks like:

Strangely, I know this wasn't happening the first time I built and tested the circuit using the 10uF capacitors (see elog 1768), and now it seems to be there no matter what capacitors I use.

I tried correcting for this offset in two ways.

1. First I tried to add an inverting input (from a voltage divider on the power rail) to cancel out the offset, adjusting the gain appropriately, but this added an insane amount of noise to the signal. I tried this on both the first and second stage.

2. I then tried the method outlined in the following document: http://www.ti.com/lit/an/sloa097/sloa097.pdf, but this made no difference at all.

I also realized that I had been using the wrong input resistors (1k instead of 100k) before, which is why the cutoff frequency was so high before. I put in the 100k resistors, and with the 10uF capacitors, it gives a response that kind of makes sense (cutoff around 4Hz), except the ridiculously low gain which may be due to the DC offset (which unfortunately persists).

I am thinking about other ways to cancel out the DC offset. I think adding a third stage would be even worse than attempt 1. It's possible to just correct for this offset in software (especially since this offset would probably be different amongst the different circuits), but I don't know if this would be good practice?

ELOG V3.1.3-