I don't think we can say for sure. I was just talking to EricQ about this, he said the glitches were often seen when changing the alignment offsets when aligning the arm. I am pretty sure I have seen the ETMX alignment change abruptly since the Ruby Standoff replacement (the Oplev spot just slides across the MEDM display rapidly), but I can't find an elog where I've put in details. I also haven't done a whole lot of work with the arm cavities where I would have noticed this problem. There is this test that Eric did, and it didn't throw up any red flags. But the suspension can be well behaved for weeks at a time before this problem pops up again.

There was also the flaky power connection to the timing card on the ETMX expansion chassis which was fixed only recently, after which there has been no systematic investigation of the status of ETMX.

If it is true that these events are caused by strain building up in the suspension wire, I wonder how we can take systematic steps to avoid it. From what I remember of the SOS assembly procedure, the (unglued) standoff is slid along the optic with the wire under slight tension until the wire slips into the groove on the standoff. Then the tension in the wire is adjusted till the optic is pitch balanced and at the desired height. But it is easy to imagine imprinting some torsional stresses in the (40 um?) wire during this process of looping it around under the optic and placing it in the groove. But perhaps this mechanism makes a negligible contribution to the effect we are seeing, and some other mechanism is responsible in this case.

Now that all the CDS overview lights are green, I decided to switch back the coil driver outputs to their original state so that the MC optics could be damped and the IMC relocked. I also restored the static PIT/YAW bias values to their original values.

MC1 has been quiet over the last couple of days, lets see how it behaves in the next few days. In all the glitches I have observed, if the IMC is locked and WFS loops are enabled, the loops are able to correct for the DC misalignment caused by the glitch. But the mcwfs off script is currently set up in such a way that the output history is cleared between IMC locks. I made two copies of the mcwfson/mcwfsoff scripts, called mcwfsunhold/mcwfshold respectively. They live in /opt/rtcds/caltech/c1/scripts/MC/WFS. I've also modified the autolocker script to call these modified scripts, such that when the IMC loses lock, the WFS servo outputs are held, while the input is turned off. The hope is that in this configuration, the autolocker can catch a lock even if there is a glitch on MC1.

I haven't tried locking the arms yet, but I think other IFO work discussed at the meeting (like arm loss estimation / cavity scans etc) can proceed.

Seems like this modification didn't really work. There were several large MC1 glitches, and one of them misaligned MC1 so much that the IMC didn't relock for the last ~6 hours. I re-aligned MC1 manually, and now it is locked fine.

that's why the Autolocker clears the outputs; we don't want to be holding the offsets from the last ms of lock when it was all messed up; instead it would be best to have a slow (~mHz) relief script that takes the WFS controls and puts them onto the MC SUS sliders. This would then re-align the MC to the input beam rather than the input to the MC. Which is not the best idea.

They are synchronised tiny glitches. They are not mechanical.
 

[ericq, gautam]

Tonight, we decided to double-check the POX counts-to-meters conversion.

It is unclear when this was last done, and since I modified the coil driver electronics for the ITMs and BS recently, I figured it would be useful to get this calibration done. The primary motivation was to see if we could resolve the discrepancy between the current ALS noise (using POX as a sensor) compared to the Izumi et. al. plot.

Because we are planning to change the coil driver electronics further soon anyways, we decided to do the calibration at a single frequency for tonight. For future reference, the extension of this method to calibrate the actuator over a wider range of frequencies is here. The procedure followed, and the relevant numbers from tonight, are as follows.

Procedure:

1. Set dark offsets on all DCPDs and LSC PDs.
2. Look at the free swinging Michelson signal on ASDC.
   • For tonights test, ASDC was derived from the AS55 photodiode.
   • The AS110 photodiode actually has more light on it, but we think that the ADC that the DCPD board is interfaced to is running on 0-2V rather than 0-10V, as the signal seemed to saturate around 2000 counts. It is unclear whether the actual photodiode is saturating, to be investigated.
   • So we decided to use ASDC from AS55 photodiode with 15dB whitening gain.
   • There is also some issue with the whitening filter (not whitening gain) on ASDC - engaging the whitening shifts the DC offset. This has to be investigated while we get stuck into the LSC electronics.
3. Look at the peak-to-peak swing of ASDC. Use algebraic expression for reflected power from Michelson interferometer to calibrate the ASDC slope at Michelson half-fringe. For the test tonight, ASDC_max = 1026 counts, ASDC_min = 2 counts.
4. Lock the Michelson at half-fringe, with ASDC as the error signal.
   • Zero out the MICH elements in the RFPD input matrix.
   • Set the matrix element from ASDC to MICH in the DCPD LSC input matrix to 1.
   • The servo gain used was +0.005 on the MICH_A servo path.
   • A low-frequency boost was turned on.
5. Use the sensing matrix infrastructure to drive a line in the optic of interest.
   • Tonight, we looked at ITMX and ITMY.
   • The line was driven at 311.1Hz, and the amplitude was 300 counts.
   • Download 60secs of ASDC data, demodulate at the driven frequency to find the peak height in counts, and using the slope of ASDC (in cts/m) at the Michelson half-fringe, calculate the actuator gain in m/cts.
   • ITMY: 2.55e-9 / f^2 m/count
   • ITMX: 2.65e-9 / f^2 m/count
   • These numbers kind of make sense - the previous numbers were ~5nm/f^2 /ct, but I removed an analog gain of x3 in this path. Presumably there has been some change in the N/A conversion factor - perhaps because of a change in the interaction between the optics' face magnets and the static magnetic field in the OSEMs?
6. Lock the arms with POX/POY, and drive the newly calibrated ITMs.
   • So we know how many meters we are driving the ITMs by.
   • Looking at POX/POY, we can calibrate these into meters/count.
   • Both POX and POY were whitened.
   • POX whitening gain = +30dB, POY whitening gain = +18dB.
   • ITMX and ITMY were driven at 311.1Hz, with amplitude = 2counts.
   • Download 60 secs of data, demodulate at the drive frequency to find the peak height, and use the known ITM actuator gains to calibrate POX and POY.
   • POX: 7.34e-13 m / count (approx. 5 times less than the number in the Foton filter bank in the C1:CAL-CINV model).
   • POY: 1.325e-13 m / count
   • We did not optimize the demod phases for POX/POY tonight. 

Once these calibrations were updated, we decided to control the arms with ALS, and look at the POX spectrum. Y-arm ALS wasn't so stellar tonight, especially at low frequencies. I can see the GTRY spot moving on the CCD monitor, so something is wonky. To be investigated. But the X arm ALS noise looked pretty good.

Seems like updating the calibration did the job; see the attached comparison plot.

Last night, while we were working on the ALS, I noticed the GTRY spot moving around (in PITCH) on the CCD monitor in the control room at ~1-2Hz. The operating condition was that the arm was locked to the IR, and the PSL green shutter was closed, so that only the arm transmissions were visible on the CCD screens. There was no such noticable movement of the GTRX spot. When looking at the out-of-loop ALS nosie in this configuration (but now with the PSL green shutter open of course), the Y arm ALS noise at low frequencies was much worse than the X arm.

Today, I looked into this a little more. I first checked that the Y-endtable enclosure was closed off as usual (as I had done some tweaking to the green input pointing some days ago). There are various green ghost beams on the Y-endtable. When time permits, we should make an effort to cleanly dump these. But the enclosure was closed as usual.

Then I looked at the in-loop Oplev error signal spectra for the ITMY and ETMY Oplev loops. There was high coherence between ETMYP Oplev error signal and GTRY. So I took a loop transfer function measurement - the upper UGF was around 3.5Hz. I increased the loop gain such that the upper UGF was around 4.5Hz, with phase margin ~30degrees. Doing so visibly reduced the angular movement of the GTRY spot on the CCD. Attachment #1 shows the Oplev loop TF after the gain increase, while Attachment #2 compares the GTRX and GTRY spectra (DC value is approximately the same for both, around 0.4). GTRY still seems a bit noisier at low frequencies, but the out-of-loop ALS noise for the Y arm now lines up much more closely with its reference trace from a known good time. 

MC1, MC2 and MC3 damping turned off to see glitching action at 9:57am

I re-enabled the MC SUS damping and IMC locking for some IFO work just now.

Summary:

The signal path for the ASDC signal is AS55 PD --> D990543 (interface board) --> D990694 (whitening board) --> D000076 (AA board) --> ADC Ch 31. Everything in this signal chain should be able to handle signals in the range +/- 10V, which should correspond to the full range of our +/-10V, 16bit ADCs. But the ASDC signal seems to saturate at ~2000 counts (i.e. turning up the analog whitening gain doesn't make the signal get any bigger than this). I investigated this a little more today.

Details:

• The ASDC signal is derived from the AS55 photodiode. According to the schematic, the Op27 that supplies this voltage is powered by +/- 15V, so the output should be able to swing between at least +/- 12V.
• The DC signal goes from the DB15 connector on the side of the PD to the LSC electronics rack, 1Y2, where it is interfaced with an LSC PD Interface Card, D990543. Again, per the schematic, the Op27 driving this voltage is powered by +/- 15V, and so the available output voltage swing should be greater than +/-12V.
• The D990543 output is to its backplane connector. There is an adaptor board hooked up to the backplane that makes these outputs available to a LEMO connector. A LEMO-SMA cable then pipes this output to a D990694.
  • I decided to test the functionality of this board.
  • Disconnected the SMA ASDC input signal (CH8 on the board).
  • Drove that channel with an SR function generator and gradually turned up the Vpp of the input signal (sine wave at 145Hz).
  • Monitored the ASDC channel on dataviewer while doing this.
  • Saw that the ASDC signal saturated at ~2000 counts. Turning up the signal amplitude did not have any effect.
• From the whitening board, the signal goes through an anti-aliasing module (D000076). The final stage LT1125s on these boards should also be supplied with +/-15V.

So the problem lies somewhere downstream of the D990694. There are other anomalous behaviours of this channel - e.g. engaging the analog whitening filters changes the DC offset of the signal. I am going to pull out this board to check it out.

Why does this matter? I want to calibrate the ASDC level (and eventually the other PD DC signals as well) into Watts. This is useful for IFO diagnostics, noise budgeting the shot noise level etc.

According to the AS55 schematic, the DC transimpedance is 66.7 ohms. I claim that the DC power on the AS55 photodiode during a DRMI (no arms) lock is ~1mW. The C30642 photodiode (InGaAs) responsivity is ~0.8 A/W. So I'd expect ~50mV to be the signal level into the ADC (assuming gain of all the other electronics in the signal chain at the start of this elog is unity). This corresponds to ~163 counts (since the ADC conversion factor is 2^16 counts over 20volts). The DC signal level I observed is ~200 counts. So things seem roughly consistent.

*Note: Despite my above statement, I don't think it is true that the AS110 PD has more light on it - the BS splitting the light between

AS55 and AS110 PDs is a 50-50 BS, and using the crude method of putting an Ophir power meter in front of both PDs and

monitoring the power while the Michelson was swinging around freely showed roughly the same maximum value.

We've been talking about increasing the series resistance for the coil driver path for the test masses. One consequence of this will be that we have reduced actuation range.

This may not be a big deal since for almost all of the LSC loops, we currently operate with a limiter on the output of the control filter bank. The value of the limit varies, but to get an idea of what sort of "threshold" velocities we are looking at, I calculated this for our Finesse 400 arm cavities. The calculation is rather simplistic (see Attachment #1), but I think we can still draw some useful conclusions from it:

• In Attachment #1, I've indicated with dashed vertical lines some series resistances that are either currently in use, or are values we are considering.
• The table below tabulates the fraction of passages through a resonance we will be able to catch, assuming velocities sampled from a Gaussian with width ~3um/s, which a recent ALS study suggests describes our SOS optic velocity distribution pretty well (with lcoal damping on).
• I've assumed that the maximum DAC output voltage available for length control is 8V.
• Presumably, this Gaussian velocity distribution will be modified because of the LSC actuation exerting impulses on the optic on failed attempts to catch lock. I don't have a good model right now for how this modification will look like, but I have some ideas.
• It would be interesting to compare the computed success rates below with what is actually observed.
• The implications of different series resistances on DAC noise are computed here (although the non-linear nature of the DAC noise has not been taken into account).

So, from this rough calculation, it seems like we would lose ~25% efficiency in locking the arm cavity if we up the series resistance from 400ohm to 1kohm. Doesn't seem like a big deal, becuase currently, the single arm locking

Summary:

• SOS solidworks model is nearly complete
  • Having trouble with the design of the sensor/actuator head assembly and the lower clamps
• After Gautam's suggestion, installed Abaqus on computer. Teaching it to myself to eventually do FEM analysis and find resonant frequency of the system
  • Goal is to replicate frequency listed in the SOS documents to confirm accuracy of computer model, then replace guide rods with sapphire prisms and change geometry to get same results

Questions:

• How accurate do the details (like fillet, chamfer, placement of little vent holes), and material of the different SOS parts need to be in the model?
• If I could get pictures of the lower mirror clamp (document D960008), it would be helpful in making solidworks model. Document is unclear. Same for sensor/actuator head assembly. 

If you go through this thread of elogs, there are lots of pictures of the SOS assembly with the optic in it from the vent last year. I think there are many different perspectives, close ups of the standoffs, and of the OSEMs in their holders in that thread.

This elog has a measurement of the pendulum resonance frequencies with ruby standoffs - although the ruby standoff used was cylindrical, and the newer generation will be in the shape of a prism. There is also a link in there to a document that tells you how to calculate the suspension resonance frequencies using analytic equations.

I've been observing this for a few days: ETMX's DC alignment seems to drift by so much that the previously well aligned X arm cavity is now totally misaligned.

The wall StripTool trace shows that both the X and Y arms were locked with arm transmissions around 1 till c1psl conked out - so in the attached plot, around 1400 UTC, the arm cavity was well aligned. So the sudden jump in the OSEM sensor signals is the time at which LSC control to the ETM was triggered OFF. But as seen in the attached plot, after the lockloss, the Oplev signals seem to show that the mirror alignment drifted by >50urad. This level of drift isn't consistent with the OSEM sensor signals - of course, the Oplev calibration could be off, but the tension in values is almost an order of magnitude. The misalignment seems real - the other Oplev spots have stuck around near the (0,0) points where I recentered them last night, only ETMX seems to have undergone misalignment.

Need to think about what's happening here. Note that this kind of "drift" behaviour seems to be distinct from the infamous ETMX "glitching" problem that was supposed to have been fixed in the 2016 vent.

I should've put in the SUSPIT and SUSYAW channels in the previous screenshot. I re-aligned ETMX till I could see IR flashes in the arm, and also was able to lock the green beam on a TEM00 mode with reasonable transmission. As I suspected, this brought the Oplev spot back near the center of it's QPD. But the answer to the question "How much did I move the ETM by" still varies by ~1 order of magnitude, depending on if you believe the OSEM SUSPIT and SUSYAW signals, or the Oplev error signals - I don't know which, if any, of these, are calibrated.

Best to just calibrate the ETM OL in the usual way. I bet the OSEM outputs have a cal uncertainty of ~50% since the input matrix changes as a function of the DC alignment. Still, a 30 urad pitch mis-alignment gives a (30e-6 rad)(40 m) ~ 1 mm beam spot shift. This would be enough to flash other modes, but it would still be easy to lock on a TEM00 like this. I also doubt that the OL calibration is valid outside of some region near zero - can easily check by moving the ETM bias sliders.

What we still don't know is if this is due to Johannes/Aaron working at the ETMX rack (bumping some of the flaky coil cables and/or bumping the blue beams which support the stack). Adding or substracting weight from the stack supports will give us an ETM mis alignment.

I've often gotten confused by the labeling on the SUS MEDM screens about the coil "Vmon" fields - they're labelled as "30 Hz HPF", and indeed this is one of the many readbacks available on the coil driver board. But the actual EPICS channel that is being displayed in this field is from the "EPICS VMON" monitor point on the coil driver board. It has a gain of 1/2, so the actual voltage going to the coil is twice the channel value. Today, I fixed the SUS master screen to avoid this confusion - new labeling is shown in Attachment #1.

The ETMX  Sorrenson power supply -15V was running at -13.9V

Seems like there was a 5.3 magnitude EQ ~10km from us (though I didn't feel it). All watchdogs were tripped so our mirrors definitely felt it. ITMX is stuck (but all the other optics are damping fine). I tried the usual jiggling of DC bias voltage but ITMX still seems stuck. Probably a good sign that the magnet hasn't come off, but not ideal that I can't shake it free..

edit: after a bit more vigorous shaking, ITMX was freed. I had to move the bias slider by +/-10,000 cts, whereas initially I was trying +/-2000 cts. There is a tendency for the optic to get stuck again once it has been freed (while the optic's free swinging motion damps out), so I had to keep an eye out and as soon as the optic was freed, I re-engaged the damping servos to damp out the optic motion quickly.

Satellite amplifiers labeled with date. Old labels left on.

[SV,KA,RXA,GV]

The stack weight measurement is going on at EX. ETMX watchdog is shutdown. Area is off limits over the weekend until the test is finished.

Not related to this work, but the dog clamps used on the EX table have to be re-positioned such that the clamping force is better distributed. The 2" beam splitter mount used to pick off a portion of the EX NPRO beam to the fiber has to be rotated. Also, there was a M6.9 EQ in Hawaii while we were doing this work it seems..

[steve,gautam]

We tried to estimate what the load cell measurement should yield. Here is the weight breakdown (fudge factor for Al table is to try and account for tapped holes):

• Steve pointed out that there is some material removed from the stack legs for stability (hollows into which the viton springs fit). These countersinks have dimensions of diameter=2", height=1.75". So if we assume each leg has 10% less mass, the total weight becomes ~4600lbs.
• I think we will need to use one more load cell (i.e. total 4) for this measurement (we have more load cells, just need to setup one more controller).
• Steve is looking into acquiring some low profile jacks to deal with the fact that we only have limited travel range on the overall stack height because of the bellows.
• A useful document, from which we pulled some numbers (which also look reasonable using estimated dimensions and density calculations): P952005

I'm working near 1X5 and there is an SR785 adjacent to the electronics rack with some cabling running along the floor. I plan to continue in the evening so please leave the setup as is.

During the course of this work, I noticed the +15V Sorensen in 1X6 has 6.8 A of current draw, while Steve's February2018 label says the current draw is 8.6A. Is this just a typo?

Steve: It was most likely my mistake. Tag is corrected to 6.8A

I'm still in the process of electronics characterization, so the SR785 is still hooked up. MC3 coil driver signal is broken out to measure the output voltage going to the coil (via Gainx100 SR560 Preamp), but MC is locked.

The ITMX oplev still clipping

To obtain a colored version with good contrast of the grayscale image of scattering of light by dust particles on the surface of test mass, got using GigE camera. The original and colored images are attached here.

Seems like as a result of my recent poking around at 1X6, MC3 is more glitchy than usual (I've noticed that the IMC lock duty cycle seems degraded since Tuesday). I'll try the usual cable squishing voodo.

gautam 8.15pm: Glitches persisted despite my usual cable squishing. I've left PSL shutter closed and MC watchdog shutdown to see if the glitches persist. I'll restore the MC a little later in the eve.

Per discussion today eve, barring objections, I will do the following tomorrow morning:

1. Remove ETMX coil driver board from 1X9
   • Change series resistances on the fast path to 2x4k in parallel. One will be snipped off once we are happy we can still lock.
   • Remove AD797s, potentiometers.
   • Thick film-->thin film for important components.
2. Remove ETMX de-whitening board from 1X9
   • Remove x3 analog gain.
   • Thick film-->thin film for important components.

I finished the re-soldering work today, and have measured the coil driver noise pre-Mods and post-Mods. Analysis tomorrow. I am holding off on re-installing the board tonight as it is likely we will have to tune all the loops to make them work with the reduced range. So ETMX will remain de-commissioned until tomorrow.

I decided to take a quick look at the data. Changes made to the ETMX coil driver board:

1. Fast path series resistances: 400 ohm ---> 2.25 kOhm (= 2x 4.5 kohm in parallel). Measured (with DMM) resistance in all 5 paths varied by less than 3 ohms (~0.2%).
2. All thick film resistors in signal (fast and bias) paths changed to thin film.
3. AD797 ---> Op27 for monitor output.
4. Above-mentioned mon output (30Hz HPF-ed) routed to FP LEMO mon via 100ohm for diagnostic purposes.
5. 4x Trim-pots in analog path removed. 

I also took the chance to check the integrity of the LM6321 ICs. In the past, a large DC offset on the output pin of these has been indicative of a faulty IC. But I checked all the ICs with a DMM, and saw no anomalies.

Measurement condition was that (i) the Fast input was terminated to ground via 50ohm, (ii) the Bias input was shorted to ground. SR785 was used with G=100 Busby preamp (in which Steve installed new batteries today, for someone had left it on for who knows how long) for making the measurement. The voltage measurement was made at the D-Sub connector on the front panel which would be connected to the Sat. Box, with the coil driver not connected to anything downstream.

Summary of results:

[Attachment #1] - Noise measurement out to 800 Hz. The noise only seems to agree with the LISO model above 300 Hz. Not sure if the low-frequency excess is real or a measurement artefact. Tomorrow, I plan to make an LPF pomona box to filter out the HF pickup and see if the low-frequency characteristics change at all. Need to think about what this corner freq. needs to be. In any case, such a device is probably required to do measurements inside the VEA.

[Attachment #2] - Noise measurement for full SR785 span. The 19.5 kHz harmonics are visible. I have a theory about the origin of these, need to do a couple of more tests to confirm and will make a separate log.

[Attachment #3] - zip of LISO file used for modeling coil driver. I don't have the ASCII art in this, so need to double check to make sure I haven't connected some wrong nodes, but I think it's correct.

Measurements seem to be consistent with LISO model predictions.

*Note: Curves labelled "LISO model ..." are really quad sum of liso pred + busby box noise.

My main finding tonight is: With the increased series resistance (400 ohm ---> 2.25 kohm), LISO modeling tells me that even though the series resistance (Johnson noise) used to dominate the voltage noise at the output to the OSEM, the voltage noise of the LT1125 in the bias path now dominates. Since we are planning to re-design the entire bias path anyways, I am not too worried about this for the moment.

I will upload more details + photos + data + schematic + LISO model breakdown tomorrow to a DCC page. 

gautam noon 21 June 2018: I was looking at the wrong LISO breakdown curves. So the input stage Op27 voltage noise used to dominate. Now the Bias path LT1125 voltage noise dominates. None of the conclusions are affected... I've uploaded the corrected plots and LISO file here now. 

Initial tests look promising. Local damping works and I even locked the X arm using POX, although I did it in a fake way by simply inserting a x5.625 (=2.25 kohm / 400 ohm) gain in the coil driver filter banks. I will now tune the individual loop gains to account for the reduced actuation range.

Now I have changed the loop gains for local damping loops, Oplev loops, and POX locking loop to account for the reduced actuation range. The dither alignment servo (X arm ASS) has not been re-commissioned yet...

We may lost the UL magnet or LED

I think if the magnet fell off, we would see high DC signal, and not 0 as we do now. I suspect satellite box or PD readout board/cabling. I am looking into this, tester box is connected to ITMY sat. box for now. I will restore the suspension later in the evening.

Suspension has now been restored. With combination of multimeter, octopus cable and tester box, the problem is consistent with being in the readout board in 1X5/1X6 or the cable routing the signals there from the sat. box.

• Tester box hooked up to sat box ---> UL coil still shows 0 in CDS.
• Tester box hooked up to sat box ---> Mon D-sub on sat box shows expected voltages on DMM. So tester box LEDs are being powered and seem to work.
• Sat box re-connected to test mass ---> Mon D-sub on sat box shows expected voltages on DMM. So OSEM LEDs are being powered and seem to work.
• Sat box remains connected to TM ---> Front panel LEMO monitor points on readout board shows 0 for UL channel, other channels are okay.

Summary:

For a series resistance of 4.5 kohm, we are suffering from the noise-gain amplified voltage noise of the Op27 (2*3.2nV/rtHz), and the Johnson noise of the two 1 kohm input and feedback resistances. As a result, the current noise is ~2.7 pA/rtHz, instead of the 1.9 pA/rtHz we expect from just the Johnson noise of the series resistance. For the present EX coil driver configuration of 2.25 kohm, the Op27 voltage noise is actually the dominant noise source. Since we are modeling small amounts (<1dB) of measurable squeezing, such factors are important I think. 

Details:

[Attachment #1] --- Sketch of the fast signal path in the coil driver board, with resistors labelled as in the following LISO model plots. Note that as long as the resistance of the coil itself << the series resistance of the coil driver fast and slow paths, we can just add their individual current noise contributions, hence why I have chosen to model only this section of the overall network.

[Attachment #2] --- Noise breakdown per LISO model with top 5 noises for choice of Rseries = 2.25 kohm. The Johnson noise contributions of Rin and Rf exactly overlap, making the color of the resulting line a bit confusing, due to the unfortunate order of the matplotlib default color cycler. I don't want to make a custom plot, so I am leaving it like this.

[Attachment #3] --- Noise breakdown per LISO model with top 5 noises for choice of Rseries = 4.5 kohm. Same comments about color of trace representing Johnson noise of Rin and Rf. 

Possible mitigation strategies:

1. Use an OpAmp with lower voltage noise. I will look up some candidates. LT1028/LT1128? LISO library warns of a 400 kHz noise peak though...
2. Use lower Rin and Rf. The values of these are set by the current driving capability of the immediately preceeding stage, which is the output OpAmp of the De-Whitening board, which I believe is a TLE2027. These can source/sink 50 mA according to the datasheet . So for +/-10V, we could go to 400 ohm Ri and Rf, source/sink a maximum of 25mA, and reduce the Johnson noise contribution by 40%.

Other comments/remarks:

I've chosen to ignore the noise contribution of the high current buffer IC that is inside the feedback loop. Actually, it may be interesting to compare the noise measurements (on the electronics bench) of the circuit as drawn in Attachment #1, without and with the high current buffer, to see if there is any difference.

This study also informs about what level of electronics noise is tolerable from the De-Whitening stage (aim for ~factor of 5 below the Rseries Johnson noise).

Finally, in doing this model, I understand that the observation the voltage noise of the coil driver apparently decreased after increasing the series resistance, as reported in my previous elog. This is due to the network formed by the fast and slow paths (during the measurement, the series resistance in the slow path makes a voltage divider to ground), and is consistent with LISO modeling. If we really want to measure the noise of the fast path alone, we will have to isolate it by removing the series resistance of the slow bias path.

Comment about LISO breakdown plots: for the OpAmp noises, the index "0" corresponds to the Voltage noise, "1" and "2" correspond to the current noise from the "+" and "-" inputs of the OpAmp respectively. In future plots, I'll re-parse these...

I wanted to investigate my coil driver noise measurement technique under more controlled circumstances, so I spent yesterday setting up various configurations on a breadboard in the control room. The overall topology was as sketched in Attachment #1 of the previous elog, except for #4 below. Summary of configurations tried (series resistance was 4.5k ohm in all cases):

1. Op 27 with 1kohm input and feedback resistors.
2. LT1128 with 1kohm input and feedback resistors.
3. LT1128 with 400 ohm input and feedback resistors.
4. LT1128 with 400 ohm input and feedback resistors, and also the current buffer IC LM6321 implemented.

Attachments:

Attachment #1: Picture of the breadboard setup.

Attachment #2: Noise measurements (input shorted to ground) with 1 Hz linewidth from DC to 4 kHz.

Attachment #3: Noise measurements for full SR785 span. 

Attachment #4: Apparent coupling due to PSRR.

Attachment #5: Comparison of low frequency noise with and without the LM6321 part of the fast DAC path implemented.

All SR785 measurements were made with input range fixed at -42dBVpk, input AC coupled and "Floating", with a Hanning window. 

Conclusions:

• I get much better agreement between LISO and measurement at a few hundred Hz and below with this proto setup. So it would seem like the excess noise I measure at ~200 Hz in the Eurocrate card version of the coil driver could be real and not simply a measurement artefact.
• I am puzzled about the 10 Hz comb in all these measurements:
  • I have seen this a few times before - e.g. elog13655.
  • It is not due to the infamous GPIB issue - the lines persist even though I disconnect both power adaptor and GPIB prologix box from the SR785.
  • It does not seem to be correlated with the position of the analyzer w.r.t. the DC power supply (Tektronix PS280) used to power the circuit (I moved the SR785 around 1m away from the supply).
  • It persists with either of the two LN preamp boxes available. 
  • It persists with either "Float" or "Ground" input setting on the SR785.
  • All this pointed to some other form of coupling - perhaps conductive EMI.
  • The only clue I have is the apparent difference between the level of the coupling for Op27 and LT1128 - it is significantly lower for the latter compared to the former. 
  • I ruled out position on the breadboard: simply interchanging the Op27 and LT1128 positions on the breadboard, I saw higher 10 Hz harmonics for the Op27 compared to the LT1128. In fact, the coupling was higher for the DIP Op27 compared to an SOIC one I attached to the breadboard via an SOIC to DIP adapter (both were Op27-Gs, with spec'ed PSRR of 120 dB typ).
  • To test the hypothesis, I compared the noise for the Op27 config, on the one hand with regulated (via D1000217) DC supply, and on the other, directly powered by the Tektronix supply. The latter configuration shows much higher coupling.
  • I did have 0.1uF decoupling capacitors (I guess I should've used ceramic and not tantala) near the OpAmp power pins, and in fact, removing them had no effect on the level of this coupling 
  • As a quick check, I measured the spectrum of the DC power used to run the breadboard - it is supplied via D1000217. I used an RC network to block out the DC, but the measurement doesn't suggest a level of noise in the supply that could explain these peaks.
  • The regulators are LM2941 and LM2991. They specify something like 0.03% of the output voltage as AC RMS, though I am not sure over what range of frequencies this is integrated over.
  • But perhaps the effect is more subtle, some kind of downconversion of higher frequency noise, but isn't the decoupling cap supposed to protect against this?
• The 19.5 kHz harmonics seem to originate from the CRT display of the SR785 (SVGA).
  • The manual doesn't specify the refresh rate, but from a bit of googling, it seems like this is a plausible number.
  • The coupling seems to be radiative. The box housing the Busby preamp provides ~60dB attentuation of this signal, and the amplitude of the peaks is directly correlated to where I position the Busby box relative to the CRT screen.
  • This problem can be avoided by placing the DUT and preamp sufficiently far from the SR785.

Punchlines:

1. The actual coildriver used, D010001, doesn't have a regulated power supply, it just draws the +/- 15V directly from Sorensens. I don't think this is good for low noise. 
2. The LM6321 part of the circuit doesn't add any excess noise to the circuit, consistent with it being inside the unity gain feedback loop. In any case, with 4.5 kohm series resistance with the coil driver, we would be driving <2.5 mA of current, so perhaps we don't even need this?

For the upcoming vent, we'd like to rotate the SOS towers to correct for the large YAW bias voltages used for DC alignment of the ITMs and ETMs. We could then use a larger series resistance in the DC bias path, and hence, reduce the actuation noise on the TMs. 

Today, I used the calibrated Oplev error signals to estimate what angular correction is needed. I disabled the Oplev loops, and drove a ~0.1 Hz sine wave to the EPICS channel for the DC yaw bias. Then I looked at the peak-to-peak Oplev error signal, which should be in urad, and calibrated the slider counts to urad of yaw alignment, since I know the pk-to-pk counts of the sine wave I was driving. With this calibration, I know how much DC Yaw actuation (in mrad) is being supplied by the DC bias. I also know the directions the ETMs need to be rotated, I want to double check the ITMs because of the multiple steering mirrors in vacuum for the Oplev path. I will post a marked up diagram later. 

Steve is going to come up with a strategy to realize this rotation - we would like to rotate the tower through an axis passing through the CoM of the suspended optic in the vertical direction. I want to test out whatever approach we come up with on the spare cage before touching the actual towers.

Here are the numbers. I've not posted any error analysis, but the way I'm thinking about it, we'd do some in air locking so that we have the cavity axis as a reference and we'd use some fine alignment adjust (with the DC bias voltages at 0) until we are happy with the DC alignment. Then hopefully things change by so little during the pumpdown that we only need small corrections with the bias voltages.

Some remarks:

1. Why the apparent difference between ITMs and ETMs? I think it's because the bias path resistors are 400 ohms on the ETMs, but 100 ohms on the ITMs. 
2. If we want the series resistance for the bias path to be 10 kohm, we'd only have ~800 urad actuation (for +10V DC), so this would be an ambitious level of accuracy. 

This bad connection is coming back

PRM watchdog was tripped around 7:15am PT today morning. I restored it.

For the heater setup on EY table, I EQ-stopped ETMY. Only the face EQ stops (3 on HR face, 2 on AR face) were engaged. The EY Oplev HeNe was also shutdown during this procedure. 

Yesterday I inspected this BS oplev viewport. The heavy connector tube was shorting to table so It was moved back towards the chamber. The connection is air tight with kapton tape temporarly.

 The beam paths are well centered. The viewport is dusty on the inside.

The motivation was to improve the oplev noise.

When I came in this morning:

• PMC was unlocked.
• Seis BLRMS were off scale.
• ITMX OSEM LEDs were dark on the CRT monitor even though Sat Box was plugged in.

Checking status of slow machines, it looked like c1sus, c1aux, and c1iscaux needed reboots, which I did. Still PMC would not lock. So I did a burtrestore, and then PMC was locked. But there seemed to be waaaaay to much motion of MCREFL, so I checked the suspension. The shadow sensor EPICS channels are reporting ~10,000 cts, while they used to be ~1000cts. No unusual red flags on the CDS side. Everything looked nominal when I briefly came in at 6:30pm PT yesterday, not sure if anything was done with the IFO last night.

Pending further investigation, I'm leaving all watchdogs shutdown and the PSL shutter closed.

A quick look at the Sorensens in 1X6 revealed that the +/- 20V DC power supplies were current overloaded (see Attachment #1). So I set those two units to zero until we figure out what's going on. Possibly something is shorted inside the ITMX satellite box and a fuse is blown somewhere. I'll look into it more once Steve is back.

[koji, steve, gautam]

We debugged this in the following way:

1. Disconnect all fuses in the terminal blocks coming from the +/- 20 VDC Sorensens.
2. Check that they are indeed isolated using DMM.
3. Test blocks of fuses in order to identify where the problem is happening (i.e. plug fuses in, turn up Sorensen voltage knobs, look for current overload). We did things in the following order:
   • MC suspensions
   • BS, PRM and SRM
   • ITMY
   • ITMX
   • Trillium interface box.
4. Turns out that the Trillium box is the culprit.
5. Confirmed that the problem is in the trillium interface box and not in the seismometer itself by unplugging all cables leading out of the interface box, and checking that the problem persists when the box is powered on.

So for now, the power cable to the box is disconnected on the back end. We have to pull it out and debug it at some point.

Apart from this, megatron was un-sshable so I had to hard reboot it, and restart the MCautolocker, FSSslowPy and nds2 processes on it. I also restarted the modbusIOC processes for the PSL channels on c1auxex (for which the physical Acromag units sit in 1X5 and hence were affected by our work), mainly so that the FSS_RMTEMP channel worked again. Now, IMC autolocker is working fine, arms are locked (we can recover TRX and TRY~1.0), and everything seems to be back to a nominal state. Phew.

The trillium interface box was removed from the rack.

The problem was the incorrect use of an under-spec TVS (Transient Voltage Suppression) diodes (~ semiconductor fuse) for the protection circuit.
The TVS diodes we had had the breakdown voltages lower than the supplied voltages of +/-20V. This over-voltage eventually caused the catastrophic breakdown of one of the diodes.

I don't find any particular reason to have these diodes during the laboratory use of the interface. Therefore, I've removed the TVS diodes and left them unreplaced. The circuit was tested on the bench and returned to the rack. All the cables are hooked up, and now the BRLMs look as usual.

Details

- The board version was found to be D1000749-v2

- There was an obvious sign of burning or thermal history around the components D17 and D14. The solder of the D17 was so brittle that just a finger touch was enough to remove the component.

- These D components are TVS diodes (Transient Voltage Suppression Diodes) manufactured by Littelfuse Inc. It is sort of a surge/overvoltage protector to protect rest of the circuit to be exposed to excess voltage. The specified component for D17/D14 was 5.0SMMDJ20A with reverse standoff voltage (~operating voltage) of 20V and the breakdown voltage of 22.20V(min)~24.50V(max). However, the spec sheet told that the marking of the proper component must be "5BEW" rather than "DEM," which is visible on the component. Some search revealed that the used component was SMDJ15A, which has the breakdown voltage of 16.70V~18.50V. This spec is way too low compared to the supplied voltage of +/-20V.

Summary:

The idea we are going with to push the coil driver noise contribution down is to simply increase the series resistance between the coil driver board output and the OSEM coil. But there are two paths, one for fast actuation and one that provides a DC current for global alignment. I think the simplest way to reduce the noise contribution of the latter, while preserving reasonable actuation range, is to implement a precision DC high-voltage source. A candidate that I pulled off an LT application note is shown in Attachment #1.

Requirements:

• The series resistance in the bias path should be , such that the noise from this stage is dominated by the Johnson noise of said resistor, and hence, the current noise contribution is negligible compared to the series resistance in the fast actuation path ().
• Since we only really need this for the test masses, what actuation range do we want?
  • Currently, ETMY has a series resistance of  and has a pitch DC bias voltage of -4 V. 
  • This corresponds to 10 mA of DC current.
  • To drive this current through , we need 100 V. 
  • I'm assuming we can manually correct for yaw misalignments such that 10mA of DC current will be sufficient for any sort of corrective alignment.
  • So +/- 120 V DC should be sufficient.
• The current noise of this stage should be negligible at 100 Hz. 
  • The noise of the transistors and the HV supply should be suppressed by the feedback loop and so shouldn't be a significant contribution (I'll model to confirm).
  • The input noise of the LT1055 is ~20nV/rtHz at 100 Hz, while the Johnson noise of  is ~13nV/rtHz so maybe the low-passing needs to be tuned, but I think if it comes to it, we can implement a passive RC network at the output to achieve additional filtering.
• To implement this circuit, we need +/- 125V DC. 
  • At EX and EY, we have a KEPCO HV supply meant to be used for the Green Steering PZTs. 
  • I'm not sure if these can do bipolar outputs, if not, for temporary testing, we can transport the unit at EY to EX.

If all this seems reasonable, I'd like to prototype this circuit and test it with ETMX, which already has the high series resistance for the fast path. So I will ask Steve to order the OpAmp and transistors.

Bah! Too complex.

The wall StripTool indicated that the IMC wasn't too happy when I came in today. Specifically:

• MC1 watchdog was tripped.
• Even in the tripped state, MC REFL spot on the camera showed spot motion that was too large to be explained as normal seismic driven motion (i.e. with local damping supposedly disabled).
• Strange excursions were observed in the MC1 shadow sensor signal levels as well, see Attachment #1 - negative values don't make any sense for this readout.

The last time this happened, it was due to the Sorensens not spitting out the correct voltages. This time, there were no indications on the Sorensens that anything was funky. So I just disabled the MCautolocker and figured I'd debug later in the evening.

However, around 5pm, the shadow sensor values looked nominal again, and when I re-enabled the local damping, the MC REFL spot suggested that the local damping was working just fine. I re-enabled the MCautolocker, MC re-locked almost immediately. To re-iterate, I did nothing to the electronics inside the VEA. Anyways, this enabled us to work on the X arm ASS (next elog).

Independent from the problems the vertex machine has been having (I think, unless it's something happening over the shared memory network), I noticed on Friday that the ETMX watchdog was tripped. Today, once again, the ETMX watchdog was tripped. There is no evidence of any abnormal seismic activity around that time, and anyways, none of the other watchdogs tripped. Attachment #1 shows that this happened ~838am PT today morning. Attachment #2 shows the 2k sensor data around the time of the trip. If the latter is to be believed, there was a big impulse in the UL shadow sensor signal which may have triggered the trip. I'll squish cables and see if that helps - Steve and I did work at the EX electronics rack (1X9) on Friday but this problem precedes our working there...

OK, how about this:

• Attachment #1 shows the proposed schematic.
  • It consists of a second order section with Gain x10 to map the +/-10V DC range of the DAC to +/- 100V DC such that we preserve roughly the same amount of DC actuation range.
  • Corner frequency of the SOS is set to ~0.7 Hz. In hindsight, maybe this is more aggressive than necessary, we can tune this.
  • DC gain is 20 dB (typo in the text where I say the DC gain is x15, though we could go with this option as well I think if we want a larger series resistance).
  • A first order passive low-pass stage is added to filter out the voltage noise of the PA91, which dominates the output voltage noise (next bullet).
• Attachment #2 shows the transfer function from input to output
  • The two traces compare having just a single SOS filtering stage vs the current topology of having two SOS stages.
  • The passive output RC network is necessary in either case to filter the voltage noise of the PA91 OpAmp.
  • For the DAC noise, I just assumed a flat noise level of , I don't actually know what this is for the Acromag DACs.
• Attachments #3 shows a breakdown of the top 5 noise contributions.
  • The PA91 datasheet doesn't give current noise information so I just assumed , which was what was used for the PA85 in the existing opamp.lib file.
  • The voltage noise is modelled as , which seems to line up okay with the plot on Pg4 of the datasheet.
  • So the model suggests we will be dominated by the voltage noise of the PA91.
• Attachment #4 translates the noise into current noise seen by the actuator.
  • I add the Johnson noise contribution of the series resistance for this path, which is assumed to be .
  • For comparison, I add the filtered DAC noise contribution, and Johnson noise of the proposed series resistance in the fast path.
  • For the bias path, we are dominated by the Johnson noise of the series resistor from ~60 Hz upwards.
  • It's not quite fair to say that the Johnson noise of the resistance in the fast path dominates, the quadrature sum of fast and bais paths will be ~1.2 times of the former alone. 
  • Bottom line: we will be in the regime of total current noise of ~2.2 pA/rtHz, where I think Kevin's modeling suggests we can see some squeezing.

The question still remains of how to combine the fast and bias paths in this proposed scheme. I think the following approach works for prototyping at least:

• Remove the series resistance on the existing coil driver boards' bias path, hence isolating this from the coil.
• Route the DB15 output connector from the coil driver board (which is now just the fast actuation signals) into a sub-sattelite box housing the bias path electronics.
• Sum the two signals as it is done now, by simply having a conductor (PCB trace) merge the two paths after their respective series resistances.

In the longer term, perhaps the Satellite Box revamp can accommodate a bias voltage summation connector.

I have neglected many practical concerns. Some things that come to mind:

1. Is it necessary to protect the upstream DAC from some potential failure of the PA91 in which the high voltage appears at the input?
2. What is the correct OpAmp for this purpose? This chart on Apex's page suggests that PA15, PA85, PA91 and PA98 are all comparable in terms of drive capability, and the spec sheets don't suggest any dramatic differences. Some LIGO circuits use PA85, some use PA90, but I can't find any that use PA91. Perhaps Rana/Koji can comment about this.
3. What kind of protection is necessary for the PA91 power?
4. What is the correct way to do heat management? Presumably we need heatsinks, and in fact, there is a variant of the packaging style that has "formed" legs, which from what I can figure out, allow the heat sink plane on the PA91 to be parallel to the PCB surface. But I think the heat-sink wisdom suggests vertical fins are the most efficient (not sure if this holds if the PCB is inside a box though). What about the PCB itself? Are some kind of special traces needed?
5. Can we use the current-limiting resistor feature on the PA91? The datasheet seems to advice against it for G>10 configurations, which is what we need, although our requirement is only at DC so I don't know if that table is applicable to this circuit.
6. Are 3W resistors sufficient? I think we require only 10mA maximum current to preserve the current actuation range, so 100 V * 10mA = 1W, so 3W leaves some safety margin.
7. All capacitors should be rated for 500 V per the datasheet.