[kira, gautam]

We did a survey of the lab today to figure out some of the logistics for the PID control test for the seismometer can. Kira will upload sketches/photos from our survey. Kira tells me we need

• +/- 15V for the temperature sensors
• +/- 20V, 5A for heater circuit (to be confirmed by Kira after looking at voltage regulator datasheet for dropout voltage)
• 2 ADC channels for temperature sensing (one inside can and one outside)
• 1 DAC channel for controlling MOSFET

There are no DAC channels available in the c1ioo rack. In fact, there is a misleading SCSI cable labelled "c1ioo DAC0" that comes into the rack 1X3 - tracing it back to its other end, it goes into the c1ioo expansion chassis - but there are no DAC cards in there, and so this cable is not actually transporting any signals!

So I recommend moving the whole setup to the X end (which is the can's real home anyways). We plan to set it up without the seismometer inside for a start, to make sure we don't accidentally fry it. We have sufficient ADC and DAC channels available there (see Attachments #1 and #2, we also checked hardware), and also Sorensens to power the heater circuit / temperature sensing circuit. Do we want to hook up the Heater part of this setup to the Sorensens, which also power everything else in the rack? Or do we want to use the old RefCav heater power supply instead, to keep this high-current draw path isolated from the rest of our electronics?

If this looks okay (after pics are uploaded), we will implement these changes (hardware + software) tomorrow.

-----

I have attached the sketch of the whole system (attachment 3) with all the connections and inputs that we will need. Attachment 4 is the rack with the ADC and DAC channels labeled. Attachment 5 is the space where we could set up the can and have the wires go over the top and to the rack.

1. The heater circuit should get its own dedicated supply.
2. We do not want to ever use the old Ref Cav heater for anything. Its unreliable and noisy.
3. Steve should update all the sticky labels on all the power supplies in the lab to indicate what voltage they should be set at. Even if the label is correct, the date should be updated.

I was poking around at the LSC rack to try and set up a temporary arrangement whereby I take the signals from the DAC differentially and route them to the D990694 differentially. The situation is complicated by the fact that, afaik, we don't have any break out boards for the DIN96 connectors on the back of all our Eurocrate cards (or indeed for many of the other funky connecters we have like IDE/IDC 10,50 etc etc). I've asked Steve to look into ordering a few of these. So I tried to put together a hacky solution with an expansion card and an IDC64 connector. I must have accidentally shorted a pair of DAC pins or something, because all models on the c1lsc FE crashed. On attempting to restart them (c1lsc was still ssh-able), the usual issue of all vertex FEs crashing happened. It required several iterations of me walking into the lab to hard-reboot FEs, but everything is back green now, and I see the AS beam on the camera so the input pointing of the TTs is roughly back where it was. Y arm TEM00 flashes are also seen. I'm not going to re-align the IFO tonight. Maybe I'll stick to using a function generator for the THD tests, probably routing non AI-ed signals directly is as bad as any timing asynchronicity between funcGen and DAQ system...

I decided to try doing the THD measurement with a function generator. Did some quick trials tonight to verify that the measurement plan works. Note that for the test, I turned off the z=15,p=150 whitening filter - I'm driving a signal at ~100Hz and should have plenty of oomph to be seen above ADC noise.

1. Checked for ground loops - seem to be fine, see black trace on Attachment #1 which was taken with the FnGen hooked up to the input, but not putting out any signal
2. Spectrum with 1Vpp sine wave @ ~103Hz. The various harmonic peaks are visible, and though I've not paid attention to bin width etc, the largest harmonics are ~1000x smaller than the main peak, and so the THD is ~1ppm, which is in the ballpark of what the datasheet tells us to expect around 100Hz for a gain of ~10 (=20dB). The actual gain was set at 0dB (so all opAmps in the quad bypassed)

I'm going to work on putting together some code that gives me a quick readback on the measured THD, and then do the test for real with different amplitude input signal and whitening gain settings.

**Matlab has a thd function, but to the best of my googling, can't find a scipy.signal analog.

To remind myself of the problem, summarize some of the discussion Koji and I had on the actual problem via email, and in case I've totally misunderstood the problem:

1. The "Variable Gain" feature on the D990694 boards is achieved by 4 single gain stages cascaded together in series, with the ability to engage/bypass each stage individually.
2. The 4 gain stages are constructed using the 4 OpAmps in a quad LT1125 IC, each in standard non-inverting configuration.
3. The switches unfortunately are on the output side of each op-amp. This means that even if a stage is bypassed, the signal reaches the input pin of the OpAmp.
4. For proper operation, in closed-loop, the differential voltage between the input pins of the OpAmp are 0.
5. But this may require the OpAmp to source more current than it can (just using Ohms law and the values of the resistors in the feedback path).
6. As a result, a large differential voltage develops between the input pins of the OpAmp.
7. The LT1125 is not rated to operate in such conditions (this is what Hartmut was saying in the ilog linked earlier in this thread).
8. Part of the internal protection mechanism to prevent damage to the IC in such operating conditions is a pair of diodes between the input pins of the OpAmp.
9. When a large differential voltage develops between the input pins of the OpAmp, the diodes act to short the two to bring them to the same potential (minus whatever small drop there is across the diodes). Actually, according to the datasheet, when the differential voltage between the input pins exceeds 1.4V, the input current must be limited to 25mA, to avoid damaging the protection diodes? If so, we may already have damaged a bunch of these amplifiers.
10. While the LT1125 IC is protected in this condition, the infinite input impedance of the OpAmp is reduced to the resistance between the inverting input and ground. The output voltage may still be saturated, but the output current draw is within what the IC can supply.
11. As a result, Ohms law means that the preceeding stage is overdrawn for current. This is clearly not ideal.
12. Another possible problem is that there is some sort of interaction between the 4 opamps in the quad IC, which means that even if one stage is overdrawn for current, all of them may be affected.
13. The Advanced LIGO version of this board addresses #11 and #12 by (i) placing a series resistor between the input signal and the non-inverting input of the opamp, and (ii) using single opamp ICs instead of a quad, respectively.

So my question is - should we just cut the PCB trace and add this series resistance for the 4 ALS signal channels, and THEN measure the THD? Since the DC voltage level of the ALS signal is expected to be of the order of a few volts, we know we are going to be in the problematic regime where #11 and #12 become issues.

> So my question is - should we just cut the PCB trace and add this series resistance for the 4 ALS signal channels, and THEN measure the THD?

GO A HEAD

Correcting a mistake in my earlier elog: the D990694 is NOT differential receiving, it is single ended receiving via the front panel SMA connectors. The aLIGO version of the whitening board, D1001530 has an additional differential-to-single-ended input stage, though it uses the LT1125 to implement this stage. So the possibility of ground loops on all channels using this board will exist even after the planned change to install series resistance to avoid current overloading the preceeding stage.

Some points before we can set up the can:

1. Cable length and type
   • For the DAC, we can use the LEMO outputs and change it to BNC, then have a long BNC cable running over the top of the lab and to the can 
   • ADC is also LEMO, which we can convert to BNC and have a cable run from that to the temperature sensors
   • Sorensens use plain cables, so we need to find ones that can take a few amps of current and have them be long enough to reach the can and temperature sensors
2. Making sure that there is enough space for the can
   • Can measures about 59 cm in diameter, which does fit in the space we chose
3. Finding Sorensens that work and can provide +/-24V to the heater circuit (since Rana said we want the heater to have its own supply)
   • Found two Sorensens, but only one works for our purpose (update: found a second one that works)
   • The other can only proviide up to 20V before shorting and has been labeled
   • Grounding (see point 5) - we want to have these power supplies be independent, but we must still specify a ground
   • There is exactly enough space to fit in the two Sorensens below the ones that are currently there
4. DIN fuses for 15V and 24V
   • 15V fuses can be easily installed since we don't need a very high current for the temperature sensors
   • the 24V fuses seem to be able to handle 6.3A according to the datasheet, but it only says 4V on the fuse itself. Not sure if this is the wrong darasheet...
5. Connecting the crcuit to the DAC and what connectors to use
   • Using the rightmost DAC because there's less important things connected to it, and use the LEMO conncectors to provide the input
   • Connect the grounds of the DAC and the new Sorensens that we're going to install to the grounds of the rest of the Sorensens
   • *confirm that this setup will work and if not find an alternative
6. Which channels to use for the ADC
   • channels 29, 30, 31 are available, so we can use any two of those (one for each sensor)

Also, I need to eventually remake the connections on my circuit board because they are all currently test points. I also need to find a box for the heater circuit and figure out what to do with the MOSFET and heat sink for it. This can either be done before setting everything up, or we can just change it later once we have the final setup for the can ready.

If all of this looks good then we can begin the setup.

gautam:

1. I recommend using a DAC output from the rightmost AI board because (i) only the green steering mirror PZTs are hooked up to it while the other has ETMX suspension channels and (ii) the rightmost AI board has differential receiving from the DAC, and in light of the recent discussions about ground loops, this seems to be the way to go. Outputs 5-8 are currently unused, while outputs 1-4 are used for the EX green input steering mirror control.
2. Converters required:
   • 2 pin LEMO to BNC --- 2pcs for each temp sensor.
   • Single pin LEMO to BNC --- 1pc for AI board to heater circuit input (readily available)

After labeling all cables, I pulled out one of the D990694s in the LSC rack (the one used for the ALS X signals, it is Rev-B1, S/N 118 according to the sticker on it).

Took some photos before cutting anything. Attachments #1-3 are my cutting plans (shown for 1 channel, plan is to do it for both ALS channels coming into this board). #1 & #2 are meant to show the physical locations of the cuts, and #3 is the corresponding location on the schematic. These are the most convenient locations I could identify on the board for this operation.

I don't know what the purpose of resistors R196, R197, R198 are. I'm assuming it has something to do with the way the ADG333ABR switches. The aLIGO board uses a different switch (MAX4659EUA+), and doesn't have an analogous resistor (though from what I can tell, it too is a CMOS SPDT switch just like the ADG333ABR, just has a lower ON resistance of 25ohm vs 45ohm for the ADG333ABR).

As for the actual resistance to be used: Let's say we don't have signals > 5V coming into this board. Then using 301ohms (as in the aLIGO boards) in series means the peak current draw will be <20mA, which sounds like a reasonable number to me. Larger series resistance is better, but I guess then the contribution of the current noise of the OpAmp keeps increasing.

[Kira, Steve]

We set up a new rail for the Sorensens (attachment 1) and placed one of them down on this new rail (attachment 2). Unfortunately the older rail that had been used to support the other Sorensens (the top one in attachment 1) is thick and does not allow another one of the Sorensens to slide in between the current ones. So we will have to support all the ones on top with a temporary support, take out the old rail, and then insert the new ones before letting the new bottom rail carry the weight of all of the Sorensens. We will do that tomorrow.

In addition, we have to figure out how to lead all the cables to the can, but there are no holders on the side of the lab to do so. So, we decided that we would have a new one installed on the side shown in attachment 3 so that we wouldn't have to place the wires along the floor.

Also, there has been some space made for the can along with the new insulation. The stuff mounted on the wall was removed and will be reattached tomorrow so that it doesn't get in the way of the can anymore.

This is proving much more challenging than I thought - while Cut #1 was easy to identify and execute, my initial plan for Cut #2 seems to not have isolated the input of the second opamp (as judged by DMM continuity). Koji pointed out that this is actually not a robust test, as the switches are in an undefined state while I am doing these tests with the board unpowered. It seems rather complicated to do a test with the board powered out here in the office area though - and I'd rather not desolder the 16 and 20 pin ICs to get a better look at the tracks. This PCB seems to be multilayered, and I don't have a good idea for what the hidden tracks may be. Does anyone know of a secret place where there is a schematic for the PCB layout of this board? The DCC page only has the electrical schematic drawings, and I can't find anything useful on the elog/wiki/old ilog on a keyword search for this DCC document number. The track layout also is not identical for all channels. So I'm holding off on exploratory cuts.

*I've asked Ben Abbott/Mike Pedraza about this and they are having a look in Dale Ouimette's old drives to see if they can dig up the Altium/Protel files.

I quickly put together some code that calculates the THD from CDS data and generates a plot (see e.g. Attachment #1).

Algorithm is:

1. Get data (for now, offile file, but can be readily adapted to download data live or from NDS).
2. Compute power spectrum using scipy.signal.periodogram. I use a Kaiser window with beta=38 based on some cursory googling, and do 10 averages (i.e. nfft is total length / 10), and set the scaling to "spectrum" so as to directly get a power spectrum as opposed to a spectral density.
3. Find fundamental (assumed highest peak) and N harmonics using scipy.signal.find_peaks_cwt. I downsample 16k data to 2k for speed. A 120second time series takes ~5 seconds.
4. Compute THD as where V_i denotes an rms voltage, or in the case of a power spectrum, just the y-axis value.

I conducted a trial on the Y arm ALS channel whitening board (while the X arm counterpart is still undergoing surgery). With the whitening gain set to 0dB, and a 1Vpp input signal (so nothing should be saturated), I measure a THD of ~0.08% according to the above formula. Seems rather high - the LT1125 datasheet tells us to expect <0.001% THD+N at ~100Hz for a closed loop gain of ~10. I can only assume that the digitization process somehow introduces more THD? Of course the FoM we care about is what happens to this number as we increase the gain.

[Kira, Steve]

We installed and labeled the Sorensens today.

Our 3 cranes passed  professional  inspection. Fred Goodbar of Konacrane with 450 lbs load at full extension.

Certificates will be posted in 40m wiki as they arrive.

Gautam and Steve,

The "called 225 lbs" steel crane load measured right on 102 kg

The trick to the measurment to maintain 1 mm gap to the central cilynder of the load cell.

The lead plate stabilized the large load.

gautam: some additional notes:

1. the wiring on the Omega controller unit as given to us was wrong - I had to fix this on the D-sub connector in order to get the load cell to work. something to check for the other units.
2. the main difficulty in doing this calibration run was that the readback is very sensitive to tilts of the load relative to the sensor.
3. the problem is complicated by the fact that the load cell itself does not have a flat surface - it has a ring that protrudes above the flat face of the cylindrical load cell by a few mm as Steve mentioned.
4. so in order to measure the weight of our stacks, we have to mitigate this problem and ensure that the full load of the stack is normally incident on the load cell - if the load cell itself is somehow torqued during the measurement because of the distribution of the load on it being uneven, we get an inaccurate measurement.
5. In this calibration measurement, we think the error is <1% (true mass is 102kg, we measure 104kg on the meter which seems reasonable as the sum of the donut + lead plate)

The main motivation for this work is that I want +15VDC power available on the PSL table to hookup the Teledyne box that Koji made a week ago and do some noise measurements on my revised IR ALS signal chain. But I think this is a good opportunity to effect a number of changes I've been wanting to do for a while.

Tomorrow, Steve and I will do the following:

1. Fix the AOM driver power cabling that I broke.
2. Make the AOM +24VDC power supply independent - right now it is shared between the AOM driver and the two ZHL-3-A amplifiers.
3. Tap an independent +24VDC power supply from 1X1 for the ZHL-3A amplifiers (I guess one power supply and fuse is sufficient for both amplifiers since they are in the same box).
4. Tap an independent +15VDC power supply for the Teledyne box.
5. Tap an independent +15VDC power supply for the little fan on the back of the PSL controller, that is currently powered by a bench supply (+12VDC, but it's just a fan, so +15VDC or +10VDC will do just fine, and these are the Sorensen levels we have).
6. Tap an independent +/-24VDC power supply for the FSS summing box. Right now it is being powered by a bench supply under the PSL table. The indicated supply voltage on the box is +/-18V. But according to the schematic, this +/-18V get regulated down to +/- 15V, so we may as well use +/-24V which is available from the Sorensens in 1X1 (there is no +/-18VDC Sorensen there). The datasheets for the 7815 and 7915 ICs suggest that this will be just fine.
7. Where possible, make at least 1 spare outlet for each supply voltage available at 1X1, such that in future, tapping extra supply points won't be such a huge pain.

So in summary, we will need, at 1X1, (at least, including 1 spare for future work):

• New +24VDC connections ------ 3x
• New -24VDC connections ------- 2x
• New +15VDC connections ------ 3x

[steve, gautam]

We completed this work today. Need to clean up a little (i.e. coil excess cable lengths, remove unused cables etc), which we will do tomorrow. All connections have been made at the DIN rail end, but the fuses have not been inserted yet, so there is no voltage reaching the PSL table on any of the newly laid out cables. We also need to establish two +15VDC connections at the DIN rail side. I may establish this later in the evening, as the main point of this work was to get the Teledyne signal path operational. Setting up these DIN connectors is actually a huge pain, we tried to setup a few extra ports for the voltages we used today so that in future, life is easier for whoever wants to pipe DC power to the PSL table. The rule is, however, to re-establish the same number of open ports for each voltage as was available when you started.

For the ZHL-3A, Teledyne, and AOM driver cables, we used 18AWG, 2 conductor, twisted wire, while for the PSL fan we used 20AWG. For the FSS box, we decided to use the 3 conductor 24AWG twisted wire. I believe that these wire gauge choices are appropriate given the expected current in each of these paths.

Pictures + further details tomorrow.

gautam @ 1030pm: there was some mistake with the +15V wiring we did in the evening (the PSL fan and Teledyne cables were plugged into the wrong DIN terminal blocks). I fixed this, and also routed +15VDC to the newly installed set of terminal blocks for this purpose (since we had run out of +15VDC ports at 1X1). After checking voltages at both 1X1 and on the PSL table, I hooked up

1. FSS Summing box
2. Teledyne amplifier
3. ZHL-3A amplifiers

to their newly laid out power supplies. IMC locks so looks like the FSS box is doing fine . So we can recover one bench power supply from under the PSL table on the east side. I didn't hook up the AOM driver just now because of some accessibility issues, and I'd also like to do an ALS beat spectrum measurement if possible.

I checked channels 6 and 7 on the ADC and they have long wires leading to BNC ends and are currently not being used, so we could probably just attach the temperature sensors to those channels.

I have been puzzled as to why the duty cycle of the EX green locks are much less than that of the EY NPRO. If anything, the PDH loop has higher bandwidth and comparable stability margins at the X end than at the Y end. I hypothesize that this is because the EX laser (Innolight 1W Mephisto) has actuation PZT coefficient 1MHz/V, while the EY laser (Lightwave 125/126) has 5MHz/V. I figure the EX laser is sometimes just not able to keep up with the DC Xarm cavity length drift. To test this hypothesis, I disabled the LSC locking for the Xarm, and enabled the SLOW (temperature of NPRO crystal) control on the EX laser. The logic is that this provides relief for the PZT path and prevents the PDH servo from saturating and losing lock. Already, the green lock has held longer than at any point tonight (>60mins). I'm going to leave it in this state overnight and see how long the lock holds. The slow servo path has a limiter set to 100 counts so should be fine to leave it on. The next test will be to repeat this test with LSC mode ON, as I guess this will enhance the DC arm cavity length drift (it will be forced to follow MCL).

Why do I care about this at all? If at some point we want to do arm feedforward, I thought the green PDH error signal is a great target signal for the Wiener filter calculations. So I'd like to keep the green locked to the arm for extended periods of time. Arm feedforward should help in lock acquisiton if we have reduced actuation range due to increased series resistances in the coil drivers.

As an aside - I noticed that the SLOW path has no digital low pass filter - I think I remember someone saying that since the NPRO controller itself has an in-built low pass filter, a digital one isn't necessary. But as this elog points out, the situation may not be so straightforward. For now, I just put in some arbitrary low pass filter with corner at 5Hz. Seems like a nice simple problem for optimal loop shaping...

gautam noon CNY2018: Looks like the green has been stably locked for over 8 hours (see Attachment #1), and the slow servo doesn't look to have railed. Note that 100 cts ~=30mV. For an actuation coefficient of 1GHz/V, this is ~30MHz, which is well above the PZT range of 10V-->10MHz (whereas the EY laser, by virtue of its higher actuation coefficient, has 5 times this range, i.e. 50MHz). Supports my hypothesis.

Having implemented the changes to the audio amplifier stage, I re-installed this unit at the LSC rack, and did some testing. The motivation was to determine the shape of the ALS error signal spectrum, so that I can design a whitening preamp accordingly. Attachment #1 is the measurement I've been after. The measurement was taken with EX NPRO PDH locked to the arm via green, and Xarm locked to MC via POX. Slow temperature relief servo for EX NPRO was ON. Here are the details:

1. Mode-matching into the BeatMouth PSL light fiber had deteriorated dramatically - it was ~1mW out of 4.4mW. I spent 5 mins getting it back to 3.2mW (72% efficiency) and then moved on... I am a little surprised the drift was so large, but perhaps, it's not surprising given that there has been a lot of work on and around the PSL table in the last couple of weeks. There is a 300mm focusing lens after the last steering mirror so the effect of any alignment drifts should be attenuated, I don't really understand why this happened. Anyways, perhaps a more intelligent telescope design would avoid this sort of problem.
2. I removed the ND filter in the PSL pickoff to BeatMouth path (this was not responsible for the reduced power mentioned in #1). I verified that the total power reaching the photodiode was well below its rated damage threshold of 2mW (right now, there is ~620uW). I will update the BeatMouth schematic accordingly, but I think there will be more changes as we improve mode matching into the fibers at the end.
3. Hooked up the output of the fiber PD to the Teledyne amp, routed the latters output to the LSC rack. Measured RF electrical power at various places. In summary, ~6dBm of beat reaches the splitter at the LSC rack. This is plenty.
4. The main finding tonight was discovered by accident.
   • For the longest time, I was scratching my head over why the beat note amplitude, as monitored on the control room SA (I restored it to the control room from under the ITMX optical table where Koji had temporarily stored it for his tests on the PSL table) was drifting by ~10-15dB!
   • So each time, having convinced myself that the power levels made sense, I would come back to the control room to make a measurement, but then would see the beat signal level fluctuate slowly but with considerable amplitude.
   • The cause - See Attachment #2. There is a length of fiber on the PSL table that is unshielded to the BeatMouth. While plugging in RF cables to the BeatMouth, I found that accidentally brushing the fiber lightly with my arm dramatically changed the beat amplitude as monitored on a scope.
   • For now, I've "strain relieved" this fiber as best as I could, we should really fix this in a better way. This observation leads me to suspect that many of the peaky features seen in Attachment #1 are actually coupling in at this same fiber...
   • The beat note amplitude has been stable since, in the ~90 mins while I've been making plots/elogs.
   • Surely this is a consequence of differential polarization drift between the PSL and EX beams?
5. There are prominent powerline harmonics in these signals - how can we eliminate these? The transmission line from PSL table to LSC rack already has a BALUN at its output to connect the signal to the unbalanced input of the demod board.
6. Not sure what to make of the numerous peaks in the LO driven, RF terminated trace.
7. The location of the lowest point in the bucket also doesn't quite match previous measured out-of-loop ALS noise - we seem to have the lowest frequency noise at 150-200Hz, but in these plots its more like 400Hz.

Conclusion: In the current configuration, with x10 gain on the demodulated signals, we barely have SNR of 10 at ~500Hz. I think the generic whitening scheme of 2 zeros @15Hz, 2poles@150Hz will work just fine. The point is to integrate this whitening with the preamp stage, so we can just go straight into an AA board and then the ADC (sending this signal into D990694 and doing the whitening there won't help with the SNR). Next task is to construct a test daughter board that can do this...

The forline pressure of TP3 was 399 mTorr

It was replaced this morning at  TP3 controller 134,638hrs with the "failed TP2 station" drypump. The foreline pressure now at TP3 is 100 mTorr at 6 hrs of operation.[ at day 3  63 mT ]

IFO pressure at CC Hornet 7.9e - 6 Torr

Valve configuration: vacuum normal as TP3 is the forepump of the Maglev & the annuloses are not pumped

c1mcs had died for some reason. Looking at dmesg, I see:

None of the other EPICS processes died. Not sure what to make of this. I was at the PSL table working, and had closed the PSL shutter to avoid MC autolocker trying to keep the MC locked while I was mucking about, but this shouldn't have had any effect on an EPICS process?

Anyway, I just logged into c1sus, stopped and restarted the model. IMC locks fine now.

After discussing with Koji, I decided to try and align the input beam polarization at the PSL fiber coupler to one of the special axes of the PM fiber. The motivation is to try and narrow down the source of the large RF beatnote amplitude drift I noticed and reported last night.

The setup for doing so is shown in Attachment #1 - essentially, I setup one of the newly purchased couplers in a mount, set up a PBS, and placed two photodiodes at the S and P ports of the PBS. The idea is to rotate the input coupler in its mount, thereby maximizing the PER (monitored on two Thorlabs PDA520s - I didn't check the gain balance of them). 

I spent ~30mins doing some preliminary trials just now, and, I was able to achieve a PER of ~1/20. But I think much better numbers were reported in this SURF project (although I'm not entirely sure I understand that measurement). I will spend a little more time tweaking the alignment. The procedure is tricky as at some point, simply rotating the mount reduces the mode-matching efficiency into the fiber so much that it is not possible to get a meaningful PER measurement from the photodiodes. I'm adjouring for now, more to follow...

Summary:

Current configuration of PSL free-space to fiber coupling is:

• 3.25 mW / 4.55mW (~71%) coupling efficiency, both numbers measured with Ophir power meter, Filter OFF
•  (I choose to define it in this way as opposed to the reciprocal) of 75 (~19dB). The uncertainty in this number is large (see discussion), but I am confident that we have >10dB, which while isn't as good as can be, is sufficient for the main motivation behind this work.

Motivation:

I had noticed that the RF beat amplitude was fluctuating by up to 20dBm as viewed on the control room analyzer. As detailed in my earlier elog, I suspected this to be because of random polarization drift between the PSL and EX fields incident on the Fiber coupled PDs. Since I am confident the problem is optical (as opposed to something funny in the electronics), we'd like to be able to isolate which of the many fiber segments is dominating the contribution to this random polarization drift.

Some useful references:

1. General writeup about how PM fibers work and PER. Gives maximum achievable PERs for a given misalignment of incident beam relative to one of the two birefringent axes.
2. Another similar writeup. This one put me onto the usefulness of the alignment keys on the fibers.
3. Thorlabs PM980 specs - this tells us about the orientation of the two axes for the kind of fibers we use.

Procedure and details:

• The principle of operation behind polarization maintaining (PM) fibers is that intentional birefringence is introduced along two perpendicular axes in the fiber.
• As a result of which light propagates with different phase velocity along these axes.
• For an arbitrary incident field with E-field components along both axes, it is almost impossible to predict the output polarization as we do not know the length of propagation along each axis to sufficient precision (it is also uncontrolled w.r.t. environmental fluctuations). So even if you launch linear polarization into the fiber, it is most likely that the output polarization state will be elliptical.
• But if we align the incident, linear polarization along one of the two axes, then we can accurately predict the polarizaiton at the output, to the extent that the fiber doesn't couple power in the two axes during propagation. I cant find a spec for the isolation between axes for the fiber we use, but the specs I could find for other fiber manufacturers suggest that this number is >30dB, so I think the assumption is a fair one.
• A useful piece of information is that the alignment key on the fibers gives us information about the orientation of the birefringent axes inside the fiber. For the Thorlabs fibers, it seems that the alignment key lines up with the stress-inducing rods inside the fiber (i.e. the slow axis). I confirmed this by looking at the fiber with the fiber scope.
• The PSL pickoff beam I am using for this setup is from the transmission of the PBS after the Faraday. So this field should have relatively pure P-polarization.
• The way I have set up the fiber on the PSL table, the fast axis of the fiber corresponds to P-polarization (i.e. E field oscillates parallel to the plane of the optical table). Actually, it was this alignment that I tweaked in this work.
• Using the information about the alignment key defining polarization axes on the fiber, I also set up the output fiber coupler such that the fast axis lined up as near parallel to the plane of the optical table as possible. In this way, the beam incident on the PBS at the output of my setup should be pure P-polarizaiton if I setup my input alignment into the fiber well.
• I tweaked the rotation of the Fiber mount at the input coupler to maximize the ratio of P_p / P_s, as measured by the pair of PDs at the output. 
• As #1 of my listed references details, you need to align the incident linear polarization to one of the two birefringent axes to closer than 6 degrees to achieve a PER of >20dB. While this sounds like a pretty relaxed requirement, in practise, it is about as good as we can hope to achieve with the mounts we have, as there is no feature that allows us to lock the rotational degree of freedom once we have optimized the alignment. Any kind of makeshift arrangement like taping the rotating part to the mount is also flaky, as during the taping, we may ruin the alignment.
• Attachment #1 shows the result of my alignment optimization - the ratio P_p / P_s is about 75.
• The uncertainty on the above number is large. Possible sources of error:
  • Output coupler is not really aligned such that fast axis corresponds to P-polarizaiton for the output PBS.
  • The two photodiodes' gain balance was not checked.
  • The polarization content of the input beam was not checked.
  • The PBS at the output could be slightly misaligned relative to the S/P polarization directions defined by the tabletop.
  • The PBS extinction ratio was not checked.
• But anyways, this is a definite improvement on the situation before. And despite the large uncertainty, I am confident that P_p / P_s is better than 10dB.
• Moreover, Steve and I installed protective tubing on the lengths of fiber that were unprotected on the PSL table, this should help in reducing stress induced polarization drifts in the fiber, at least in these sections of fiber.
• So I think the next step is to monitor the stability of the RF beatnote amplitude after these improvements. At some point, we need to repeat this procedure for the EX and EY fibers as well.
• If the large drifts are still seen, the only thing we can exclude as a result of this work is the section of fiber from the PSL light coupler to the beat mouth.

Last night I worked at the PSL table for the modulation depth measurement for an aLIGO EOM. Let me know if the IFO behavior is unusual.

What I did was:

• Cranked up the HEPA speed to 100
• Placed an aLIGO EOM in the AUX beat path (south side of the PSL laser). (It is still on the PSL table as of Feb 20, 2018)
• Closed the PSL shutter
• Turned off the main Marconi forr 11MHz. The freq and output power of this marconi have not been touched.
• Turned off the freq generation unit
   
• Worked on my measurement with the spectrum and network analyzers + aux marconi.
   
• Turned down the HEPA speed to 30
• Turned on the freq generation unit
• Turned on the main Marconi
• Opened the PSL shutter => IMC locked

I wanted to lock the single arm POX/POY config to do some tests on the BeatMouth. But I was unable to.

• I tracked the problem down to the fact that the TRX and TRY triggers weren't getting piped correctly to the LSC model
• In fact, all RFM channels from the end machines were showing error rates of 16384/sec (i.e. every sample).
• After watchdogging ETMX, I tried restarting just the c1scx model - this promptly took down the whole c1iscex machine.
• Then I tried the same with c1iscey - this time the models restarted successfully without the c1iscey machine crashing, but the RFM errors persisted for the c1scy channels.
• I walked down to EX and hard rebooted c1iscex.
• c1iscex came back online, and I ssh-ed in and did rtcds start --all.
• This brought all the models back online, and the RFM errors on both c1iscex and c1iscey channels vanished.

Not sure what to make of all this, but I can lock the arms now.

Attachment #1 shows the ALS noise measurement today. Main differences from the spectrum posted last week is that

1. I have tried to align the input polarization axis (p-pol) to the fast axis of the fiber, and believe I have done it to ~75dB.
2. Steve and I installed some protective tubing for the vertical lengths of fiber going into the beat mouth.
3. Today, I decided to measure the noise at the differential rear panel outputs rather than the single-ended front panel outputs. For the test, I used a DB25 breakout board and some pomona mini-grabber to BNC clips to connect to the SR785.

For comparison, I have plotted alongside today's measurement (left column) the measurement from last week (right column).

Conclusions:

• The clear daylight between red and green traces in the left column give me confidence that I am measuring real laser frequency noise in the red trace. It even has the right shape considering the bandwidth of the EX PDH servo.
• The installation of protective tubing doesn't seem to have reduced the heights of any of the peaks in the red traces. I hypothesize that some of these are acoustic coupling to the fiber. But if so, either the way we installed the protective tubing doesn't help a whole lot, or the location of the coupling is elsewhere.
• Judging by the control room analyzer, there doesn't seem to be as large drifts in the RF beat amplitude tonight () as I saw the last couple of times I was testing the BeatMouth®. For a more quantitative study, I'm gonna make a voltage divider so that the ~10V output I get at the rear panel power monitor output (for a LO level of ~0dBm, which is what I have) can be routed to some ADC channel. I'm thinking I'll use the Y ALS channels which are currently open while ALS is under work.
• Still have to make preamp prototype daughter board with the right whitening shape... This test suggests to me that I should also make the output differential sending...

I made a voltage divider using a 20.47kohm and 1.07kohm (both values measured with a DMM). The whole thing is packaged inside a Pomona box I found lying around on the Electronics bench. I have hooked it up to the ALSY_I channel and will leave it so overnight. The INMON of this channel isn't DQed, but for this test, the 16Hz EPICS data will suffice. I've locked the EX laser to the arm, enabled slow temperature servo to allow overnight lock (hopefully) and disabled LSC mode (as locking the arm to the MC tends to break the green lock)

To convert the INMON counts to RF power, I will use (based on my earlier calibration of this monitor channel, see DCC document for the demod chassis).

1AM update: Attachment #1 shows that the RF amplitude has been relatively stable (less than 10% of nominal value variation) over the course of the last hour or so. Even though there is some low frequency drift over timescales of ~20mins, no evidence of the wild ~20dB amplitude changes I saw last week. The signs are encouraging...

overnight update: See Attachment #2 - looking at the past 11 hours of second trend data during which the arm stayed locked, there actually seems to have been more significant variation in the beatnote amplitude. Swings of up to 6dBm are seen on a ~20min timescale, while there is also some longer term drift over 12 hours by a couple of dBm. There is probably a systematic error in the Y-axis, as I measured the RF power at the input of the power splitter at the LSC rack to be ~3dBm, so I expect something closer to 0dBm to be the LO input power which is what I am monitoring. So further debugging is required - I think I'll start by aligning the X fiber coupled beam to one of the fiber's special axes.

To make this setup more permanent, I modified the c1lsc model to pipe the LO power monitor signals from the Demod chassis to unused channels ADC_0_25 (X channel LO) and ADC_0_26 (Y channel LO) in the c1lsc model. I also added a couple of CDS filter blocks inside the "ALS" namespace block in c1lsc so as to allow for calibration from counts to dBm. I didn't add any DQ channels for now as I think the slow EPICS records will be sufficient for diagnostics. It is kind of overkill to use the fast channels for DC voltage monitoring, but until we have acromag channels readily accessible at 1Y2, this will do.

Modified model compiled and installed successfully, though I have yet to restart it given that I'll likely have to do a major reboot of all vertex FEs

I wired the six available BNC connectors on the front panel of the new XEND slow DAQ to physical Acromag channels. There were two unused ADC channels and eight DAC channels, of which I connected four. The following entries were added to /cvs/cds/caltech/target/c1auxex2/ETMXAUX2.db /caltech/target/c1auxex2/ETMXaux2.db

C1:Vac-CC1_HORNET_PRESSURE_VOLT is converted to the additional soft channel C1:Vac-CC1_HORNET_PRESSURE in units of torr using the conversion  stated in the manual. A quick check showed that the resulting number and the displayed pressure on the vacuum gauge itself agree to ~1e-8 torr. Gautam added the new EPICS calc channel to the C0EDCU and restarted FB, now the data is being recorded.

Three of the output channels do not have a purpose yet, so their epics records were created but remain inactive for the time being.

I thought a little bit about the design of the preamp we want for the demodulated ALS signals today. The requirements are:

1. DC gain that doesn't cause ADC saturation.
2. Audio frequency gain that allows the measured beat signal spectrum to be at least 20dB the ADC noise level.
3. Electronics noise such that the measured beat signal spectrum is at least 20dB above the input-referred noise of this amplifier.
4. Low pass filtering at the input to the differential receiving stages, such that the 2f product from the demodulation doesn't drive the AD829 crazy. For now, I've preserved the second-order inductor based LPF from the original board, but if this proves challenging to get working, we can always just go for a first-order RC LPF. One challenge may be to find a 2.2uH inductor that is compatible with prototype PCB boards...
5. Differential sending, since this seems to be definitively the lower noise option compared to the single-ended output (see yesterday's measurement). The plan is to use an aLIGO AA board that has differential receiving and sending, and then connect directly to the differential receiving ADC.

Attachment #3 shows a design I think will work (for now it's a whiteboard sketch, I''ll make this a computer graphic tomorrow). I have basically retained the differential sending and receiving capabilities of the existing Audio I/F amplifier, but have incorporated some whitening gain with a pole at ~150Hz and zero at ~15Hz. I've preserved the DC gain of 10, which seems to have worked well in my tests in the last week or so. Attachments #1 and #2 show the liso modelled characteristics. Liso does not support input-referred noise measurements for differential voltage inputs, so I had to calculate that curve manually - I suspect there is some subtlety I am missing, as if I plot the input referred noise out to higher frequencies, it blows up quite dramatically.

Next step is to actually make a prototype of this. I am wondering if we need a second stage of whitening, as in the current config, we only get 20dB gain at 150Hz relative to DC. Yesterday's beat spectrum measurement shows that we can expect the frequency noise of the ALS signal at ~100Hz to be at the level of ~1uV/rtHz, but this is is around the ADC noise level? If so, 20dB of whitening gain may be sufficient?

*Side note: I was wondering why we need the differential receiving stage, followed by a difference amplifier, and then a differential sending stage. After discussing with Koji, we think this is to suppress any common-mode noise from the mixer outputs.

All rack power supplies labeled if their load changed.

aLIGO EOM crystal replacement

• The entire operation has been performed at the south flow bench @40m.
• We knew that the original crystal in the aLIGO EOM we are testing has some problem. This was replaced with a spare RTP crystal.
• Once the housing was removed, it was obvious that the crystal has a crack (Attachment 1).
  It seemed that it was produced by either a mechanical stress or a thermally induced stress (e.g. soldering).
• I wanted to make sure the new crystal is properly aligned interms of the crystal axis.
  The original crystal has the pencil marking at the top saying "Z" "12". The new (spare) crystal has "Z" and "11".
  So the new crystal was aligned in the same way as the original one. (Attachment 2)
• I took an opportunity to measure the distribution of the electrode lengths (Attachment 3). The lengths are 14, 5, and 14mm, respectively.

Rewired the temperature sensor inputs to Molex connectors so that we can now attach them to the +/- 15V Sorensens for input instead of using a power supply.

aLIGO EOM test: Setup

• The modulation signal was supplied from an aux Marconi.
• Between the Marconi and the EOM, a 20dB coupler (ZFDC-20-5) was inserted. There the Marconi was connected to the output port, while the EOM was to the input port. This way, we can observe how much of the RF power is reflected back to Marconi.
• The beat setup (40m ELOG 13567) was used for the measurement. The EOM was placed in the beam path of the beat setup in the PSL side.
• To eliminate the modulation sidebands of 11MHz and 55MHz, the 40m Marconi and the freq generator were turned off (in this order).
• The nominal amplitude of the carrier beat note was -15dBm ~ -16dBm.
• The cable from the source to the EOM was ~3m. And the loss of this cable was ~0.4dB.

Measurement

• The EOM had three input ports. 

1. 9MHz input - In reality, there was no matching circuit.
2. Center port - matched at 24.1MHz and 118.3MHz. 24.1MHz port has no amplification (just matching), and 118.3MHz is resonant.
3. 45.5MHz port - resonantly matched at 45.5MHz

• The Marconi output power was set to be +13dBm. For the 45MHz measurement, 20dB attenuator is inserted right next to the Marconi so that the VSWR seen from the Marconi was improbed. (Marconi did not like the full reflection of unmatched circuit and shutdown due to the protection function.)
• The amplitude ratios between the sidebands and the carrier were multiplied by a factor of 2, to obtain the modulaiton depths. ( BesselJ(1,m)/BesselJ(0,m) ~ m/2 )
   
• The result is found in Attachment 2.
  • The center port showed the modulation response of 0.7mrad/V and 15mrad/V for 24.1MHz and 118.3MHz, respectively. This suggests that the amplification factor for 118.3MHz is ~x21.
  • The VSWR of the center port is below 1.5 at the target frequencies. That's as tuned in Downs and has not been changed by the crystal replace.
  • The 45MHz port has the modulation response of 0.034mrad/V. This later tuned out that the amplification of ~x19. The circuit is well matched at the resonant frequency.
     
• The linearity was checked with the 45MHz port (Attachment 3). The input power (idrectly connected to the EOM without 20dB attn) was varied between -17dBm to +13dBm. There was no sign of non linearity.
   
• The modulation response at 24MHz was compared at various input ports. (Attachment 4)
  • The input signal was amplified tobe 23dBm by ZHL-3A for better sideband visibility. The actual amplifier output was ~30dBm, and a 6dB ATTN was used to improve the VSWR to protect the amplifier.
  • The 9MHz port showed 3.6mrad/V and 1.8mrad/V with the port unterminated and terminated, respectively. This factor of two difference is as expected.
    This 1.8mrad/V is roughly x2.6 higher compared to the one of the matched 24/118MHz port. This is close number to the ratio of the plate sizes (14mm/5mm = 2.8).
  • With the current condition, the 9MHz (unterminated), 9MHz (terminated), 24/118MHz, and 45MHz ports requires 22dBm, 27dBm, 36dBm, and 21dBm to realize the current modulation depth of 0.014 at 24MHz.
  • Comparing this matched 9MHz performance, the amplification of the 45MHz port at 45MHz was determined to be ~x19.
     
• Considering these results, the modulation response of the center port at 24MHz seems too low. We don't want to supply 36dBm for the 0.014rad modulation (nominal number for H1).
  Here are some thoughts:
  • Use the 45MHz or 9MHz port for 24MHz modulation. Probably the unit is unmatched but, we can come up with the idea to improve the VSWR at 24MHz somehow?
  • Redistribute the plate length to have better modulation at 24MHz. Can we achieve sufficient modulation capability with the frequency of the long and short ports swapped? We hope that we don't need to start over the matching of the 24/118MHz again because the capacitances of the ports are almost the same.

We have the IFO pressure logged again! Thanks Johannes and Gautam

This InstruTech cold cathode ionization vacuum gauge " Hornet " was installed 2016 Sep 14

Here is the CC1 gauge history of 10 years from 2015 Dec 1

The next thing to do is put this channel C1:Vac-CC1_HORNET_PRESSURE  on the 40m Vacuum System Monitor   [ COVAC_MONITOR.adl ] 

gautam 1pm: Vac MEDM screen monitor has been edited to change the readback channel for the CC1 pressure field - see Attachment #2. Seems to work okay.

Using one of the prototype PCB boards given to me by Johannes, I put together v1 of this board and tested it. 

Attachment #1 - Schematic with stages grouped by function and labelled. 

Attachment #2 - Measured vs modelled Transfer function.

Attachment #3 - Measured vs modelled noise. Measurement shown only between positive output and ground, the other port is basically the same. I will update this attachment to reflect the expected signal level in comparison to the noise, but suffice it to say that given the measured input referred noise, we will have plenty of SNR between 0.1Hz and 10kHz. The single stage of whitening should also be sufficient to amplify the signal above ADC noise in the same frequency band

Attachment #4 - Positive output as viewed on a fast (300 MHz) scope using a Tektronix x1 voltage probe.

Attachment #5 - Daughter board noise with measured ALS noise overlaid (the gain of x10 on the existing audio pre-amp has been divided out). 

Comments:

• I may have overlooked the GBW of the OP27 in the design - specifically, the negative feedback is wired for gain x100 at high frequencies, and so the input signal should be filtered above 8MHz/100 ~80kHz. But the LC poles are at ~500kHz. I wonder if the small deviation seen between modelled and masured TFs is reflecting this. Practically, the easier fix is to add a feedback capacitor that rolls off the gain at high frequencies. 300pF WIMA should do the trick, and we have these in stock.
• I don't understand why the modelled response starts to roll off around 5kHz, even though the poles of the LC filter at the input stage are at 500kHz. This happens because at low frequencies, the 1.5uH inductor is basically a short - so the RC divider at the input of the Op27 has a pole at 1/2/pi/R/C ~5kHz for R=499, C = 68nF.
• I am not sure what to make of the peaky comb seen in Attachment #3, but I'm pretty sure it's electronic pickup from something. The GPIB adapter power suppy is not to blame. The peaks are 10 Hz spaced.
• From Attachment #4, I don't suspect any opamp oscillations given that the signal seen is tiny, but I don't know what amplitude is characteristic of an oscillating op amp, so I am not entirely confident about this conclusion. 
• Initially while thinking about the design, I was trying to think of making the design generic enough that we could use these signals for high-bandwidth ALS control (a.k.a. Fast ALS) but in the current incarnation, no consideration was given to minimizing phase lag at high frequencies. 
• Putting the PCB board together was more painful than I imagined as the board is configured for 4 single op amps whereas my design requires 5 - so I needed to do some trace cutting surgery. Rather than make 3 more of these, I'm just going to finish the characterization, and if the design looks good, we can get some custom PCBs printed.
• Power decoupling caps (47nF) are added to all op amp power pins, but is not shown in the schematic.

Given the overall good agreement between model and measurement, I am going to test this with the actual RF beat. For this test, we will need a differential receiving AA board to interface the output of the daughter board with the ADC input. 

[Kira, Gautam]

We began the setup for the lab temperature sensor today. First, we needed to add in a DIN fuse for both temperature sensors, which required us to shut down everything else first. To avoid having to do that next time, we made three instead of two spaces where we have + and - 15V. Attachment 1 shows the new fuses we installed, along with the fuses they connect to. Attachment 2 shows the wiring that we used to connect all the fuses. Attachment 3 shows the labeled long wires that are attached to the lab temperature sensor. The other end is labeled as well. I measured the voltage at the other end of the long cables, and while the -15V one looks good, the +15V one shows only about 13.5V. 

-----

edit (Tuesday) - I set up the other set of cables that will eventually lead to the sensor in the can, but neither of them are showing any voltage on the other end. I'll work on this issue tomorrow.

gautam: some additional remarks about the procedure followed:

• Wires were tinned with solder to facilitate easier insertion into DIN fuse blocks.
• ETMX watchdog was shutdown. I then unplugged the satellite box at the X end to avoid any sort of electrical impulse being sent to the optic.
• Shut down all the sorensens in the EX rack.
• Tapped new +15VDC and -15 VDC outputs at the EX rack in the locations Kira indicated.
• Turned Sorensens back on. Checked that all voltages as reported by front panel monitor points were as they were expected to be.
• Had some trouble getting the modbus IOC going after this work. Kept throwing an error that modbus couldn't be initialized by procserv. Ended up having to reboot c1auxex2, after which it worked fine.

Looks good.

* for bypass type applications, you don't have to use Wima caps (which are bigger and more expensive). You can just use any old ceramic SMD cap.

* This seems like a classic case to use the 3 op-amp instumention amplifier config. This is similar, but not quite.

* Ought to use output resistors of ~50 Ohms by default in the output of any circuit. SInce this is a daughter board, maybe 10 Ohms is enough, but the eventual PCB should have pads for it.

I thought a little bit about the next steps in testing the daughter board. The idea is to install this into the existing 1U chassis and tap the differential output from the FET Mixers as inputs to the daughter board. Looking at the D0902745 schematic, I think the best way to do this is to simply remove L3, L4, C10, C11, C15 and C16. I will then use the pads for L3 and L4 to pipe the differential output of the FET mixer to the differential input of the daughter board. 

The daughter board takes care of whitening the ALS signal.

Then we need to pipe the differential output of the daughter board into the differential input of a differential receiving AA board. Koji and Johannes surveyed the available stockpile from the WB workshop. The best option seems to be to use the available v5 of D070081 and install 4 of them into a 1U chassis unit (also available from WB EE shop). The v5s can be upgraded to v6 by replacing the set of input and output buffer OpAmps with AD8622, as per the revision history notes. Koji ordered 100pcs of these today. 

The input to the proposed 1U chassis housing these 8 AA boards (each with 8 channels) is a DB9 connector. The aLIGO demod board chassis that we use to demodulate the ALS signals has a nice DB25 output connector that supplies all the differential I and Q demodulated signals. But since we will install a daughter board, we will hae to hack together some connector solution anyways. I propose using a DB9 connector to pipe the outputs of the daughter board to the inputs of the AA board. Space is tight in the LSC rack, but I think we have space for a 1U chassis (see Attachment #3).

Finally - how to interface the AA board with the ADC? Koji and I discussed options, and seems like the least painful way will be to install a new ADC in the c1lsc expansion chassis in 1Y3. I checked the computer hardware cabinet and there seems to be 1 spare general standards 16bit ADC in there (see Attachment #1). Its health/providence is unknown. But Koji and I will test it after the meeting tomorrow. I also have another ADC card that Jamie and I removed from c1ioo sometime ago. I have labelled it as "GPIO0 LED RED", though I don't remember exactly what the problem was and can't find any elog about it. Incidentally, there are also 2 spare DAC cards available in the cabinet, although their health/rpovidence too is unknown. There are sufficient free slots in the c1lsc expansion chassis (see Attachment #2 though we will need a LIGO ADC adaptor card). Then we can just change the input ADC channels for the ALS signals in the c1lsc model.

In the short term, while the hardware for this plan is being put together, I can test the uncalibrated noise performance of the demod + daughter board combo (uncalibrated because I will make a measurement of voltage noise with an SR785 as opposed to frequency noise). A second daughter board will also need to be assembled - I'm just going to do it on another prototyping board as figuring out how to use Altium will probably take me longer. There is also the matter of fine tuning the polarization axes alignment of the input to the EX fiber coupler.

I switched out the DIN fuses for the long cables and it fixed the issue of them not showing any votage on the other end. At first, the +15V cable worked and the -15V didn't, but when I switched the fuse for the -15V it began working, but the +15V stopped working. I then switched out the fuse for +15V and both cables began showing voltage. But for both the long cables and the shorter ones, they show +13.4V instead of +15V. Not sure what's going on there.

[koji, gautam]

we did a bunch of tests to figure out the feasibility of the plan I outlined last night. Bottom line is: we appear to have a working 64 channel ADC (but with differential receiving that means 32 channels). But we need an aLIGO ADC adaptor card (I'm not sure of the DCC number but I think it is D0902006). See attached screenshot where we managed to add an ADC block to the IOP model on c1lsc, and it recognizes the additional ADC. The firmware on the (newly installed) working card is much newer than that on the existing card inside the expansion chassis (see Attachment #1).

Details:

• Watchdogged all optics because we expected messing around with c1lsc to take down all the vertex FEs. Actually, only c1sus was killed, c1ioo survived.
• Closed PSL shutter. Shut down c1lsc FE machine.
• Started out by checking the functionality of the two ADC cards I found.
• Turns out the one Jamie and I removed from c1ioo ~6months ago is indeed broken in some way, as we couldn't get it to work.
• Took us a while to figure out that we require the adaptor board and a working ADC card to get the realtime model to run properly. A useful document in understanding the IO expansion chassis is this one.
• Another subtlety is that the ADC card we installed today (photo in previous elog) is somewhat different from the ones installed in c1sus and c1lsc expansion chassis. But a similar one is installed at the Y-end at least. Point is, this ADC card seems to need an external power supply via a 4-pin Molex connector to work properly.
• We borrowed an adapter card from c1iscey expansion chassis (after first shutting down the machine).
• It seems like a RED GPIO0 LED on these ADC cards isn't indicative of a fault.
• Added an ADC part from CDS_PARTS library. Added an ADC selector bus and an "MADC" block that sets up the 64k testpoints as well as the EPICS readbacks.
• We were able to see sensible numbers (i.e. ~0 since there is no input to the ADC) on these readback channels.
• To restore everything, we first shutdown c1lsc, then restored the adaptor card back to c1iscey, and then rebooted c1iscey, c1lsc and c1sus. Recompiled c1x04 with the added ADC block removed as it would otherwise complain due to the absence of an adapter board.
• Did rtcds restart <model> on all machines to bring back all models that were killed. This went smoothly.
• IMC and Yarm locked smooth.

Note that we have left the working ADC card inside the c1lsc expansion chassis. Plan is to give Rolf the faulty ADC card and at the same time ask him for a working adapter board.

Unrelated to this work: we have also scavenged 4 pcs of v2 of the differential receiving AA board from WB EE shop, along with a 1U chassis for the same. These are under my desk at the 40m for the moment. We will need to re-stuff these with appropriate OpAmps (and also maybe change some Rs and Cs) to make this board the same as v6, which is the version currently in use.

I spent today making another daughter board (so that we can use the new scheme for I and Q for one arm), testing it (i.e. measuring noise and TF and comparing to LISO model), and arranging all of this inside the 1U demod chassis. To accommodate everything inside, I decided to remove the 2 unused demod units from inside the box. I then drilled a few holes, installed the daughter boards on some standoffs, removed the capacitors and inductors as I outlined yesterday, and routed input and output signals to/from the daughter board. The outputs are routed to a D-sub on the rear panel. More details + better photo + results of testing the combined demod+daughter board signal chain tomorrow...

In Steve's absence, I've tried to keep an eye on the health of the vacuum system. From Attachment #1, the pressure of the main volume seems stable, no red flags there. I also don't here any anomalously loud sounds near the vacuum pumps. I've changed the N2 cylinders that keep V1 open twice, on Wednesday and Sunday of last week. So in summary, the vacuum system looks fine based on all the metrics I know of.

For testing the new IR ALS noise, we had decided that we would like to use the differential output of the demodulated ALS beat signal, as opposed to a single-ended output, as measurements suggested the former to be a lower noise configuration than the latter. For this purpose, Koji and I acquired a couple of old AA boards from the WB electronics shop. These are however, rev2 of the board, whereas the latest version is v6. The main difference between v2 and v6 is that (i) the THS4131 instrumentation amplifier has the Vocm pin grounded in v6 but is floating in v2 and (ii) the buffer opamps are AD8622 in v6 but are AD8672 in v2. But in fact, the boards we have are stuffed with AD8682. 

I talked to Rich on Friday, and he seemed to think the AD8672 didn't have any issues noise-wise, the main reason they changed it was because its power consumption was high, and was causing overheating when several of these 1U chassis were packed closely together in an electronics rack. But the AD8682, which is what we have, has comparable power consumption to the AD8622. It is however a JFET opamp, and the voltage noise is a bit higher than the AD8622. 

I am sure there is a way to LISO model a differential output opamp like the THS4131, but I thought I'd simulate the noise in LTSPICE instead. But I couldn't get that to work. So instead, I just measured the transfer function and noise of a single channel, for which Koji had expertly hacked together a custom shorting of the THS4131 Vocm pin to ground. Attachments #1 and #2 show the measurement. All looks good. Note that the phase is 180 at DC because I had hooked up the input signal opposite to what it should have been. The voltage noise of the differential outputs (each measured w.r.t. ground, with both inputs shorted to ground by a short patch cable) at 10 Hz is <100nV/rtHz, and the ADC noise is expected to be ~1uV/rtHz, so I think this is fine.

Conclusion: I think for the ALS test, we can just use the AA board in this config without worrying too much about replacing the buffer stage opamps, even though we've ordered 100pcs of AD8622.

Addendum 7 Mar 2018 11am: As per this document, the output noise of the AA board should be <75nV/rtHz from 10 Hz-50 kHz. So maybe the AD8682 noise is a little high after all. I've gotten the LTSpice model working now, will post the comparison of modelled output noise for various combinations here shortly.

I did a quick test of the noise of the new ALS electronics with the X arm ALS. Attachment #1 shows the results - but something looks off in the measurement, especially the "LO driven, RF terminated" trace. I will have to defer further testing to tomorrow. Of course the real test is to digitize these signals and look at the spectrum of the phase tracker output, but I wanted a voltage noise comparison first. Also, note that I have NOT undone the whitening TFs of (z,p) = (15,150) on these traces. I wonder if these noisy signals (particularly the 10Hz multiple harmonics) are an artefact of measurement, or if something is wonky in the daughter board circuits themselves. I am measuring these with the help of a DB9 breakout board and some pomona minigrabbers. Reagrdless, the sort of ripple seen in the olive green trace for the I channel wasn't present when I did the same test with RF signal generators out on the electronics workbench, so I am inclined to think that this isn't a problem with the circuit. I'm measuring with the SR785 with the "A" input setting, but with the ground set to "Float". I need to look into what the difference is between this mode, and the "A-B" mode. At first glance, both seem to be equivalent differential measurements, but I wonder if there is some subtlety w.r.t. pickup noise.

Perhaps I can repeat the test at the output of the AA board. I looked into whether there is a spare +/- 24V DC power supply available at the LSC rack, to power the 1U AA chassis, but didn't see anything there.

Here are the plots. Comments:

1. Measurement and model agree quite well .
2. Of the 3 OpAmps, the ones installed seem to be the noisiest (per model). 
3. Despite #2, I don't think it is critical to replace the buffer opamps as we only win by ~10nV/rtHz in the 300-10kHz range.
4. I don't understand the spec given in T070146. It says the noise everywhere between 10Hz-50kHz should be <75nV/rtHz. But even the model suggests that at 10Hz, the noise is ~250nV/rtHz for any choice of buffer opamp, so that's a factor of 3 difference which seems large. Maybe I made a mistake in the model but the agreement between measurement and model for the AD8682 choice gives me confidence in the simulation. LTSpice files used are in Attachment #3. Could also be an artefact of the way I made the measurement - between an output and ground instead of differentially...

I like LTspice for such modeling - the GUI is nice to have (though I personally think that typing out a nodal file a la LISO is faster), and compared to LISO, I think that the LTspice infrastructure is a bit more versatile in terms of effects that can be modeled. We can also easily download SPICE models for OpAmps from manufacturers and simply add them to the library, rather than manually type out parameters in opamp.lib for LISO. But the version available for Mac is somewhat pared down in terms of the UI, so I had to struggle a bit to find the correct syntax for the various simulation commands. The format of the exported data is also not as amenable to python plotting as LISO output files, but i'm nitpicking...

I am almost ready for a digital test of the new ALS electronics. Today, Koji and I spent some time tapping new +/-24VDC DIN terminal blocks at the LSC rack to facilitate the installation of the 1U differential receiving AA chassis (separate elog entry). The missing piece of the puzzle now is the timing adapter card. I opted against trying a test tonight as I am having some trouble bringing c1lsc back online.

Incidentally, a repeat of the voltage noise measurement of the X arm ALS beat looked much cleaner today, see Attachment #1 - I don't have a good hypothesis as to why sometimes the signal has several harmonics at 10Hz multiples, and sometimes it looks just as expected. The problem may be more systematically debuggable once the signals are being digitally acquired.

This required multiple hard reboots, but seems like all the RT models are back for now. The only indicator I can't explain is the red DC field on c1oaf. Also, the SUS model seems to be overclocking more frequently than usual, though I can't be sure. The "timing" field of this model's state word is RED, while the other models all seem fine. Not sure what could be going on.

Will debug further tomorrow, when I probably will have to do all this again as I'll need to recompile c1lsc for the ALS electronics test with the new ADC card from the differential AA board.

As I had found before, restarting the c1oaf model fixed the DC error. There is however still a pesky red indicator light on the "ADC0" in c1oaf. Trying to open up the ADC MEDM screen to investigate this further leads to the blank screen on the bottom right of Attachment #1. Probably has something to do with the fact that the model has an ADC block (because every model needs one?) but no signals are actually being piped to the model directly from the ADC.

Another observation, though I don't have any hypothesis as to why this was happening: on the c1sus machine, the c1sus model would frequently overclock, and then eventually, crash. I observed this behaviour at least 3 times between last night and now. The other models seemed fine though, in fact, IMC stayed locked. Why should this have been the case? It remains to be seen if this was somehow connected to the red DC indicator on c1oaf, though why should this be the case? Isn't the DC just concerned with writing data to frames? Any sort of IPC should be independent? Attachment #2 shows that there's been a definite increase in the maximum time on c1sus clock-cycle since yesterday (it's a 10 day minute trend plot of the model clock cycle timing and also the maximum time). Why? Koji and I did switch off all the Sorensens at the LSC rack for about 30mins, but why should this affect anything at 1X6? There are no red lights in either the c1lsc or c1sus expansion chassis. Curiously, the PRM also seems to be glitchy - as I'm sitting in the control room, I see a spot flashing across vertically on the REFL CRT monitor sporadically. Note that nominally, with PRM misaligned, the REFL CRT should be dark. dmesg on c1sus doesn't shed any light on the issue.

Seems like some high level voodoo .

Edit 330pm: The model just crashed again. dmesg rather unhelpfully just says "ADC timeout". Unclear how to debug further. See Attachment #3.

[Koji, Gautam]

Yesterday, we installed some new DIN rail connectors at the LSC rack to provide 3 new outputs each for +24V DC and -24V DC. The main motivation was to facilitate the installation and powering of the differential receiving AA board. The regulators used inside the 1U chassis actually claims a dropout voltage of 0.5V and outputs 14V nominally, so a +/-15V DC supply would've perhaps been sufficient, but we decided to leave a bit more margin, and unfortunately, there are no +/-18V DC KEPCO linear power supplies to the LSC rack. Procedure:

1. Prepared a bunch of DIN rail connectors with tinned, daisy-chained wires in the office area. Checked continuity and isolation with DMM.
2. Checked that the two Sorensens at the bottom of the LSC rack were powering the RF distribution box and nothing else at the LSC rack.
3. Walked over to the little rack housing all the KEPCO DC power supplies that supply DC voltages to the LSC rack. After checking that the labelled voltage and current values were correct, we turned them off, first +/-5V, then +/-15V (2 sets), and finally +/-24V.
4. Installed the pre-assembled DIN connectors on the side rail at the LSC rack (we had to remove the side panel for the rack to do this work).
   • We used the ports supplying power to the ALS 1U demod chassis (+/-24V DC) to tap these voltages to our newly installed connectors.
   • The interconnecting wires are rather thick gauge, and especially for the ground wire, we found it impossible to push in our tap-off wire into the "correct/hot" side of the DIN blocks. So we had to use the other side instead. I'll upload a picture shortly which will make this more clear.
   • Checked continuity and isolation with DMM.
   • Turned the KEPCOs back on in reverse order to how they were turned off.
   • Measured voltages on the hot side of the DIN blocks, confirmed that they were as expected.
5. Prepared a 12AWG aLIGO style power cable to connect to the 1U chassis. A reel of this cabling, with yellow shielding, is located ~halfway along under the EW arm. Koji prepared the actual connector and housed it in a DSUB shell as per aLIGO wiring color scheme.
6. Installed the power cabling to one set of our 3 newly installed +/-24V DC power supplies.
7. Inserted fuses into the hot DIN blocks, measured voltage at connector end of our newly installed power cable. At first, I forgot to check if the fuse blocks had fuses inside, but after this was rectified, voltages were as expected .

The c1lsc frontend models crashed for some reason during this procedure. Now the c1sus frontend model is also behaving weirdly. It is unclear to me if/how this work would have led to these problems, but the temporal correlation (but not causation?) is undeniable.