I switched out the DIN fuses for the long cables and it fixed the issue of them not showing any votage on the other end. At first, the +15V cable worked and the -15V didn't, but when I switched the fuse for the -15V it began working, but the +15V stopped working. I then switched out the fuse for +15V and both cables began showing voltage. But for both the long cables and the shorter ones, they show +13.4V instead of +15V. Not sure what's going on there.

[koji, gautam]

we did a bunch of tests to figure out the feasibility of the plan I outlined last night. Bottom line is: we appear to have a working 64 channel ADC (but with differential receiving that means 32 channels). But we need an aLIGO ADC adaptor card (I'm not sure of the DCC number but I think it is D0902006). See attached screenshot where we managed to add an ADC block to the IOP model on c1lsc, and it recognizes the additional ADC. The firmware on the (newly installed) working card is much newer than that on the existing card inside the expansion chassis (see Attachment #1).

Details:

• Watchdogged all optics because we expected messing around with c1lsc to take down all the vertex FEs. Actually, only c1sus was killed, c1ioo survived.
• Closed PSL shutter. Shut down c1lsc FE machine.
• Started out by checking the functionality of the two ADC cards I found.
• Turns out the one Jamie and I removed from c1ioo ~6months ago is indeed broken in some way, as we couldn't get it to work.
• Took us a while to figure out that we require the adaptor board and a working ADC card to get the realtime model to run properly. A useful document in understanding the IO expansion chassis is this one.
• Another subtlety is that the ADC card we installed today (photo in previous elog) is somewhat different from the ones installed in c1sus and c1lsc expansion chassis. But a similar one is installed at the Y-end at least. Point is, this ADC card seems to need an external power supply via a 4-pin Molex connector to work properly.
• We borrowed an adapter card from c1iscey expansion chassis (after first shutting down the machine).
• It seems like a RED GPIO0 LED on these ADC cards isn't indicative of a fault.
• Added an ADC part from CDS_PARTS library. Added an ADC selector bus and an "MADC" block that sets up the 64k testpoints as well as the EPICS readbacks.
• We were able to see sensible numbers (i.e. ~0 since there is no input to the ADC) on these readback channels.
• To restore everything, we first shutdown c1lsc, then restored the adaptor card back to c1iscey, and then rebooted c1iscey, c1lsc and c1sus. Recompiled c1x04 with the added ADC block removed as it would otherwise complain due to the absence of an adapter board.
• Did rtcds restart <model> on all machines to bring back all models that were killed. This went smoothly.
• IMC and Yarm locked smooth.

Note that we have left the working ADC card inside the c1lsc expansion chassis. Plan is to give Rolf the faulty ADC card and at the same time ask him for a working adapter board.

Unrelated to this work: we have also scavenged 4 pcs of v2 of the differential receiving AA board from WB EE shop, along with a 1U chassis for the same. These are under my desk at the 40m for the moment. We will need to re-stuff these with appropriate OpAmps (and also maybe change some Rs and Cs) to make this board the same as v6, which is the version currently in use.

I spent today making another daughter board (so that we can use the new scheme for I and Q for one arm), testing it (i.e. measuring noise and TF and comparing to LISO model), and arranging all of this inside the 1U demod chassis. To accommodate everything inside, I decided to remove the 2 unused demod units from inside the box. I then drilled a few holes, installed the daughter boards on some standoffs, removed the capacitors and inductors as I outlined yesterday, and routed input and output signals to/from the daughter board. The outputs are routed to a D-sub on the rear panel. More details + better photo + results of testing the combined demod+daughter board signal chain tomorrow...

In Steve's absence, I've tried to keep an eye on the health of the vacuum system. From Attachment #1, the pressure of the main volume seems stable, no red flags there. I also don't here any anomalously loud sounds near the vacuum pumps. I've changed the N2 cylinders that keep V1 open twice, on Wednesday and Sunday of last week. So in summary, the vacuum system looks fine based on all the metrics I know of.

For testing the new IR ALS noise, we had decided that we would like to use the differential output of the demodulated ALS beat signal, as opposed to a single-ended output, as measurements suggested the former to be a lower noise configuration than the latter. For this purpose, Koji and I acquired a couple of old AA boards from the WB electronics shop. These are however, rev2 of the board, whereas the latest version is v6. The main difference between v2 and v6 is that (i) the THS4131 instrumentation amplifier has the Vocm pin grounded in v6 but is floating in v2 and (ii) the buffer opamps are AD8622 in v6 but are AD8672 in v2. But in fact, the boards we have are stuffed with AD8682. 

I talked to Rich on Friday, and he seemed to think the AD8672 didn't have any issues noise-wise, the main reason they changed it was because its power consumption was high, and was causing overheating when several of these 1U chassis were packed closely together in an electronics rack. But the AD8682, which is what we have, has comparable power consumption to the AD8622. It is however a JFET opamp, and the voltage noise is a bit higher than the AD8622. 

I am sure there is a way to LISO model a differential output opamp like the THS4131, but I thought I'd simulate the noise in LTSPICE instead. But I couldn't get that to work. So instead, I just measured the transfer function and noise of a single channel, for which Koji had expertly hacked together a custom shorting of the THS4131 Vocm pin to ground. Attachments #1 and #2 show the measurement. All looks good. Note that the phase is 180 at DC because I had hooked up the input signal opposite to what it should have been. The voltage noise of the differential outputs (each measured w.r.t. ground, with both inputs shorted to ground by a short patch cable) at 10 Hz is <100nV/rtHz, and the ADC noise is expected to be ~1uV/rtHz, so I think this is fine.

Conclusion: I think for the ALS test, we can just use the AA board in this config without worrying too much about replacing the buffer stage opamps, even though we've ordered 100pcs of AD8622.

Addendum 7 Mar 2018 11am: As per this document, the output noise of the AA board should be <75nV/rtHz from 10 Hz-50 kHz. So maybe the AD8682 noise is a little high after all. I've gotten the LTSpice model working now, will post the comparison of modelled output noise for various combinations here shortly.

I did a quick test of the noise of the new ALS electronics with the X arm ALS. Attachment #1 shows the results - but something looks off in the measurement, especially the "LO driven, RF terminated" trace. I will have to defer further testing to tomorrow. Of course the real test is to digitize these signals and look at the spectrum of the phase tracker output, but I wanted a voltage noise comparison first. Also, note that I have NOT undone the whitening TFs of (z,p) = (15,150) on these traces. I wonder if these noisy signals (particularly the 10Hz multiple harmonics) are an artefact of measurement, or if something is wonky in the daughter board circuits themselves. I am measuring these with the help of a DB9 breakout board and some pomona minigrabbers. Reagrdless, the sort of ripple seen in the olive green trace for the I channel wasn't present when I did the same test with RF signal generators out on the electronics workbench, so I am inclined to think that this isn't a problem with the circuit. I'm measuring with the SR785 with the "A" input setting, but with the ground set to "Float". I need to look into what the difference is between this mode, and the "A-B" mode. At first glance, both seem to be equivalent differential measurements, but I wonder if there is some subtlety w.r.t. pickup noise.

Perhaps I can repeat the test at the output of the AA board. I looked into whether there is a spare +/- 24V DC power supply available at the LSC rack, to power the 1U AA chassis, but didn't see anything there.

Here are the plots. Comments:

1. Measurement and model agree quite well .
2. Of the 3 OpAmps, the ones installed seem to be the noisiest (per model). 
3. Despite #2, I don't think it is critical to replace the buffer opamps as we only win by ~10nV/rtHz in the 300-10kHz range.
4. I don't understand the spec given in T070146. It says the noise everywhere between 10Hz-50kHz should be <75nV/rtHz. But even the model suggests that at 10Hz, the noise is ~250nV/rtHz for any choice of buffer opamp, so that's a factor of 3 difference which seems large. Maybe I made a mistake in the model but the agreement between measurement and model for the AD8682 choice gives me confidence in the simulation. LTSpice files used are in Attachment #3. Could also be an artefact of the way I made the measurement - between an output and ground instead of differentially...

I like LTspice for such modeling - the GUI is nice to have (though I personally think that typing out a nodal file a la LISO is faster), and compared to LISO, I think that the LTspice infrastructure is a bit more versatile in terms of effects that can be modeled. We can also easily download SPICE models for OpAmps from manufacturers and simply add them to the library, rather than manually type out parameters in opamp.lib for LISO. But the version available for Mac is somewhat pared down in terms of the UI, so I had to struggle a bit to find the correct syntax for the various simulation commands. The format of the exported data is also not as amenable to python plotting as LISO output files, but i'm nitpicking...

I am almost ready for a digital test of the new ALS electronics. Today, Koji and I spent some time tapping new +/-24VDC DIN terminal blocks at the LSC rack to facilitate the installation of the 1U differential receiving AA chassis (separate elog entry). The missing piece of the puzzle now is the timing adapter card. I opted against trying a test tonight as I am having some trouble bringing c1lsc back online.

Incidentally, a repeat of the voltage noise measurement of the X arm ALS beat looked much cleaner today, see Attachment #1 - I don't have a good hypothesis as to why sometimes the signal has several harmonics at 10Hz multiples, and sometimes it looks just as expected. The problem may be more systematically debuggable once the signals are being digitally acquired.

This required multiple hard reboots, but seems like all the RT models are back for now. The only indicator I can't explain is the red DC field on c1oaf. Also, the SUS model seems to be overclocking more frequently than usual, though I can't be sure. The "timing" field of this model's state word is RED, while the other models all seem fine. Not sure what could be going on.

Will debug further tomorrow, when I probably will have to do all this again as I'll need to recompile c1lsc for the ALS electronics test with the new ADC card from the differential AA board.

As I had found before, restarting the c1oaf model fixed the DC error. There is however still a pesky red indicator light on the "ADC0" in c1oaf. Trying to open up the ADC MEDM screen to investigate this further leads to the blank screen on the bottom right of Attachment #1. Probably has something to do with the fact that the model has an ADC block (because every model needs one?) but no signals are actually being piped to the model directly from the ADC.

Another observation, though I don't have any hypothesis as to why this was happening: on the c1sus machine, the c1sus model would frequently overclock, and then eventually, crash. I observed this behaviour at least 3 times between last night and now. The other models seemed fine though, in fact, IMC stayed locked. Why should this have been the case? It remains to be seen if this was somehow connected to the red DC indicator on c1oaf, though why should this be the case? Isn't the DC just concerned with writing data to frames? Any sort of IPC should be independent? Attachment #2 shows that there's been a definite increase in the maximum time on c1sus clock-cycle since yesterday (it's a 10 day minute trend plot of the model clock cycle timing and also the maximum time). Why? Koji and I did switch off all the Sorensens at the LSC rack for about 30mins, but why should this affect anything at 1X6? There are no red lights in either the c1lsc or c1sus expansion chassis. Curiously, the PRM also seems to be glitchy - as I'm sitting in the control room, I see a spot flashing across vertically on the REFL CRT monitor sporadically. Note that nominally, with PRM misaligned, the REFL CRT should be dark. dmesg on c1sus doesn't shed any light on the issue.

Seems like some high level voodoo .

Edit 330pm: The model just crashed again. dmesg rather unhelpfully just says "ADC timeout". Unclear how to debug further. See Attachment #3.

[Koji, Gautam]

Yesterday, we installed some new DIN rail connectors at the LSC rack to provide 3 new outputs each for +24V DC and -24V DC. The main motivation was to facilitate the installation and powering of the differential receiving AA board. The regulators used inside the 1U chassis actually claims a dropout voltage of 0.5V and outputs 14V nominally, so a +/-15V DC supply would've perhaps been sufficient, but we decided to leave a bit more margin, and unfortunately, there are no +/-18V DC KEPCO linear power supplies to the LSC rack. Procedure:

1. Prepared a bunch of DIN rail connectors with tinned, daisy-chained wires in the office area. Checked continuity and isolation with DMM.
2. Checked that the two Sorensens at the bottom of the LSC rack were powering the RF distribution box and nothing else at the LSC rack.
3. Walked over to the little rack housing all the KEPCO DC power supplies that supply DC voltages to the LSC rack. After checking that the labelled voltage and current values were correct, we turned them off, first +/-5V, then +/-15V (2 sets), and finally +/-24V.
4. Installed the pre-assembled DIN connectors on the side rail at the LSC rack (we had to remove the side panel for the rack to do this work).
   • We used the ports supplying power to the ALS 1U demod chassis (+/-24V DC) to tap these voltages to our newly installed connectors.
   • The interconnecting wires are rather thick gauge, and especially for the ground wire, we found it impossible to push in our tap-off wire into the "correct/hot" side of the DIN blocks. So we had to use the other side instead. I'll upload a picture shortly which will make this more clear.
   • Checked continuity and isolation with DMM.
   • Turned the KEPCOs back on in reverse order to how they were turned off.
   • Measured voltages on the hot side of the DIN blocks, confirmed that they were as expected.
5. Prepared a 12AWG aLIGO style power cable to connect to the 1U chassis. A reel of this cabling, with yellow shielding, is located ~halfway along under the EW arm. Koji prepared the actual connector and housed it in a DSUB shell as per aLIGO wiring color scheme.
6. Installed the power cabling to one set of our 3 newly installed +/-24V DC power supplies.
7. Inserted fuses into the hot DIN blocks, measured voltage at connector end of our newly installed power cable. At first, I forgot to check if the fuse blocks had fuses inside, but after this was rectified, voltages were as expected .

The c1lsc frontend models crashed for some reason during this procedure. Now the c1sus frontend model is also behaving weirdly. It is unclear to me if/how this work would have led to these problems, but the temporal correlation (but not causation?) is undeniable.

I was forced into a simultaneous power-cycle rebooting of the three vertex FEs just now. I took the opportunity to completely disconnect the c1sus expansion chassis from all power and then restart it.

Everything is back up right now, and the weird timing issues I noticed in the sus model seem to be gone now (I'll need a longer baseline to be sure and I'll post a trend of the CPU timing tomorrow). It's disconcerting that apparently the only way to get everything back up and running is the nuclear option of power-cycling all FE related electronics. I was considering borrowing an ADC adapter card from the Y end and measuring the calibrated IR ALS noise with the digital system, but if I'm going to have to go through this whole dance each time I do a model recompile on c1lsc (which I'm going to have to in order to get the extra ADC recognized), I'm wondering if it's just better to wait till we get the new adapter cards we ordered. I think I'm going to work on tuning the input coupling into the fiber at EX in the next couple of days instead.

I made a LISO fit of the measured TF of the daughter board, so that I can digitally invert the daughter board whitening. Results attached. (Inverse) Filters have been uploaded to the ALS X Foton filter banks.

• Locked single arms, dither aligned, and saved offsets to EPICS (slow) sliders in anticipation of having to reboot all vertex FEs.
• Shutdown ETMY watchdog, stopped all models on c1iscey, and shutdown that frontend.
• Walked down to Y-end, powered of c1iscey expansion chassis, and removed the ADC adaptor card.
• Stopped all models on c1lsc. Shutdown watchdog on all optics in anticipation of c1sus model failing. Shutdown the c1lsc frontend.
• Powered off the c1lsc expansion chassis. Installed the borrowed adapter card from c1iscey in c1lsc expansion chassis. Connected it to the "spare" ADC card Koji and I had installed in c1lsc expansion chassis last Wednesday.
• Connected differential output of demod board to differential input of AA chassis. Connected SCSI connector from output of AA chassis to the newly installed adapter card.
• Powered the c1lsc expansion chassis back on. Then powered c1lsc FE on.
• Walking back out to the control room, I saw that all vertex FEs had crashed. I had to go back in and hard-reboot c1sus.
• Before bringing back any models, I backed up the existing c1lsc model, and then modified c1x04 and c1lsc to use the newly acquired ALS signals for the X arm ALS signal chain.
• Restarted all vertex FE models. Everything came back up smooth. DC light is still red on c1oaf but I didn't bother trying to rectify it tonight for these tests.
• Reset appropriate LSC offsets with PSL shutter closed. Locked X arm on IR. Reset phase tracker servo gain for X arm ALS. Engaged slow temperature servo on EX laser.

Then I looked at  the spectrum, see Attachment #1. Disappointingly, it looks like the arm PDH servo is dominating the noise, and NOT unsuppressed EX laser frequency noise,. Not sure why this is so, and I'm feeling too tired to debug this tonight. But encouragingly, the performance of the new ALS signal chain looks very promising. Once I tune up the X arm loop, I'm confident that the ALS noise will be at least as good as the reference trace.

I am leaving c1iscey shutdown until this is fixed. So ETMY is not available for the moment.

Random factoid: Trying to print a DTT trace with LaTeX in the label text on pianosa causes the DTT window to completely crash - so if you dont save the .xml file, you lose your measurement.

[koji, gautam]

I was going to head out but then it occurred to me that I could do another simple test, which is to try and lock the X arm on ALS error signal (i.e. actuate on MC length to keep the beat between EX laser and PSL fixed, while the EX frequency is following the Xarm length). Comparing the in loop (i.e. ALS) error signal with the out-of-loop sensor (i.e. POX), it seems like POX is noisy. The curves were lined up by eye, by scaling the blue curve to match the red at the ~16Hz peaks. This supports my hypothesis in the previous elog. On the downside, could be anything. Electronics in the POX chain? The demod unit itself? Will look into it more tomorrow..

As an aside, controlling the arm with ALS error signal worked quite well, and the lock was maintained for ~1 hour.

[Kira, Gautam]

I ceated a simple circuit that takes in 15V and outputs precisely 5V by using a 12V voltage regulator LM7812 and an AD586 that takes the output of the voltage regulator and outputs 5V (attachment 1). We plugged this into the slow channel and will leave it running for a few hours to see if we still have the fluctuations we observed earlier and also fit the noise curve. We'll also test the fast channel later as well. Attachment 2 shows the setup we have in the lab, with the red and white cable plugged into the +15V power supply and the red and black cable connected to the slow channel.

Bulb went out ~10am today. Looks like the lifetime of this bulb was <100 days.

Steve: bulb is arriving next week

[kevin, gautam]

we tested my noisy POX hypothesis tonight. By locking the single arm with POX, the arm length is forced to follow PSL frequency, which is itself slaved to IMC length. From Attachment #1, there is no coherence between the arm control signal and MC_F. This suggests to me that the excess noise I am seeing in the arm control signal above 30 Hz is not originating from the PSL. It also seems unlikely that at >30Hz, anything mechanical is to blame. So I am sticking with the hypothesis that something is wonky with POX. For reference, a known "normal" arm control signal spectrum looks like the red curve in this elog.

[kevin, gautam]

Kevin suggested I shouldn't be so lazy and test the POY spectrum as well. So we moved the timing card back to c1iscey, went through the usual dance of vertex machine reboots, and then got both single arm locks going. Attached spectrum shows that both POX and POY are noisy. I'm not sure what has changed that could cause this effect. The fact that both POX and POY appear uniformly bad, but that there is no coherence with MC_F, suggests to me that perhaps this has something to do with the work I did with Koji w.r.t. the power situation at the LSC rack. But we just checked that

1. All the demod board front panel LED indicators are green.
2. Marconi and all RF amplifier boxes are on (but we didn't actually measure any RF power levels yet tonight).
3. We checked the KEPCO power supplies in the little cabinet along the Yarm, and all of them are reporting the correct voltages/currents as per Steve's (recently updated) labels.
4. Checked the expansion chassis at the LSC rack for any red lights, there were none.

Another observation we made: note the huge bump around 70Hz in both arm control signals. We don't know what the cause of this is. But we occassionally noticed harmonics of this (i.e. 140, 210 Hz etc) appear in the control signal spectra, and they would grow with time - eventually, the X arm would lose lock (though the Y arm stayed locked).

I'm short on ideas for now so we will continue debugging tomorrow.

Unrelated to this work: Kevin reminded me that the high-pitched whine from the CRT TVs in the control room (which is apparently due to the flyback transformer) is DEAFENING. It's curious that the "chirp" to the eventual 15kHz whine is in opposite directions for the QUAD CRTs and the single display ones. Should be a Ph6 experiment maybe.

Update 2:30pm Mar 13: The furthest back I seem to be able to go in time with Frames is ~Jan 20 2018. Looking for a time when the arms were locked from back then, it seems like whatever is responsible for a noisy POX and POY was already a problem back in January. See Attachment #2. So it appears that the recent work at 1Y2 is not to blame...

I have attached the setup I completed today. The metal box contains the heater circuit and the board for the temperature sensor is right above it. This is basically the same setup as before, but I've just packaged everything up neater. I expect to be able to perform the test tomorrow and begin implementing PID control. I still need a DAC input for the heater circuit and the temperature sensor is having some issues as well.

Pumpdown 80 at 511 days and pd80b at 218 days

Valve configuration:  special vacuum normal, annuloses are not pumped at 3 Torr, IFO pressure 7.4e-6 Torr at vac envelope temp 22 +- 1C degrees

The working hypothesis, since the excess noise in single arm locks is coherent between both arms, the excess sensing noise is frequency noise in the IMC locking loop (sensing because it doesn't show up in MC_F). I've started investigating the IMC sensing chain, starting with the power levels of the RF modulation source. Recall that we had changed the way the 29.5MHz signal was sent to the EOM and demod electronics in 2017. With the handheld RF power meter, I measured 13.2dBm coming out of the RF distribution box (this is routed straight from the Wenzel oscillator). This is amplified to 26dBm by an RF amplifier (ZHL-2-S) and sent to the EOM, with a coupled 16dBm part sent to a splitter that supplies the LO signal to the demod board and also the WFS boards. Lydia made a summary of expected RF power levels here, and I too seem to have labelled the "nominal" LO level to the MC_REFL demod board as +5dBm. But I measured 2.7dBm with the RF power meter. But looking closely at the schematic of the splitting circuitry, I think for a (measured) 16.7dBm input to it, we should in fact expect around 3dBm of output signal. So I don't know why I labelled the "nominal" signal level as 5dBm.

Bottom line: we are driving a level 17 mixer with more like +14dBm (a number inferred from this marked up schematic) of LO, which while isn't great, is unlikely to explain the excess noise I think (the conversion loss just degrades by ~1dB). So I will proceed to check further downstream in the signal chain.

[koji, gautam]

1. I began my investigations by measuring the voltage noise of the demod board outputs with an SR560 (G=100) and SR785 in the audio band.
   • Measurement made with PSL shutter closed, LO input of demod board driven with the nominal level of ~2.5dBm, RF input terminated.
   • Motivation was to look for any noise features.
   • Expected noise level is ~2nV/rtHz (Johnson noise of 50ohm) since there are no preamp electronics post SCLF-5 LP filter on this board.
   • Attachment #1 shows the results of the measurement for a few scenarios. Spectra only shown for the I channel but the Q channel was similar. The LO=+5dBm curve corresponds to driving the input at 5dBm with a marconi, to see if the label of the nominal level being +5dBm had anything to it.
   • The arches above 1kHz seemed suspicious to me, so I decided to investigate further.
2. Looking at the IMC Demod board schematic, I I saw that there were 2 ERA-5SMs in there which are responsible for amplifying the 29.5MHz signal which serves as the LO to the oscillators.
3. I pulled the demod board out and tested it on the electronics workbench. Koji and I couldn't make sense of the numbers we were seeing (all measurements made with Agilent analyzer and active FET probe with 100:1 attentuator).
4. We eventually concluded that the ERA-5SMs were not exhibiting the expected gain of ~20dB. So we decided to swap these out.
5. This sort of measurement is not ironclad as the output of the ERA-5SM goes to the mixer whose input impedance is dynamically varying as the diodes are switching. So even after replacing the suspect amplifiers with new ones, we couldn't make the numbers jive.
6. We suspected that the new amplifiers were getting saturated. The 3dB saturation point for the ERA-5SM is spec'ed as ~19dBm.
   • We "measured" this by varying the input signal level and looking for deviation from linearity.
   • We saw that there was ~1dB compression for ~13dBm output from the ERA-5SM (after correcting for all attenuators etc). But this number may not be accurate in the absolute sense because of the unknown input impedance of the mixer.
   • Moreover, looking at the spec sheet for the mixer, JMS-1H, we found that while it wasn't ideal to operate the mixer with the LO level a few dBm below the expected +17dBm, it probably wasn't a show stopper.
7. So we figured that we need 10dB of attenuation between the "nominal" LO input level of 2.7dBm and the input of the demod board in order to keep the ERA-5SM in the linear range. This has now been implemented in the form of an SMA attenuator.
8. IMC locked straight away. But I noticed that PC drive RMS level was unusually large.
9. I found that by increasing the "IN1" gain of the CM board to 12dB (from 2dB) and the "VCO gain" to 10dB (from 7dB), I could recover a transfer function with UGF ~140kHz and PM ~30degrees (need more systematic and wider span measurements of this, and also probably need to optimize the crossover gains). See Attachment #2 for my quick measurement tonight.
10. Updated mcup to reflect these new gains. Tested autolocker a few times, seems to work okay.
11. While it presumably was a good thing to replace the faulty amplifiers and prevent them from saturating, this work has not solved the primary problem of excess frequency noise on the PSL.

It is not clear to me why installing an attenuator to prevent amplifier saturation has necessitated a 10dB increase in the IN1 gain and 3dB increase in the VCO gain. Initially, I was trying to compensate for the gain by increasing the FSS "Common Gain" but in that setting, I found an OLTF measurement impossible. The moment I enabled the excitation input to the CM board, the lock was blown, even with excitation amplitudes as small as -60dBm (from the Agilent network analyzer).

This may also be a good opportunity to test out one of the aLIGO style FET mixer demod boards (recall we have 2 spare from the 4 that were inside the ALS demod box). I'm going to ask Steve to package these into a 1U chassis so that I can try that setup out sometime. From a noise point of view, the aLIGO boards have the advantage of having a x100 preamp stage straight after the mixer+LPF. We may need to replace the lowpass filter though, I'm not sure if the one installed is 1.9MHz or 5MHz.

I've left an SR785 and AG4395 near 1X2 in anticipation of continuing this work tomorrow.

Unrelated to this work - seems like the WFS DC and RF offsets had not been set in a while so I reset these yesterday. The frequent model restarts in recent times may mean that we have to reset these to avoid using dated offset values.

Re-measured the demod board noises after replacing the suspect ERA-5SMs, with LO driven by a marconi at the "nominal" level of 2.5dBm, and RF input terminated. Attachment #1 is the input referred voltage noise spectra. I used the FET low noise pre-amp box for this purpose. I cannot explain the shape of the spectra above 1kHz. I tried doing the measurement on a minicircuits mixer (non-surface mount) and found the shape to be flat throughout the SR785 span. Unclear what else could be going on in the demod board though, all the other components on it are passive (except the ERA-5SMs which were replaced). I considered adopting a PMC style demod setup where we do the demod using some separate Minicircuits Mixer+LowPass filter combo. But the RF flashes for the IMC monitored at the RFmon port are ~0.2Vpp, and so the RF input to the mixer is expected to be ~2Vpp. The minicircuits mixer selection guide recommends choosing a diode mixer with LO level at least 10dBm above the expected RF input signal level, and we don't have any standalone mixers that are >Level 7. I've asked Steve to package the aLIGO demod board in the meantime, but even that might not be a plug and play replacement as the IF preamp stage has ~120degrees phase lag at 1MHz, which is significantly higher than the existing board which just has a SCLF5 low pass filter after the mixer and hence has <45degrees phase lag at 1MHz.

The MOSFET was getting pretty hot, so I switched it out to a larger heat sink and it's fine now. I then used a function generator in place of the DAC to provide ~3.5V. I got the current in the circuit to 1.7A, which is as expected, since we have 24V input, the heater resistance is 12.5ohm and the resistor we are using is 1ohm, so 24V/(12.5+1)ohm = 1.7A. The temperature inside the can rose about 5 degrees in half an hour. The only issue now is the voltage regulators and OP amp inside the box get hot, though it doesn't seem to be dangerous. I switched the function generator input to a DAC and Gautam set it to 1.5V. If it works, then we'll leave this on overnight and work on the PID control tomorrow. I've attached images of the current heater circuit box when it is open and the new heat sink for the MOSFET.

gautam: we also tried incorporating the EPICS channels from the Acromag into the RTCDS so that we can implement PID control by using Foton. I tried doing this using the "EpicsIn" and "EpicsOut" blocks from CDS_PARTS. While the model recompiled smoothly, I saw no signals in the filter module i had connected in series with the EpicsIn block. So I just reverted c1pem to its original state and recompiled the model. Guess we will stick to python script PID reading EPICS channels to implement the PID servo.

according to the temp sensor readout, which was ~-3.35V which corresponds to ~335K, the temperature of the can is now 60 deg C. This is a bit warm for my liking so i'm turning the heater current down to 0 now by writing 0 to C1:PEM-SEIS_EX_TEMP_CTRL

This elog by koji inspired me to consider power supply as a possible issue.

The demod board receives +/-24V DC (which is regulated down to +/-15V DC by 7815/7915), and also +15V DC via the backplane. The ERA-5SM receives DC power from the latter (unregulated) +15V DC. I can't think of why this is the case except perhaps the regulators can't source the current the amp wants? In any case, it doesn't look feasible to change this by cutting any traces on the PCB to me. While I had the board out, I decided to replace the JMS-1H mixers in a last ditch effort to improve the demod board noise. Unfortunately I'm having trouble de-soldering these MCL components from the board. So for now, I'm leaving the demod board out, IMC unlocked. Work will continue tomorrow. 

After some persistence, I managed to get the mixers off.

• Having gotten the mxiers off, I decided to temporarily solder on 50ohms between the LO pin pad and ground on the demod board and measure the RF signal levels in the LO chain with the active probe again.
• Today, with this change, I confirmed that the ERA-5SM begins to saturate closer to the +19dBm advertised on its datasheet. So we need only 2dB of attenuation at the input to have 17dBm at the LO pin of the mixer, assuming 50ohm input impedance.
• But this begs the question - what does minicircuits mean by a Level-YY mixer? Do they expect YY dBm delivered to a 50ohm load? Or do we need to supply YY dBm accounting for the dynamically changing input impedance of the mixer, as monitored by a high impedance probe?
• I soldered on some new mixers (JMS-1H) I procured from Downs earlier today.
• Re-installed the demod board in the eurocrate.

Unfortunately, the coherent noise between the arms persists so the sensing noise injection must be happening elsewhere. IMC seems to lock fine though so I'm leving the autolocker on

Light bulb replaced.

As discussed at the meeting, I decided to calibrate the MC error point into physical units of Hz/rtHz (a.k.a. the PDH discriminant). This is to facilitate the debugging of the hypothesized excess IMC sensing noise. I did this as follows.

1. Trust the POX calibration that was last updated in Aug 2017.
2. Hook up spare DAC channel (piped from LSC rack to 1X2) to IN2 of IMC CM board.
3. Inject excitation into MC error point via "IN2" input of the common board. For an excitation of 30cts with the IN2 gain at -32dB, I was able to see a peak in the calibrated X arm control signal that was ~x10 above the nominal noise level around 150Hz without seeing any nonlinear coupling effects in the DTT spectrum (I'm assuming 150Hz is sufficiently above the UGF of the X arm locking loop such that no loop correction is necessary).
4. Took a spectrum of the IMC error signal, teed off into the SR785 at the I output of the demod board with the same linewidth as the DTT spectrum.
5. Confirmed that without any excitation,
6. Did the math to make these two peaks line up. The resulting calibration is: 13kHz/Vrms.

Math details:

• DTT peak height @ 150 Hz with Hanning window, 25 avgs = 1.97e-4 nm/rtHz (See Attachment #1).
• X arm cavity length = 37.79m, using which the above number becomes 1.47 Hz/rtHz.
• Peak height in SR785 spectrum with Hanning window, 25 avgs = 1.13e-4 Vrms/rtHz (See Attachment #2).
• Dividing, we get 13kHz/Vrms.

Using this, I can now make up a noise budget of sorts for the IMC sensing.

gautam 20180327 4.30pm: I re-checked the PDH error signal calibration using the oscilloscope method. Attachment #3 shows the PDH I and Q error signals and also the output of the RF monitor port, during a TEM00 flash. This attachment should be compared to Attachment #2 of elog 12822, and the answer lines up quite well. From my Finesse model of the IMC, I calculated that the x-axis of the PDH horn-to-horn is ~12.3kHz. Comparing to the top row of Attachment #3, I get a PDH error signal calibration of ~12.4kHz/Vrms, which lines up well with the number quoted above. So I trust my calibration, and hence, the y-axis of my noise budgets in reply to this elog.

I did a preliminary noise budget of the transmitted frequency noise of the IMC. Attachment #1 shows the NB. I'm going to use this opportunity to revisit my IMC modeling. Some notes:

1. The blue, green and red traces are from my measurement of the voltage noise of the demod board with LO driven by Marconi, RF input terminated, measured using the FET preamp + SR785, and calibrated into Hz/rtHz using the number from the immediate preceeding entry.
2. The grey trace is measured by closing the PSL shutter, manually engaging the POX11 whitening, and looking at the calibrated POX. This sensing noise is ~100x higher than the IMC curves - but I think this makes sense as for the IMC, I am measuring directly at the output of the demod board, whereas for POX, the signal goes through the whole whitening infrastructure first.
3. The purple trace is the calibrated X-arm control signal converted to Hz/rtHz.
4. I've only showed the region up to ~1kHz as this is where the excess noise was seen in the original ALS study that precipitated this whole investigation.

Conclusion: From this study, assuming my PDH discriminant calibration was correct, looks like IMC demod / POX11 demod electronics noises are not to blame (this surprises me since there were apparently so many things wrong on the demod board, and yet that wasn't the worst thing in the IMC chain it would seem ). The POX11 photodiode "dark" noise is also not the problem I think, given the grey curve. Next curve to go on here is the demod board noise with the PSL shutter closed but the IMC REFL PD connected to the RF input (or maybe even better, have light on the PD, but macroscopically misalign MC2 so there is no 29.5MHz PDH signal), just to make sure there isn't anything funky going on there...

I've added two curves to the NB. Both are measured (with FET preamp) at the output of the demod board, with the LO driven at the nominal level by the Wenzel RF source pickoff (as it would be when the IMC is locked) and the RF input connected to the IMC REFL PD. For one curve, I simply closed the PSL shutter, while for the other, I left the PSL shutter open, but macroscopically misaligned MC2 so that there was no IMC cavity. So barring RFAM, there should be no PDH signal on the REFL PD, but I wanted to have light on there. I'm not sure if I understand the difference between these two curves though, need to think on it. Perhaps the IMC REFL PD's optical/electrical response needs to be characterized?

we don't ever want to use our 16 kHz real time system for such low frequency action; its main purpose is for real-time controls, whereas we are OK with multiple seconds of delay in a thermal loop. The Python PID script is sufficient and highly reliable (after years of testing).

I fit the data that we got from the test. The time constant for the cooling came out to be about 4.5 hours. The error is quite large and we should add a low pass filter to the temperature sensor eventually in order to minimize the noise of the measurements.

CC1 old MKS cold cathode gauge randomly turns on- off. This makes software interlock close VM1 to protect RGA  So the closed off RGA region pressure goes up and the result is distorted RGA scan.

CC1 MKS gauge is disconnected and VM1 opened. This reminds me that we should connect our interlocks to CC1 Hornet Pressure gauge.

[Gautam, Arijit]

PMC and IMC re-aligned and re-locked. Both cavities are staying locked. Arm cavities are also locked.

I made sketches of the final setup. There will be a box in the rack that contains both the heater circuit and the temperature sensor boards. One of them is in the loop while the other isn't. Instead of having many cables leading to the can, there will only be these three, though they can be made into a single wire. It will be connected to the can through a D-9 connector. The second attachment is what will be inside of the box, with all the major wires and components labeled.

-----

Edit: I've canged the layout to (hopefully) make the labels easier to read. I've also added in a cable to the ADC that reads out the voltage across the 1 ohm resistor. I also attached the circuit diagrams for the heater circuit and the temperature sensors. The one for the heater circuit was made by Kevin and I used the same design, except I have LM7818 and LM7918, since the 15V ones were not available at the time I made the circuit. 

In addition, all the wires leading to the can will all be part of one bundle of wires (I didn't clearly indicate it as such). There will be a total of 6 wires: two are needed for the wire to supply power to the heater and will have a LEMO connector on the rack end and two are needed for each temperature sensor, which will be attached to the board directly on the rack end. 

Also, we don't need two voltage regulators for each temperature circuit. We can just have one of each of LM7815 and LM7915 to supply +/- 15V to the boards.

Todd informed me that the ADC Timing adaptor boards we had ordered arrived today. I had to solder on the components and connectors as per the schematic, though the main labor was in soldering the high density connectors. I then proceeded to shut down all models on c1lsc (and then the FE itself). Then classic problem of all vertex machines crashing when unloading models on c1lsc happened (actually Koji noticed that this was happening even on c1ioo). Anyways this was nothing new so I decided to push ahead. 

I had to get a cable from Downs that connects the actual GS ADC card to this adaptor board. I powered off the expansion chassis, installed the adaptor board, connected it to the ADC card and restarted the expansion chassis and also the FE. I also reconnected the SCSI cable from the AA board to the adaptor card. It was a bit of a struggle to get all the models back up and running again, but everything eventually came back(after a few rounds of hard rebooting). I then edited the c1x04 and c1lsc simulink models to reflect the new path for the X arm ALS error signals. Seems to work alright.

At some point in the afternoon, I noticed a burning smell concentrated near the PSL table. Koji traced the smell down to the c1lsc expansion chassis. We immediately powered the chassis off. But Steve later informed me that he had already noticed an odd burning smell in the morning, before I had done any work at the LSC rack. Looking at the newly installed adaptor card, there wasn't any visual evidence of burning. So I decided to push ahead and try and reboot all models. Everything came back up normally eventually, see Attachment #1. Particle count in the lab seems a little higher than usual (actually, according to my midnight measurement, they are ~factor of 10 lower than Steve's 8am measurements), but Steve didn't seem to think we should read too much into this. Let's monitor the situation over the coming days, Steve should comment on the large variance seen in the particle counter output which seems to span 2 orders of magnitude depending on the time of the day the measurement is made... Also note that there is a BIO card in the C1LSC expansion chassis that is powered by a lab power supply unit. It draws 0 current, even though the label on it says otherwise. I a not sure if the observed current draw is in line with expectations.

The spare (unstuffed) adaptor cards we ordered, along with the necessary hardware to stuff them, are in the Digital FE hardware cabinet along the east arm.

Steve:  particle count in the 40m is following outside count, wind direction, weather condition .....etc. The lab particle count is NOT logged ! This is bad practice.

While Kevin and Arijit were doing their MC_REFL PD noise measurements (which they will elog about separately shortly), I noticed a feature around 600kHz that reminded me of the NPRO noise eater feature. This is supposed to suppress the relaxation oscillation induced peak in the RIN of the PSL. Surprisingly, the noise eater switch on the NPRO front panel was set to "OFF". Is this the normal operating state? I thought we want the noise eater to be "ON"? Have to measure the RIN on the PSL table itself with one of the many available pick off PDs. In any case, as Attachment #1 showed, turning the noise eater back on did not improve the excess IMC frequency noise.

[Kira, Gautam]

We setup the channels for PID control of the seismometer can. First, we ssh into c1auxex and went to /cvs/cds/caltech/target/c1auxex2 and found ETMXaux.db. We then added in new soft channels that we named C1:PEM-SEIS_EX_TEMP_SLOWKP, C1:PEM-SEIS_EX_TEMP_SLOWKI, C1:PEM-SEIS_EX_TEMP_SLOWKD that will control the proportional, integral and differential gain respectively. These channels are used in the script FSSSlow.py for PID control. We then had to restart the system, but first we turned off the LSC mode and then shut down the watchdog on the X end. After doing the restart, we disabled the OPLEV as well before restarting the watchdog. Then, we enabled the LSC mode again. This is done to not damage any of the optics during the restart. The restart is done by using sudo systemctl restart modbusIOC.service and restarted with sudo systemctl status modbusIOC.service. Then, we made sure that the channels existed and could be read and writtten to, so we tried z read [channel name] and it read 0.0. We then did z write [channel name] 5, and it wrote 5 to that channel. Now that the channels work, we can implement the PID script and check to make sure that it works as well.

Kevin, Gautam and Arijit

We made a measurement of the MC_REFL photodiode transfer function using the network analyzer. We did it for two different power input (0dB and -10dB) to the test measurement point of the MC_REFL photodiode. This was important to ensure the measurements of the transfer function of the MC_REFL photodiode was in the linear regime. The measurements are shown in attachment 1. We corrected for phase noise for the length of cable (50cm) used for the measurement. With reference to ELOG 10406, in comparison to the transimpedance measurement performed by Riju and Koji, there is a much stronger peak around 290MHz as observed by our measurement.

We also did a noise measurement for the MC_REFL photodiode. We did it for three scenarios: 1. Without any light falling on the photodiode 2. With light falling on the photodiode, the MC misaligned and the NPRO noise eater was OFF 3. With light falling on the photodiode, the MC misaligned and the NPRO noise eater was ON. We observed that the noise eater does reduce the noise being observed from 80kHz to 20MHz. This is shown in attachment 2.

We did the noise modelling of the MC_REFL photodiode using LISO and tried matching the expected noise from the model with the noise measurements we made earlier. The modeled noise is in good agreement with the measured noise with 10Ohms in the output resistance. The schematic for the MC_REFL photodiode however reveals a 50Ohm resistance being used. The measured noise shows excess noise ~ 290MHz. This is not predicted from the simplied LISO model of the photodiode we took.

Discussion with Koji and Gautam revealed that we do not have the exact circuit diagram for the MC_REFL photodiode. Hence the simplified model that was assumed earlier is not able to predict the excess noise at high frequencies. One thing to note however, is that the excess noise is measured with the same amplitude even with no light falling on the MC_REFL photodiode. This means that there is a positive feedback and oscillation in the op-amp (MAX4107) at high frequencies. One way to refine the LISO model would be to physically examine the photodiode circuit.

We also recorded the POX and POY RF monitor photodiode outputs when the interferometer arms are independently stabilized to the laser. Given the noise outputs from the RF photodiodes were similar, we have only plotted the POY RF monitor output for the sake of clarity and convenience.

I've removed the MC REFL PD unit from the AS table for investigation. So MC won't lock.

PSL shutter was closed and location of PD was marked with sharpie (placing guides to indicate position wasn't convenient). I also kapton taped the PD to minimize dust settling on the PD while I have it out in the electronics area. Johannes has the camera, and my cellphone image probably isn't really high-res enough for diagnostics but I'm posting it here anyways for what it's worth. More importantly - the board is a D980454 revision B judging by the board, but there is no schematic for this revision on the DCC. The closest I can find is a D980454 Rev D. But I can already see several differences in the component layout (though not all of them may be important). Making a marked up schematic is going to be a pain . I'm also not sure what the specific make of the PD installed is.

The lid of the RF cage wasn't on.

More to follow tomorrow, PD is on the electronics workmench for now...

gautam 28 March 2018: Schematic has been found from secret Dale stash (which exists in addition to the secret Jay stash). It has also been added to the 40m electronics tree.

MCRefl is absent, it is under investigation. I removed a bunch of hardware and note all spare optics along the edges.

Till RIN measurement noise eater is off on 2W laser. The inno 1W  has no noise eater.

2010 power v current table is below.

I re-installed the MC REFL photodiode. Centered beam on the PD by adjusting steering mirror to maximize the DC signal level (on o'scope) at the DC monitoring port. Curiously, the DC level on the scope (high-Z) was ~2.66V DC, whereas the MEDM screen reports ~twice that value, at ~5.44 "V". We may want to fix this "calibration" (or better yet, use physical units like mW). Noise-eater On/Off comparison of MC error signals to follow.

Kevin, Gautam and Arijit

We did a optical measurement of the MCREFL_PD transimpedance using the Jenny Laser set-up. We used 0.56mW @1064nm on the NewFocus 1611 Photodiode as reference and 0.475mW @1064nm on the MCREFL_PD. Transfer function was measured using the AG4395 network analyzer. We also fit the data using the refined LISO model. From the optical measurement, we can see that we do not have a prominent peak at about 300MHz like the one we had from the electrical transimpedence measurement. We also put in the electrical transimpedence measurement as reference. RMS contribution of 300MHz peak to follow.

As per Rana`s advice I have updated the entry with information on the LISO fit quality and parameters used. I have put all the relevant files concerning the above measurement as well as the LISO fit and output files as a zip file "LISO_fit" . I also added a note describing what each file represents. I have also updated the plot with fit parameters and errors as in elog 10406.

[Kira, Gautam]

We closed the loop today and implemented the PID script. I have attached the StripTool graph for an integral value of 0.5 and proportional value of 20. We had some issues getting it to work properly and it would oscillate between some low values of the control voltage. The set point here was -3.20, which corresponds to about a 20 degree increase in temperature. The next step would be to find which values of Kp, Ki, and Kd would work in this case and low pass filter the signal from the temperature sensor, and also create an MEDM screen for easier PID control.

Kevin, Gautam and Arijit

Today we performed the in-loop noise measurements of the MCREFL-PD using the SR785 to ascertain the effect of the Noise Eater on the laser. We took the measurements at the demodulated output channel from the MCREFL-PD. We performed a series of 6 measurements with the Noise Eater ''ON'' and ''OFF''. The first data set is an outlier probably, due to some transient effects. The remaining data sets were recorded in succession with a time interval of 5 minutes each between the Noise Eater in the ''ON'' and ''OFF'' state. We used the calibration factor of 13kHz/Vrms from elog 13696 to convert the V_rms to Hz-scale.

The conclusion is that the NOISE EATER does not have any noticeable effect on the noise measurements.

ALS beat spectrum and also the arm control signal look as they did before. coherence between arm control signals (in POX/POY lock) is high between 10-100Hz, so looks like there is still excess frequency noise in the MC transmitted light. Looking at POX as an OOL sensor with the arm under ALS control shows ~10x the noise at 100 Hz compared to the "nominal" level, consistent with what Koji and I observed ~3weeks ago.

We tried swapping out Marconis. Problem persists. So Marconi is not to blame. I wanted to rule this out as in Jan, Steve and I had installed a 10MHz reference to the rear of the Marconi.

I have been working on the aux beat setup on the PSL table between 9PM-3AM.

This work involved:

- Turning off the main marconi
- Turning off the freq generation unit (incl IMC modulation)
- Closing the PSL shutter

After the work, these were reverted and the IMC and both arms have been locked.