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  13646   Wed Feb 21 12:17:04 2018 gautamUpdateCDSLO Power mon channels added to c1lsc

To make this setup more permanent, I modified the c1lsc model to pipe the LO power monitor signals from the Demod chassis to unused channels ADC_0_25 (X channel LO) and ADC_0_26 (Y channel LO) in the c1lsc model. I also added a couple of CDS filter blocks inside the "ALS" namespace block in c1lsc so as to allow for calibration from counts to dBm. I didn't add any DQ channels for now as I think the slow EPICS records will be sufficient for diagnostics. It is kind of overkill to use the fast channels for DC voltage monitoring, but until we have acromag channels readily accessible at 1Y2, this will do.

Modified model compiled and installed successfully, though I have yet to restart it given that I'll likely have to do a major reboot of all vertex FEs frown

  13647   Wed Feb 21 17:20:32 2018 johannesUpdateVACHornet gauge connected to DAQ.

I wired the six available BNC connectors on the front panel of the new XEND slow DAQ to physical Acromag channels. There were two unused ADC channels and eight DAC channels, of which I connected four. The following entries were added to /cvs/cds/caltech/target/c1auxex2/ETMXAUX2.db /caltech/target/c1auxex2/ETMXaux2.db

Connector Acromag Channel EPICS Name
In1 XT1221C #6 C1:Vac-CC1_HORNET_PRESSURE_VOLT
In2 XT1221C #7 C1:PEM-SEIS_XARM_TEMP_MON C1:PEM-SEIS_EX_TEMP_MON
Out1 XT1541B #4 C1:PEM-SEIS_XARM_TEMP_CTRL C1:PEM-SEIS_EX_TEMP_CTRL
Out2 XT1541B #5 Not Assigned
Out3 XT1541B #6 Not Assigned
Out4 XT1541B #7 Not Assigned

C1:Vac-CC1_HORNET_PRESSURE_VOLT is converted to the additional soft channel C1:Vac-CC1_HORNET_PRESSURE in units of torr using the conversion  10^{(\mathrm{Voltage}-10)} stated in the manual. A quick check showed that the resulting number and the displayed pressure on the vacuum gauge itself agree to ~1e-8 torr. Gautam added the new EPICS calc channel to the C0EDCU and restarted FB, now the data is being recorded.

Three of the output channels do not have a purpose yet, so their epics records were created but remain inactive for the time being.

  13648   Thu Feb 22 00:09:11 2018 gautamUpdateALSD0902745 in-situ testing

I thought a little bit about the design of the preamp we want for the demodulated ALS signals today. The requirements are:

  1. DC gain that doesn't cause ADC saturation.
  2. Audio frequency gain that allows the measured beat signal spectrum to be at least 20dB the ADC noise level.
  3. Electronics noise such that the measured beat signal spectrum is at least 20dB above the input-referred noise of this amplifier.
  4. Low pass filtering at the input to the differential receiving stages, such that the 2f product from the demodulation doesn't drive the AD829 crazy. For now, I've preserved the second-order inductor based LPF from the original board, but if this proves challenging to get working, we can always just go for a first-order RC LPF. One challenge may be to find a 2.2uH inductor that is compatible with prototype PCB boards...
  5. Differential sending, since this seems to be definitively the lower noise option compared to the single-ended output (see yesterday's measurement). The plan is to use an aLIGO AA board that has differential receiving and sending, and then connect directly to the differential receiving ADC.

Attachment #3 shows a design I think will work (for now it's a whiteboard sketch, I''ll make this a computer graphic tomorrow). I have basically retained the differential sending and receiving capabilities of the existing Audio I/F amplifier, but have incorporated some whitening gain with a pole at ~150Hz and zero at ~15Hz. I've preserved the DC gain of 10, which seems to have worked well in my tests in the last week or so. Attachments #1 and #2 show the liso modelled characteristics. Liso does not support input-referred noise measurements for differential voltage inputs, so I had to calculate that curve manually - I suspect there is some subtlety I am missing, as if I plot the input referred noise out to higher frequencies, it blows up quite dramatically.

Next step is to actually make a prototype of this. I am wondering if we need a second stage of whitening, as in the current config, we only get 20dB gain at 150Hz relative to DC. Yesterday's beat spectrum measurement shows that we can expect the frequency noise of the ALS signal at ~100Hz to be at the level of ~1uV/rtHz, but this is is around the ADC noise level? If so, 20dB of whitening gain may be sufficient?

Quote:

Still have to make preamp prototype daughter board with the right whitening shape... This test suggests to me that I should also make the output differential sending...


*Side note: I was wondering why we need the differential receiving stage, followed by a difference amplifier, and then a differential sending stage. After discussing with Koji, we think this is to suppress any common-mode noise from the mixer outputs.

  13649   Thu Feb 22 10:49:11 2018 SteveUpdateElectronicsrack power supplies checked

All rack power supplies labeled if their load changed.

 

  13650   Thu Feb 22 16:11:14 2018 KojiUpdateGeneralaLIGO EOM crystal replacement

aLIGO EOM crystal replacement

  • The entire operation has been performed at the south flow bench @40m.
  • We knew that the original crystal in the aLIGO EOM we are testing has some problem. This was replaced with a spare RTP crystal.
  • Once the housing was removed, it was obvious that the crystal has a crack (Attachment 1).
    It seemed that it was produced by either a mechanical stress or a thermally induced stress (e.g. soldering).
  • I wanted to make sure the new crystal is properly aligned interms of the crystal axis.
    The original crystal has the pencil marking at the top saying "Z" "12". The new (spare) crystal has "Z" and "11".
    So the new crystal was aligned in the same way as the original one. (Attachment 2)
  • I took an opportunity to measure the distribution of the electrode lengths (Attachment 3). The lengths are 14, 5, and 14mm, respectively.
  13651   Thu Feb 22 16:16:43 2018 KiraUpdatePEMtemp sensor input

Rewired the temperature sensor inputs to Molex connectors so that we can now attach them to the +/- 15V Sorensens for input instead of using a power supply.

  13652   Thu Feb 22 17:19:47 2018 KojiUpdateGeneralModulation depth measurement for an aLIGO EOM

aLIGO EOM test: Setup

  • The modulation signal was supplied from an aux Marconi.
  • Between the Marconi and the EOM, a 20dB coupler (ZFDC-20-5) was inserted. There the Marconi was connected to the output port, while the EOM was to the input port. This way, we can observe how much of the RF power is reflected back to Marconi.
  • The beat setup (40m ELOG 13567) was used for the measurement. The EOM was placed in the beam path of the beat setup in the PSL side.
  • To eliminate the modulation sidebands of 11MHz and 55MHz, the 40m Marconi and the freq generator were turned off (in this order).
  • The nominal amplitude of the carrier beat note was -15dBm ~ -16dBm.
  • The cable from the source to the EOM was ~3m. And the loss of this cable was ~0.4dB.

Measurement

  • The EOM had three input ports. 
  1. 9MHz input - In reality, there was no matching circuit.
  2. Center port - matched at 24.1MHz and 118.3MHz. 24.1MHz port has no amplification (just matching), and 118.3MHz is resonant.
  3. 45.5MHz port - resonantly matched at 45.5MHz
  • The Marconi output power was set to be +13dBm. For the 45MHz measurement, 20dB attenuator is inserted right next to the Marconi so that the VSWR seen from the Marconi was improbed. (Marconi did not like the full reflection of unmatched circuit and shutdown due to the protection function.)
  • The amplitude ratios between the sidebands and the carrier were multiplied by a factor of 2, to obtain the modulaiton depths. ( BesselJ(1,m)/BesselJ(0,m) ~ m/2 )
     
  • The result is found in Attachment 2.
    • The center port showed the modulation response of 0.7mrad/V and 15mrad/V for 24.1MHz and 118.3MHz, respectively. This suggests that the amplification factor for 118.3MHz is ~x21.
    • The VSWR of the center port is below 1.5 at the target frequencies. That's as tuned in Downs and has not been changed by the crystal replace.
    • The 45MHz port has the modulation response of 0.034mrad/V. This later tuned out that the amplification of ~x19. The circuit is well matched at the resonant frequency.
       
  • The linearity was checked with the 45MHz port (Attachment 3). The input power (idrectly connected to the EOM without 20dB attn) was varied between -17dBm to +13dBm. There was no sign of non linearity.
     
  • The modulation response at 24MHz was compared at various input ports. (Attachment 4)
    • The input signal was amplified tobe 23dBm by ZHL-3A for better sideband visibility. The actual amplifier output was ~30dBm, and a 6dB ATTN was used to improve the VSWR to protect the amplifier.
    • The 9MHz port showed 3.6mrad/V and 1.8mrad/V with the port unterminated and terminated, respectively. This factor of two difference is as expected.
      This 1.8mrad/V is roughly x2.6 higher compared to the one of the matched 24/118MHz port. This is close number to the ratio of the plate sizes (14mm/5mm = 2.8).
    • With the current condition, the 9MHz (unterminated), 9MHz (terminated), 24/118MHz, and 45MHz ports requires 22dBm, 27dBm, 36dBm, and 21dBm to realize the current modulation depth of 0.014 at 24MHz.
    • Comparing this matched 9MHz performance, the amplification of the 45MHz port at 45MHz was determined to be ~x19.
       
  • Considering these results, the modulation response of the center port at 24MHz seems too low. We don't want to supply 36dBm for the 0.014rad modulation (nominal number for H1).
    Here are some thoughts:
    • Use the 45MHz or 9MHz port for 24MHz modulation. Probably the unit is unmatched but, we can come up with the idea to improve the VSWR at 24MHz somehow?
    • Redistribute the plate length to have better modulation at 24MHz. Can we achieve sufficient modulation capability with the frequency of the long and short ports swapped? We hope that we don't need to start over the matching of the 24/118MHz again because the capacitances of the ports are almost the same.
  13653   Fri Feb 23 07:47:54 2018 SteveUpdateVACCC1 Hornet

We have the IFO pressure logged again! Thanks Johannes and Gautam

This InstruTech cold cathode ionization vacuum gauge " Hornet " was installed 2016 Sep 14

Here is the CC1 gauge history of 10 years from 2015 Dec 1

The next thing to do is put this channel C1:Vac-CC1_HORNET_PRESSURE  on the 40m Vacuum System Monitor   [ COVAC_MONITOR.adl ] 

gautam 1pm: Vac MEDM screen monitor has been edited to change the readback channel for the CC1 pressure field - see Attachment #2. Seems to work okay.

  13654   Fri Feb 23 20:46:04 2018 Udit KhandelwalSummaryGeneralCAD Summary 2018/02/23

I have more or less finished cadding the test mass chamber by referring to the drawings Steve gave me. Finer details like lugs and bolts and window flaps can be left for later. Here's a quick render:

  13655   Sun Feb 25 00:03:12 2018 gautamUpdateALSDaughter board prototyping

Using one of the prototype PCB boards given to me by Johannes, I put together v1 of this board and tested it. 

Attachment #1 - Schematic with stages grouped by function and labelled. 

Attachment #2 - Measured vs modelled Transfer function.

Attachment #3 - Measured vs modelled noise. Measurement shown only between positive output and ground, the other port is basically the same. I will update this attachment to reflect the expected signal level in comparison to the noise, but suffice it to say that given the measured input referred noise, we will have plenty of SNR between 0.1Hz and 10kHz. The single stage of whitening should also be sufficient to amplify the signal above ADC noise in the same frequency band

Attachment #4 - Positive output as viewed on a fast (300 MHz) scope using a Tektronix x1 voltage probe.

Attachment #5 - Daughter board noise with measured ALS noise overlaid (the gain of x10 on the existing audio pre-amp has been divided out). 

Comments:

  • I may have overlooked the GBW of the OP27 in the design - specifically, the negative feedback is wired for gain x100 at high frequencies, and so the input signal should be filtered above 8MHz/100 ~80kHz. But the LC poles are at ~500kHz. I wonder if the small deviation seen between modelled and masured TFs is reflecting this. Practically, the easier fix is to add a feedback capacitor that rolls off the gain at high frequencies. 300pF WIMA should do the trick, and we have these in stock.
  • I don't understand why the modelled response starts to roll off around 5kHz, even though the poles of the LC filter at the input stage are at 500kHz. This happens because at low frequencies, the 1.5uH inductor is basically a short - so the RC divider at the input of the Op27 has a pole at 1/2/pi/R/C ~5kHz for R=499, C = 68nF.
  • I am not sure what to make of the peaky comb seen in Attachment #3, but I'm pretty sure it's electronic pickup from something. The GPIB adapter power suppy is not to blame. The peaks are 10 Hz spaced.
  • From Attachment #4, I don't suspect any opamp oscillations given that the signal seen is tiny, but I don't know what amplitude is characteristic of an oscillating op amp, so I am not entirely confident about this conclusion. 
  • Initially while thinking about the design, I was trying to think of making the design generic enough that we could use these signals for high-bandwidth ALS control (a.k.a. Fast ALS) but in the current incarnation, no consideration was given to minimizing phase lag at high frequencies. 
  • Putting the PCB board together was more painful than I imagined as the board is configured for 4 single op amps whereas my design requires 5 - so I needed to do some trace cutting surgery. Rather than make 3 more of these, I'm just going to finish the characterization, and if the design looks good, we can get some custom PCBs printed.
  • Power decoupling caps (47nF) are added to all op amp power pins, but is not shown in the schematic.

Given the overall good agreement between model and measurement, I am going to test this with the actual RF beat. For this test, we will need a differential receiving AA board to interface the output of the daughter board with the ADC input

Quote:

Next step is to actually make a prototype of this.

  13656   Mon Feb 26 16:22:10 2018 KiraUpdatePEMtemp sensor input

[Kira, Gautam]

We began the setup for the lab temperature sensor today. First, we needed to add in a DIN fuse for both temperature sensors, which required us to shut down everything else first. To avoid having to do that next time, we made three instead of two spaces where we have + and - 15V. Attachment 1 shows the new fuses we installed, along with the fuses they connect to. Attachment 2 shows the wiring that we used to connect all the fuses. Attachment 3 shows the labeled long wires that are attached to the lab temperature sensor. The other end is labeled as well. I measured the voltage at the other end of the long cables, and while the -15V one looks good, the +15V one shows only about 13.5V. 

-----

edit (Tuesday) - I set up the other set of cables that will eventually lead to the sensor in the can, but neither of them are showing any voltage on the other end. I'll work on this issue tomorrow.


gautam: some additional remarks about the procedure followed:

  • Wires were tinned with solder to facilitate easier insertion into DIN fuse blocks.
  • ETMX watchdog was shutdown. I then unplugged the satellite box at the X end to avoid any sort of electrical impulse being sent to the optic.
  • Shut down all the sorensens in the EX rack.
  • Tapped new +15VDC and -15 VDC outputs at the EX rack in the locations Kira indicated.
  • Turned Sorensens back on. Checked that all voltages as reported by front panel monitor points were as they were expected to be.
  • Had some trouble getting the modbus IOC going after this work. Kept throwing an error that modbus couldn't be initialized by procserv. Ended up having to reboot c1auxex2, after which it worked fine.
  13657   Mon Feb 26 20:55:56 2018 ranaUpdateALSDaughter board prototyping

Looks good.

* for bypass type applications, you don't have to use Wima caps (which are bigger and more expensive). You can just use any old ceramic SMD cap.

* This seems like a classic case to use the 3 op-amp instumention amplifier config. This is similar, but not quite.

* Ought to use output resistors of ~50 Ohms by default in the output of any circuit. SInce this is a daughter board, maybe 10 Ohms is enough, but the eventual PCB should have pads for it.

  13658   Tue Feb 27 21:10:45 2018 gautamUpdateALSDaughter board testing

I thought a little bit about the next steps in testing the daughter board. The idea is to install this into the existing 1U chassis and tap the differential output from the FET Mixers as inputs to the daughter board. Looking at the D0902745 schematic, I think the best way to do this is to simply remove L3, L4, C10, C11, C15 and C16. I will then use the pads for L3 and L4 to pipe the differential output of the FET mixer to the differential input of the daughter board. 

The daughter board takes care of whitening the ALS signal.

Then we need to pipe the differential output of the daughter board into the differential input of a differential receiving AA board. Koji and Johannes surveyed the available stockpile from the WB workshop. The best option seems to be to use the available v5 of D070081 and install 4 of them into a 1U chassis unit (also available from WB EE shop). The v5s can be upgraded to v6 by replacing the set of input and output buffer OpAmps with AD8622, as per the revision history notes. Koji ordered 100pcs of these today. 

The input to the proposed 1U chassis housing these 8 AA boards (each with 8 channels) is a DB9 connector. The aLIGO demod board chassis that we use to demodulate the ALS signals has a nice DB25 output connector that supplies all the differential I and Q demodulated signals. But since we will install a daughter board, we will hae to hack together some connector solution anyways. I propose using a DB9 connector to pipe the outputs of the daughter board to the inputs of the AA board. Space is tight in the LSC rack, but I think we have space for a 1U chassis (see Attachment #3).

Finally - how to interface the AA board with the ADC? Koji and I discussed options, and seems like the least painful way will be to install a new ADC in the c1lsc expansion chassis in 1Y3. I checked the computer hardware cabinet and there seems to be 1 spare general standards 16bit ADC in there (see Attachment #1). Its health/providence is unknown. But Koji and I will test it after the meeting tomorrow. I also have another ADC card that Jamie and I removed from c1ioo sometime ago. I have labelled it as "GPIO0 LED RED", though I don't remember exactly what the problem was and can't find any elog about it. Incidentally, there are also 2 spare DAC cards available in the cabinet, although their health/rpovidence too is unknown. There are sufficient free slots in the c1lsc expansion chassis (see Attachment #2 though we will need a LIGO ADC adaptor card). Then we can just change the input ADC channels for the ALS signals in the c1lsc model.

In the short term, while the hardware for this plan is being put together, I can test the uncalibrated noise performance of the demod + daughter board combo (uncalibrated because I will make a measurement of voltage noise with an SR785 as opposed to frequency noise). A second daughter board will also need to be assembled - I'm just going to do it on another prototyping board as figuring out how to use Altium will probably take me longer. There is also the matter of fine tuning the polarization axes alignment of the input to the EX fiber coupler.

  13660   Wed Feb 28 12:31:28 2018 KiraUpdatePEMtemp sensor input

I switched out the DIN fuses for the long cables and it fixed the issue of them not showing any votage on the other end. At first, the +15V cable worked and the -15V didn't, but when I switched the fuse for the -15V it began working, but the +15V stopped working. I then switched out the fuse for +15V and both cables began showing voltage. But for both the long cables and the shorter ones, they show +13.4V instead of +15V. Not sure what's going on there.

  13661   Wed Feb 28 19:13:25 2018 gautamUpdateALSADC test for differential receiving in c1lsc

[koji, gautam]

we did a bunch of tests to figure out the feasibility of the plan I outlined last night. Bottom line is: we appear to have a working 64 channel ADC (but with differential receiving that means 32 channels). But we need an aLIGO ADC adaptor card (I'm not sure of the DCC number but I think it is D0902006). See attached screenshot where we managed to add an ADC block to the IOP model on c1lsc, and it recognizes the additional ADC. The firmware on the (newly installed) working card is much newer than that on the existing card inside the expansion chassis (see Attachment #1).

Details:

  • Watchdogged all optics because we expected messing around with c1lsc to take down all the vertex FEs. Actually, only c1sus was killed, c1ioo survived.
  • Closed PSL shutter. Shut down c1lsc FE machine.
  • Started out by checking the functionality of the two ADC cards I found.
  • Turns out the one Jamie and I removed from c1ioo ~6months ago is indeed broken in some way, as we couldn't get it to work.
  • Took us a while to figure out that we require the adaptor board and a working ADC card to get the realtime model to run properly. A useful document in understanding the IO expansion chassis is this one.
  • Another subtlety is that the ADC card we installed today (photo in previous elog) is somewhat different from the ones installed in c1sus and c1lsc expansion chassis. But a similar one is installed at the Y-end at least. Point is, this ADC card seems to need an external power supply via a 4-pin Molex connector to work properly.
  • We borrowed an adapter card from c1iscey expansion chassis (after first shutting down the machine).
  • It seems like a RED GPIO0 LED on these ADC cards isn't indicative of a fault.
  • Added an ADC part from CDS_PARTS library. Added an ADC selector bus and an "MADC" block that sets up the 64k testpoints as well as the EPICS readbacks.
  • We were able to see sensible numbers (i.e. ~0 since there is no input to the ADC) on these readback channels.
  • To restore everything, we first shutdown c1lsc, then restored the adaptor card back to c1iscey, and then rebooted c1iscey, c1lsc and c1sus. Recompiled c1x04 with the added ADC block removed as it would otherwise complain due to the absence of an adapter board.
  • Did rtcds restart <model> on all machines to bring back all models that were killed. This went smoothly.
  • IMC and Yarm locked smooth.

Note that we have left the working ADC card inside the c1lsc expansion chassis. Plan is to give Rolf the faulty ADC card and at the same time ask him for a working adapter board.


Unrelated to this work: we have also scavenged 4 pcs of v2 of the differential receiving AA board from WB EE shop, along with a 1U chassis for the same. These are under my desk at the 40m for the moment. We will need to re-stuff these with appropriate OpAmps (and also maybe change some Rs and Cs) to make this board the same as v6, which is the version currently in use.

  13662   Wed Feb 28 21:14:34 2018 gautamSummaryPEMChannel admin

Since we decided to use the Acromag for readback of the temperature sensor for Kira's seismometer temperature control, I enabled logging of the channel Johannes had reserved for this purpose last week. Kira has made the physical connection of a temperature sensor to the BNC input for this channel - it reads back -2.92 V right now, which is around what I remember it being when Kira was doing her benchtop tests. I edited C0EDCU.ini to enable logging of this channel at 16 Hz. Presumably, a study of the ADC noise of the Acromag at low frequencies has to be made to ensure appropriate whitening (if any) can be added. Channel name is C1:PEM-SEIS_EX_TEMP_MON. Similarly, there is C1:PEM_SEIS_EX_TEMP_CTRL which is meant to be the control channel for the servoing. Calibration of the temperature sensor readback into temperature units remains. It also remains to be verified if we can have these slow EPICS channels integrated with a fast control model, or if the PID temperature control will be purely custom-script based as we have for the FSS slow loop.

I removed the fast channels I had setup temporarily in c1als. Recompilation and restart of the model went smoothly.

Quote:
 I then made a "PEM" namespace block inside the c1als model, and placed a single CDS filter module inside it (this can be used for calibration purposes). The filter module is named "C1:PEM-SEIS_EX_TEMP", and has the usual CDSfilt channels available. I DQ'ed the output of the filter module (@256 Hz, probably too high, but I'm holding off on a recompile for now). Recompilation and model restart of c1als went smoothly. 
 
  13663   Fri Mar 2 01:45:06 2018 gautamUpdateALSnew look ALS electronics

I spent today making another daughter board (so that we can use the new scheme for I and Q for one arm), testing it (i.e. measuring noise and TF and comparing to LISO model), and arranging all of this inside the 1U demod chassis. To accommodate everything inside, I decided to remove the 2 unused demod units from inside the box. I then drilled a few holes, installed the daughter boards on some standoffs, removed the capacitors and inductors as I outlined yesterday, and routed input and output signals to/from the daughter board. The outputs are routed to a D-sub on the rear panel. More details + better photo + results of testing the combined demod+daughter board signal chain tomorrow...

  13664   Mon Mar 5 10:13:21 2018 gautamUpdateVACvacuum health

In Steve's absence, I've tried to keep an eye on the health of the vacuum system. From Attachment #1, the pressure of the main volume seems stable, no red flags there. I also don't here any anomalously loud sounds near the vacuum pumps. I've changed the N2 cylinders that keep V1 open twice, on Wednesday and Sunday of last week. So in summary, the vacuum system looks fine based on all the metrics I know of.

  13665   Mon Mar 5 11:58:24 2018 gautamUpdateElectronicsThree opamps walked onto an AA board

For testing the new IR ALS noise, we had decided that we would like to use the differential output of the demodulated ALS beat signal, as opposed to a single-ended output, as measurements suggested the former to be a lower noise configuration than the latter. For this purpose, Koji and I acquired a couple of old AA boards from the WB electronics shop. These are however, rev2 of the board, whereas the latest version is v6. The main difference between v2 and v6 is that (i) the THS4131 instrumentation amplifier has the Vocm pin grounded in v6 but is floating in v2 and (ii) the buffer opamps are AD8622 in v6 but are AD8672 in v2. But in fact, the boards we have are stuffed with AD8682

I talked to Rich on Friday, and he seemed to think the AD8672 didn't have any issues noise-wise, the main reason they changed it was because its power consumption was high, and was causing overheating when several of these 1U chassis were packed closely together in an electronics rack. But the AD8682, which is what we have, has comparable power consumption to the AD8622. It is however a JFET opamp, and the voltage noise is a bit higher than the AD8622. 

I am sure there is a way to LISO model a differential output opamp like the THS4131, but I thought I'd simulate the noise in LTSPICE instead. But I couldn't get that to work. So instead, I just measured the transfer function and noise of a single channel, for which Koji had expertly hacked together a custom shorting of the THS4131 Vocm pin to ground. Attachments #1 and #2 show the measurement. All looks good. Note that the phase is 180 at DC because I had hooked up the input signal opposite to what it should have been. The voltage noise of the differential outputs (each measured w.r.t. ground, with both inputs shorted to ground by a short patch cable) at 10 Hz is <100nV/rtHz, and the ADC noise is expected to be ~1uV/rtHz, so I think this is fine.

Conclusion: I think for the ALS test, we can just use the AA board in this config without worrying too much about replacing the buffer stage opamps, even though we've ordered 100pcs of AD8622.


Addendum 7 Mar 2018 11am: As per this document, the output noise of the AA board should be <75nV/rtHz from 10 Hz-50 kHz. So maybe the AD8682 noise is a little high after all. I've gotten the LTSpice model working now, will post the comparison of modelled output noise for various combinations here shortly.

  13666   Mon Mar 5 17:27:34 2018 gautamUpdateALSnew look ALS electronics - characterization

I did a quick test of the noise of the new ALS electronics with the X arm ALS. Attachment #1 shows the results - but something looks off in the measurement, especially the "LO driven, RF terminated" trace. I will have to defer further testing to tomorrow. Of course the real test is to digitize these signals and look at the spectrum of the phase tracker output, but I wanted a voltage noise comparison first. Also, note that I have NOT undone the whitening TFs of (z,p) = (15,150) on these traces. I wonder if these noisy signals (particularly the 10Hz multiple harmonics) are an artefact of measurement, or if something is wonky in the daughter board circuits themselves. I am measuring these with the help of a DB9 breakout board and some pomona minigrabbers. Reagrdless, the sort of ripple seen in the olive green trace for the I channel wasn't present when I did the same test with RF signal generators out on the electronics workbench, so I am inclined to think that this isn't a problem with the circuit. I'm measuring with the SR785 with the "A" input setting, but with the ground set to "Float". I need to look into what the difference is between this mode, and the "A-B" mode. At first glance, both seem to be equivalent differential measurements, but I wonder if there is some subtlety w.r.t. pickup noise.

Perhaps I can repeat the test at the output of the AA board. I looked into whether there is a spare +/- 24V DC power supply available at the LSC rack, to power the 1U AA chassis, but didn't see anything there.

  13667   Wed Mar 7 12:04:14 2018 gautamUpdateElectronicsThree opamps walked onto an AA board

Here are the plots. Comments:

  1. Measurement and model agree quite well yes.
  2. Of the 3 OpAmps, the ones installed seem to be the noisiest (per model)
  3. Despite #2, I don't think it is critical to replace the buffer opamps as we only win by ~10nV/rtHz in the 300-10kHz range.
  4. I don't understand the spec given in T070146. It says the noise everywhere between 10Hz-50kHz should be <75nV/rtHz. But even the model suggests that at 10Hz, the noise is ~250nV/rtHz for any choice of buffer opamp, so that's a factor of 3 difference which seems large. Maybe I made a mistake in the model but the agreement between measurement and model for the AD8682 choice gives me confidence in the simulation. LTSpice files used are in Attachment #3. Could also be an artefact of the way I made the measurement - between an output and ground instead of differentially...

I like LTspice for such modeling - the GUI is nice to have (though I personally think that typing out a nodal file a la LISO is faster), and compared to LISO, I think that the LTspice infrastructure is a bit more versatile in terms of effects that can be modeled. We can also easily download SPICE models for OpAmps from manufacturers and simply add them to the library, rather than manually type out parameters in opamp.lib for LISO. But the version available for Mac is somewhat pared down in terms of the UI, so I had to struggle a bit to find the correct syntax for the various simulation commands. The format of the exported data is also not as amenable to python plotting as LISO output files, but i'm nitpicking...

Quote:

I've gotten the LTSpice model working now, will post the comparison of modelled output noise for various combinations here shortly.

 

  13668   Thu Mar 8 00:40:25 2018 gautamUpdateALSnew look ALS electronics - characterization

I am almost ready for a digital test of the new ALS electronics. Today, Koji and I spent some time tapping new +/-24VDC DIN terminal blocks at the LSC rack to facilitate the installation of the 1U differential receiving AA chassis (separate elog entry). The missing piece of the puzzle now is the timing adapter card. I opted against trying a test tonight as I am having some trouble bringing c1lsc back online.

Incidentally, a repeat of the voltage noise measurement of the X arm ALS beat looked much cleaner today, see Attachment #1 - I don't have a good hypothesis as to why sometimes the signal has several harmonics at 10Hz multiples, and sometimes it looks just as expected. The problem may be more systematically debuggable once the signals are being digitally acquired.

  13669   Thu Mar 8 01:10:22 2018 gautamUpdateGeneralCDS recovery after work at LSC rack

This required multiple hard reboots, but seems like all the RT models are back for now. The only indicator I can't explain is the red DC field on c1oaf. Also, the SUS model seems to be overclocking more frequently than usual, though I can't be sure. The "timing" field of this model's state word is RED, while the other models all seem fine. Not sure what could be going on.

Will debug further tomorrow, when I probably will have to do all this again as I'll need to recompile c1lsc for the ALS electronics test with the new ADC card from the differential AA board.

  13670   Thu Mar 8 14:41:25 2018 gautamUpdateGeneralCDS recovery after work at LSC rack

As I had found before, restarting the c1oaf model fixed the DC error. There is however still a pesky red indicator light on the "ADC0" in c1oaf. Trying to open up the ADC MEDM screen to investigate this further leads to the blank screen on the bottom right of Attachment #1. Probably has something to do with the fact that the model has an ADC block (because every model needs one?) but no signals are actually being piped to the model directly from the ADC.

Another observation, though I don't have any hypothesis as to why this was happening: on the c1sus machine, the c1sus model would frequently overclock, and then eventually, crash. I observed this behaviour at least 3 times between last night and now. The other models seemed fine though, in fact, IMC stayed locked. Why should this have been the case? It remains to be seen if this was somehow connected to the red DC indicator on c1oaf, though why should this be the case? Isn't the DC just concerned with writing data to frames? Any sort of IPC should be independent? Attachment #2 shows that there's been a definite increase in the maximum time on c1sus clock-cycle since yesterday (it's a 10 day minute trend plot of the model clock cycle timing and also the maximum time). Why? Koji and I did switch off all the Sorensens at the LSC rack for about 30mins, but why should this affect anything at 1X6? There are no red lights in either the c1lsc or c1sus expansion chassis. Curiously, the PRM also seems to be glitchy - as I'm sitting in the control room, I see a spot flashing across vertically on the REFL CRT monitor sporadically. Note that nominally, with PRM misaligned, the REFL CRT should be dark. dmesg on c1sus doesn't shed any light on the issue.

Seems like some high level voodoo indecision.


Edit 330pm: The model just crashed again. dmesg rather unhelpfully just says "ADC timeout". Unclear how to debug further. See Attachment #3.

Quote:

This required multiple hard reboots, but seems like all the RT models are back for now. The only indicator I can't explain is the red DC field on c1oaf. Also, the SUS model seems to be overclocking more frequently than usual, though I can't be sure. The "timing" field of this model's state word is RED, while the other models all seem fine. Not sure what could be going on.

Will debug further tomorrow, when I probably will have to do all this again as I'll need to recompile c1lsc for the ALS electronics test with the new ADC card from the differential AA board.

  13671   Thu Mar 8 15:23:16 2018 gautamUpdateElectronicsNew DC power ports at c1lsc

[Koji, Gautam]

Yesterday, we installed some new DIN rail connectors at the LSC rack to provide 3 new outputs each for +24V DC and -24V DC. The main motivation was to facilitate the installation and powering of the differential receiving AA board. The regulators used inside the 1U chassis actually claims a dropout voltage of 0.5V and outputs 14V nominally, so a +/-15V DC supply would've perhaps been sufficient, but we decided to leave a bit more margin, and unfortunately, there are no +/-18V DC KEPCO linear power supplies to the LSC rack. Procedure:

  1. Prepared a bunch of DIN rail connectors with tinned, daisy-chained wires in the office area. Checked continuity and isolation with DMM.
  2. Checked that the two Sorensens at the bottom of the LSC rack were powering the RF distribution box and nothing else at the LSC rack.
  3. Walked over to the little rack housing all the KEPCO DC power supplies that supply DC voltages to the LSC rack. After checking that the labelled voltage and current values were correct, we turned them off, first +/-5V, then +/-15V (2 sets), and finally +/-24V.
  4. Installed the pre-assembled DIN connectors on the side rail at the LSC rack (we had to remove the side panel for the rack to do this work).
    • We used the ports supplying power to the ALS 1U demod chassis (+/-24V DC) to tap these voltages to our newly installed connectors.
    • The interconnecting wires are rather thick gauge, and especially for the ground wire, we found it impossible to push in our tap-off wire into the "correct/hot" side of the DIN blocks. So we had to use the other side instead. I'll upload a picture shortly which will make this more clear.
    • Checked continuity and isolation with DMM.
    • Turned the KEPCOs back on in reverse order to how they were turned off.
    • Measured voltages on the hot side of the DIN blocks, confirmed that they were as expected.
  5. Prepared a 12AWG aLIGO style power cable to connect to the 1U chassis. A reel of this cabling, with yellow shielding, is located ~halfway along under the EW arm. Koji prepared the actual connector and housed it in a DSUB shell as per aLIGO wiring color scheme.
  6. Installed the power cabling to one set of our 3 newly installed +/-24V DC power supplies.
  7. Inserted fuses into the hot DIN blocks, measured voltage at connector end of our newly installed power cable. At first, I forgot to check if the fuse blocks had fuses inside, but after this was rectified, voltages were as expected yes.

The c1lsc frontend models crashed for some reason during this procedure. Now the c1sus frontend model is also behaving weirdly. It is unclear to me if/how this work would have led to these problems, but the temporal correlation (but not causation?) is undeniable.

  13672   Thu Mar 8 18:15:42 2018 gautamUpdateGeneralCDS recovery after work at LSC rack

I was forced into a simultaneous power-cycle rebooting of the three vertex FEs just now. I took the opportunity to completely disconnect the c1sus expansion chassis from all power and then restart it.

Everything is back up right now, and the weird timing issues I noticed in the sus model seem to be gone now (I'll need a longer baseline to be sure and I'll post a trend of the CPU timing tomorrow). It's disconcerting that apparently the only way to get everything back up and running is the nuclear option of power-cycling all FE related electronics. I was considering borrowing an ADC adapter card from the Y end and measuring the calibrated IR ALS noise with the digital system, but if I'm going to have to go through this whole dance each time I do a model recompile on c1lsc (which I'm going to have to in order to get the extra ADC recognized), I'm wondering if it's just better to wait till we get the new adapter cards we ordered. I think I'm going to work on tuning the input coupling into the fiber at EX in the next couple of days instead.

Quote:
 

Seems like some high level voodoo indecision.


Edit 330pm: The model just crashed again. dmesg rather unhelpfully just says "ADC timeout". Unclear how to debug further. See Attachment #3.

 

  13673   Thu Mar 8 19:38:37 2018 gautamUpdateALSdigital unwhitening of daughter board

I made a LISO fit of the measured TF of the daughter board, so that I can digitally invert the daughter board whitening. Results attached. (Inverse) Filters have been uploaded to the ALS X Foton filter banks.

  13674   Thu Mar 8 23:50:27 2018 gautamUpdateALSFirst look at new ALS electronics
  • Locked single arms, dither aligned, and saved offsets to EPICS (slow) sliders in anticipation of having to reboot all vertex FEs.
  • Shutdown ETMY watchdog, stopped all models on c1iscey, and shutdown that frontend.
  • Walked down to Y-end, powered of c1iscey expansion chassis, and removed the ADC adaptor card.
  • Stopped all models on c1lsc. Shutdown watchdog on all optics in anticipation of c1sus model failing. Shutdown the c1lsc frontend.
  • Powered off the c1lsc expansion chassis. Installed the borrowed adapter card from c1iscey in c1lsc expansion chassis. Connected it to the "spare" ADC card Koji and I had installed in c1lsc expansion chassis last Wednesday.
  • Connected differential output of demod board to differential input of AA chassis. Connected SCSI connector from output of AA chassis to the newly installed adapter card.
  • Powered the c1lsc expansion chassis back on. Then powered c1lsc FE on.
  • Walking back out to the control room, I saw that all vertex FEs had crashed. I had to go back in and hard-reboot c1sus.
  • Before bringing back any models, I backed up the existing c1lsc model, and then modified c1x04 and c1lsc to use the newly acquired ALS signals for the X arm ALS signal chain.
  • Restarted all vertex FE models. Everything came back up smooth. DC light is still red on c1oaf but I didn't bother trying to rectify it tonight for these tests.
  • Reset appropriate LSC offsets with PSL shutter closed. Locked X arm on IR. Reset phase tracker servo gain for X arm ALS. Engaged slow temperature servo on EX laser.

Then I looked at  the spectrum, see Attachment #1. Disappointingly, it looks like the arm PDH servo is dominating the noise, and NOT unsuppressed EX laser frequency noise,. Not sure why this is so, and I'm feeling too tired to debug this tonight. But encouragingly, the performance of the new ALS signal chain looks very promising. Once I tune up the X arm loop, I'm confident that the ALS noise will be at least as good as the reference trace.

I am leaving c1iscey shutdown until this is fixed. So ETMY is not available for the moment.

Random factoid: Trying to print a DTT trace with LaTeX in the label text on pianosa causes the DTT window to completely crash - so if you dont save the .xml file, you lose your measurement.

Quote:

I made a LISO fit of the measured TF of the daughter board, so that I can digitally invert the daughter board whitening. Results attached. (Inverse) Filters have been uploaded to the ALS X Foton filter banks.

 

  13675   Fri Mar 9 01:07:01 2018 gautamUpdateALSFirst look at new ALS electronics

[koji, gautam]

I was going to head out but then it occurred to me that I could do another simple test, which is to try and lock the X arm on ALS error signal (i.e. actuate on MC length to keep the beat between EX laser and PSL fixed, while the EX frequency is following the Xarm length). Comparing the in loop (i.e. ALS) error signal with the out-of-loop sensor (i.e. POX), it seems like POX is noisy. The curves were lined up by eye, by scaling the blue curve to match the red at the ~16Hz peaks. This supports my hypothesis in the previous elog. On the downside, could be anything. Electronics in the POX chain? The demod unit itself? Will look into it more tomorrow..

As an aside, controlling the arm with ALS error signal worked quite well, and the lock was maintained for ~1 hour.

  13676   Fri Mar 9 12:59:53 2018 KiraUpdatePEMADC noise measurement

[Kira, Gautam]

I ceated a simple circuit that takes in 15V and outputs precisely 5V by using a 12V voltage regulator LM7812 and an AD586 that takes the output of the voltage regulator and outputs 5V (attachment 1). We plugged this into the slow channel and will leave it running for a few hours to see if we still have the fluctuations we observed earlier and also fit the noise curve. We'll also test the fast channel later as well. Attachment 2 shows the setup we have in the lab, with the red and white cable plugged into the +15V power supply and the red and black cable connected to the slow channel.

  13677   Fri Mar 9 20:35:41 2018 Udit KhandelwalSummaryGeneralSummary 2018/03/09

1. Optical Table Layout 

I had discussed with Koji a way to record coordinates of optical table equipments in a text file, and load to solidworks. The goal is to make it easier to move things around on the table in the CAD. While I have succeeded in importing coordinates through txt files, there is still a lot of tediousness in converting these points into sketches. Furthermore, the task has to be redone everytime a coordinate is added to or changed in the txt file. Koji and I think that this can all be automated through solidworks macros, so I will explore that option for the next two weeks.

2. Vacuum Chamber CADs 

Steve will help find manufacturing drawings of the BS chamber. I have completed the ETM chambers, while the ITM ones are identical to them so I will reuse parts for the CAD. 

  13678   Mon Mar 12 13:58:37 2018 gautamUpdateGeneralprojector light bulb blown

Bulb went out ~10am today. Looks like the lifetime of this bulb was <100 days.

Steve: bulb is arriving next week

Quote:

Bulb  is replaced.

  13679   Mon Mar 12 22:08:31 2018 gautamUpdateALSNoisy POX

[kevin, gautam]

we tested my noisy POX hypothesis tonight. By locking the single arm with POX, the arm length is forced to follow PSL frequency, which is itself slaved to IMC length. From Attachment #1, there is no coherence between the arm control signal and MC_F. This suggests to me that the excess noise I am seeing in the arm control signal above 30 Hz is not originating from the PSL. It also seems unlikely that at >30Hz, anything mechanical is to blame. So I am sticking with the hypothesis that something is wonky with POX. For reference, a known "normal" arm control signal spectrum looks like the red curve in this elog.

 

  13680   Mon Mar 12 23:57:31 2018 gautamUpdateALSNoisy POX

[kevin, gautam]

Kevin suggested I shouldn't be so lazy and test the POY spectrum as well. So we moved the timing card back to c1iscey, went through the usual dance of vertex machine reboots, and then got both single arm locks going. Attached spectrum shows that both POX and POY are noisy. I'm not sure what has changed that could cause this effect. The fact that both POX and POY appear uniformly bad, but that there is no coherence with MC_F, suggests to me that perhaps this has something to do with the work I did with Koji w.r.t. the power situation at the LSC rack. But we just checked that

  1. All the demod board front panel LED indicators are green.
  2. Marconi and all RF amplifier boxes are on (but we didn't actually measure any RF power levels yet tonight).
  3. We checked the KEPCO power supplies in the little cabinet along the Yarm, and all of them are reporting the correct voltages/currents as per Steve's (recently updated) labels.
  4. Checked the expansion chassis at the LSC rack for any red lights, there were none.

Another observation we made: note the huge bump around 70Hz in both arm control signals. We don't know what the cause of this is. But we occassionally noticed harmonics of this (i.e. 140, 210 Hz etc) appear in the control signal spectra, and they would grow with time - eventually, the X arm would lose lock (though the Y arm stayed locked).

I'm short on ideas for now so we will continue debugging tomorrow.


Unrelated to this work: Kevin reminded me that the high-pitched whine from the CRT TVs in the control room (which is apparently due to the flyback transformer) is DEAFENING. It's curious that the "chirp" to the eventual 15kHz whine is in opposite directions for the QUAD CRTs and the single display ones. Should be a Ph6 experiment maybe.


Update 2:30pm Mar 13: The furthest back I seem to be able to go in time with Frames is ~Jan 20 2018. Looking for a time when the arms were locked from back then, it seems like whatever is responsible for a noisy POX and POY was already a problem back in January. See Attachment #2. So it appears that the recent work at 1Y2 is not to blame...

  13681   Tue Mar 13 20:03:16 2018 johannesConfigurationComputersc1auxex replacement

I assembled the rack-mount server that will long-term replace c1auxex, so we can return the borrowed unit to Larry.

SUPERMICRO SYS-5017A-EP Specs:

  • Intel Atom N2800 (2 cores, 1.8GHz, 1MB, 64-bit)
  • 4GB (2x2GB) DDR3 RAM
  • 128 GB SSD

IMG_20180313_105154890.jpg      IMG_20180313_133031002.jpg

I installed a standard Debian Jessie distribution, with option LXDE for minimal resource usage. Steps taken after fresh install

  1. Give controls sudo permission: usermod -aG sudo controls
  2. mkdir /cvs/cds
  3. apt-get install nfs-common
  4. Added line "chiara:/home/cds              /cvs/cds        nfs     rw,bg,nfsvers=3" to end of /etc/fstab
  5. Configured network adapter in /etc/network/interfaces
            iface eth0 inet static
            address 192.168.113.48
            netmask 255.255.255.0
            gateway 192.168.113.2
            dns-nameservers 192.168.113.104 131.215.125.1 131.215.139.100
            dns-search martian

    I first assigned the IP 192.168.113.59 of the original c1auxex, but for some reason my ssh connections kept failing mid-session. After I switched to a different IP the disruption no longer happened.
  6. Add lines "search martian" and "nameserver 192.168.113.104" to /etc/resolv.conf
  7. apt-get install openssh-server
    At this point the unit was ready for remote connections on the martian network, and I moved it to the XEND.
  8. Added lines to /home/controls/.bashrc to set paths and environment variables:
    export PATH=/cvs/cds/rtapps/epics-3.14.12.2_long/base/bin/linux-x86_64:/cvs/cds/rtapps/epics-3.14.12.2_long/extensions/bin/linux-x86_64:$PATH
    export HOST_ARCH=linux-x86_64
    export EPICS_HOST_ARCH=linux-x86_64
    export RPN_DEFNS=~/.defns.rpn
    export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/cvs/cds/rtapps/epics-3.14.12.2_long/base/lib/linux-x86_64:/cvs/cds/rtapps/epics-3.14.12.2_long/modules/modbus/lib/linux-x86_64/:/cvs/cds/rtapps/epics-3.14.12.2_long/modules/asyn/lib/linux-x86_64
  9. apt-get install libmotif-common libmotif4 libxp6 (required to run burtwb utility)

The server is ready to take over for c1auxex2 and does not need any local epics compiled, since it can run the 3.14.12.2_long binaries in /cvs/cds.

  13682   Wed Mar 14 23:58:30 2018 johannesConfigurationComputersc1auxex replacement

I replaced the borrowed server with the permanent one today. Before Removing the current server, Before, I performed several additional preparations:

  • Updated Chiara hostables to IP 192.168.113.48 for c1auxex
  • apt-get install procserv
  • copied ETMXaux2.* files in /cvs/cds/caltech/target/c1auxex2 to ETMXaux.* and changed references from /opt/rtcds/epics (which was a local directory on c1auxex2) to /cvs/cds/rtapps/epics-3.14.12.2_long in the copied files
  • Added instruction
    Environment="LD_LIBRARY_PATH=/cvs/cds/rtapps/epics-3.14.12.2_long/base/lib/linux-x86_64:/cvs/cds/rtapps/epics-3.14.12.2_long/modules/modbus/lib/linux-x86_64/:/cvs/cds/rtapps/epics-3.14.12.2_long/modules/asyn/lib/linux-x86_64"
    to /etc/systemd/system/modbusIOC.service  (required for burtwb dependencies)

Then I replaced the server:

  1. IFO was in LSC mode with both arms locked
  2. Backed up ETMX alignment using save feature in IFOalign screen
  3. Disengaged LSC mode
  4. Shut down ETMX watchdog
  5. Disconnected ETMX satellite box
  6. Shut down c1auxex2 and c1auxex
  7. Performed the server swap
  8. Booted c1auxex
  9. Made sure EPICS channels were back online and channel defaults were restored
  10. Reconnected satellite box
  11. Turned on watchdog
  12. Turned on OpLevs
  13. Engaged LSC mode -> both arms were instantly locked

I returned c1auxex2 to Larry, who needed it back asap because of some hardware failure

Steve: Acromag XT1221 ordered 3-15-18

  13683   Thu Mar 15 16:00:25 2018 Larry WallaceSummaryComputersCert renewal for NODUS

The cert for nodus has been renewed for another 2 years.

The following is the basic procedure for getting a new cert: (Note certs are only good for two years as of 2018)
openssl req -sha256 -nodes -newkey rsa:2048 -keyout nodus.ligo.caltech.edu.key -out nodus.ligo.caltech.edu.csr
Country Name (2 letter code) [AU]:US
State or Province Name (full name) [Some-State]:CaliforniaLocality Name (eg, city) []:Pasadena
Organization Name (eg, company) [Internet Widgits Pty Ltd]:California Institute of Technology
Organizational Unit Name (eg, section) []:LIGO
Common Name (eg, YOUR name) []:nodus.ligo.caltech.edu

Leave the e-mail address, challenge password and optional company name blank. A new private key will be generated.
chown root nodus.ligo.caltech.edu.key
chgrp root nodus.ligo.caltech.edu.key
chmod 0600 nodus.ligo.caltech.edu.key

The nodus.ligo.caltech.edu.csr file is what is sent in for the cert.
This file should be sent to either ryan@ligo.caltech.edu or security@caltech.edu and copy wallace_l@ligo.caltech.edu.

A URL llink with the new cert to be downloaded will be sent to the requestor.

Once the files are downloaded, the new cert and intermediate cert, they can be copied and renamed.

The PEM-encoded host certificate by itself is saved at:

  /etc/httpd/ssl/nodus.ligo.caltech.edu.crt

The nodus.ligo.caltech.edu.key file should be in the same directory or whichever directory is indicated in the ssl.conf located in /etc/httpd/conf.d/  directory.

httpd will need to be restarted in order for it to see the new cert.

 

  13684   Thu Mar 15 17:33:56 2018 KiraUpdatePEMtest setup

I have attached the setup I completed today. The metal box contains the heater circuit and the board for the temperature sensor is right above it. This is basically the same setup as before, but I've just packaged everything up neater. I expect to be able to perform the test tomorrow and begin implementing PID control. I still need a DAC input for the heater circuit and the temperature sensor is having some issues as well.

  13685   Fri Mar 16 09:36:56 2018 SteveUpdateVACRGA scan at day 511,218d

Pumpdown 80 at 511 days and pd80b at 218 days

Valve configuration:  special vacuum normal, annuloses are not pumped at 3 Torr, IFO pressure 7.4e-6 Torr at vac envelope temp 22 +- 1C degrees

Quote:

pd80b rga scan at 175 day.  IFO pressure 7.3e-6 Torr-it

Condition: vacuum normal, annuloses not pumped. Rga turned on yesterday.

The rga was not on since last poweroutage Jan 2, 2018 It is warming up and outgassing Atm2

 

  13686   Mon Mar 19 07:37:00 2018 Angelina PanSummary Proposed QPD Optical Arrangement

I am currently working on an optical arrangement consisting of a QPD that measures the fluctuations of an incoming HeNe laser beam that is reflected by a mirror. The goal is to add a second QPD to the optical arrangement to form a linear combination that effectively cancels out the (angular) fluctuations from the laser beam itself so that we can only focus on the fluctuations produced by the mirror.

In order to solve this problem, I have written a program for calculating the different contributions of the fluctuations of the HeNe laser and fluctuations from the mirror, for each QPD (program script attached). The goal of the program is to find the optimal combination of L0, L1, L2, and f2 that cancels the fluctuations from the laser beam (while retaining  solely the fluctuations from the mirror) when adding the fluctuations of QPD 1 and QPD 2 together. 

By running this program for different combinations of distances and focal lengths, I have found that the following values should work to cancel out the effects of the oscillations from the HeNe laser beam (assuming a focal length of 0.2 m for the lens in front of the original QPD):

  • L0 = 1.0000 m (distance from laser tube to mirror)
  • L1 = 0.8510 m (distance from mirror to lens in front of QPD 1)
  • L2 = 0.9319 m (distance from beamsplitter to lens in front of QPD 2)
  • f2 = 0.3011 m (focal length of lens in front of QPD 2)

Based on these calculations, I propose to try the following lens for QPD 2:

1’’ UV Fused Silica Plano-Convex Lens, AR-Coated: 350 - 700 nm (focal length 0.3011 m). https://www.thorlabs.com/newgrouppage9.cfm?objectgroup_id=6508

  13687   Mon Mar 19 14:39:09 2018 johannesConfigurationComputersc1auxex replacement

[gautam, johannes]

The temperature control output channel for the XEND seismometer wasn't working properly. The EPICS channel existed, could be written to and read from, but no physical voltage was observed on the (confirmed properly) wired connector.

The Acromag DAC that outputs this channel was completely spare in the original scheme and does not serve any other channels at the moment. We found it to be unresponsive to ping from the host machine (reminder: the Acromags are on their own subnet with IPs 192.168.114.xxx connected to the secondary ethernet adapter of c1auxex), while all others returned the ping just fine. The modules have daisy-chained ethernet connections, and the one Acromag unit behind the unresponsive one in the chain was still responding to ping and its channels were working, so it couldn't have been a problem with the (ethernet) cabling.

Gautam and I power-cycled the chassis and server, which resolved the issue. The channel is now outputting the requested voltage on the Out1 BNC connector of the chassis (front). When I was setting up the whole system and did frequent rebooting and IP-redefinitions I have seen network issues arise between server and Acromags. In particular, when changing the network settings server-side, the Acromags needed to reboot occasionally. So this whole problem was probably due to the recent server-swap, as the chassis had not been power-cycled since.

 

During the debugging we also found that the c1psl2 channels were not working. This was because I had overlooked to update the epics environment variables for the modbus path defined in /cvs/cds/caltech/target/c1psl2/npro_config.cmd from the local installation /opt/epics/ (which doesn't exist on the new server anymore) to the network location /cvs/cds/rtapps/epics-3.14.12.2_long/. This has been fixed and the slow diagnostic PSL channels are recording again.

  13688   Mon Mar 19 15:02:29 2018 gautamUpdateALSNoisy MC sensing

The working hypothesis, since the excess noise in single arm locks is coherent between both arms, the excess sensing noise is frequency noise in the IMC locking loop (sensing because it doesn't show up in MC_F). I've started investigating the IMC sensing chain, starting with the power levels of the RF modulation source. Recall that we had changed the way the 29.5MHz signal was sent to the EOM and demod electronics in 2017. With the handheld RF power meter, I measured 13.2dBm coming out of the RF distribution box (this is routed straight from the Wenzel oscillator). This is amplified to 26dBm by an RF amplifier (ZHL-2-S) and sent to the EOM, with a coupled 16dBm part sent to a splitter that supplies the LO signal to the demod board and also the WFS boards. Lydia made a summary of expected RF power levels here, and I too seem to have labelled the "nominal" LO level to the MC_REFL demod board as +5dBm. But I measured 2.7dBm with the RF power meter. But looking closely at the schematic of the splitting circuitry, I think for a (measured) 16.7dBm input to it, we should in fact expect around 3dBm of output signal. So I don't know why I labelled the "nominal" signal level as 5dBm.

Bottom line: we are driving a level 17 mixer with more like +14dBm (a number inferred from this marked up schematic) of LO, which while isn't great, is unlikely to explain the excess noise I think (the conversion loss just degrades by ~1dB). So I will proceed to check further downstream in the signal chain.

  13689   Mon Mar 19 23:44:00 2018 gautamUpdateIOOIMC loop checkup

[koji, gautam]

  1. I began my investigations by measuring the voltage noise of the demod board outputs with an SR560 (G=100) and SR785 in the audio band.
    • Measurement made with PSL shutter closed, LO input of demod board driven with the nominal level of ~2.5dBm, RF input terminated.
    • Motivation was to look for any noise features.
    • Expected noise level is ~2nV/rtHz (Johnson noise of 50ohm) since there are no preamp electronics post SCLF-5 LP filter on this board.
    • Attachment #1 shows the results of the measurement for a few scenarios. Spectra only shown for the I channel but the Q channel was similar. The LO=+5dBm curve corresponds to driving the input at 5dBm with a marconi, to see if the label of the nominal level being +5dBm had anything to it.
    • The arches above 1kHz seemed suspicious to me, so I decided to investigate further.
  2. Looking at the IMC Demod board schematic, I I saw that there were 2 ERA-5SMs in there which are responsible for amplifying the 29.5MHz signal which serves as the LO to the oscillators.
  3. I pulled the demod board out and tested it on the electronics workbench. Koji and I couldn't make sense of the numbers we were seeing (all measurements made with Agilent analyzer and active FET probe with 100:1 attentuator).
  4. We eventually concluded that the ERA-5SMs were not exhibiting the expected gain of ~20dB. So we decided to swap these out.
  5. This sort of measurement is not ironclad as the output of the ERA-5SM goes to the mixer whose input impedance is dynamically varying as the diodes are switching. So even after replacing the suspect amplifiers with new ones, we couldn't make the numbers jive.
  6. We suspected that the new amplifiers were getting saturated. The 3dB saturation point for the ERA-5SM is spec'ed as ~19dBm.
    • We "measured" this by varying the input signal level and looking for deviation from linearity.
    • We saw that there was ~1dB compression for ~13dBm output from the ERA-5SM (after correcting for all attenuators etc). But this number may not be accurate in the absolute sense because of the unknown input impedance of the mixer.
    • Moreover, looking at the spec sheet for the mixer, JMS-1H, we found that while it wasn't ideal to operate the mixer with the LO level a few dBm below the expected +17dBm, it probably wasn't a show stopper.
  7. So we figured that we need 10dB of attenuation between the "nominal" LO input level of 2.7dBm and the input of the demod board in order to keep the ERA-5SM in the linear range. This has now been implemented in the form of an SMA attenuator.
  8. IMC locked straight away. But I noticed that PC drive RMS level was unusually large.
  9. I found that by increasing the "IN1" gain of the CM board to 12dB (from 2dB) and the "VCO gain" to 10dB (from 7dB), I could recover a transfer function with UGF ~140kHz and PM ~30degrees (need more systematic and wider span measurements of this, and also probably need to optimize the crossover gains). See Attachment #2 for my quick measurement tonight.
  10. Updated mcup to reflect these new gains. Tested autolocker a few times, seems to work okay.
  11. While it presumably was a good thing to replace the faulty amplifiers and prevent them from saturating, this work has not solved the primary problem of excess frequency noise on the PSL.

It is not clear to me why installing an attenuator to prevent amplifier saturation has necessitated a 10dB increase in the IN1 gain and 3dB increase in the VCO gain. Initially, I was trying to compensate for the gain by increasing the FSS "Common Gain" but in that setting, I found an OLTF measurement impossible. The moment I enabled the excitation input to the CM board, the lock was blown, even with excitation amplitudes as small as -60dBm (from the Agilent network analyzer).

This may also be a good opportunity to test out one of the aLIGO style FET mixer demod boards (recall we have 2 spare from the 4 that were inside the ALS demod box). I'm going to ask Steve to package these into a 1U chassis so that I can try that setup out sometime. From a noise point of view, the aLIGO boards have the advantage of having a x100 preamp stage straight after the mixer+LPF. We may need to replace the lowpass filter though, I'm not sure if the one installed is 1.9MHz or 5MHz.

I've left an SR785 and AG4395 near 1X2 in anticipation of continuing this work tomorrow.

Unrelated to this work - seems like the WFS DC and RF offsets had not been set in a while so I reset these yesterday. The frequent model restarts in recent times may mean that we have to reset these to avoid using dated offset values.

  13690   Tue Mar 20 16:53:03 2018 gautamUpdateIOOIMC loop checkup

Re-measured the demod board noises after replacing the suspect ERA-5SMs, with LO driven by a marconi at the "nominal" level of 2.5dBm, and RF input terminated. Attachment #1 is the input referred voltage noise spectra. I used the FET low noise pre-amp box for this purpose. I cannot explain the shape of the spectra above 1kHz. I tried doing the measurement on a minicircuits mixer (non-surface mount) and found the shape to be flat throughout the SR785 span. Unclear what else could be going on in the demod board though, all the other components on it are passive (except the ERA-5SMs which were replaced). I considered adopting a PMC style demod setup where we do the demod using some separate Minicircuits Mixer+LowPass filter combo. But the RF flashes for the IMC monitored at the RFmon port are ~0.2Vpp, and so the RF input to the mixer is expected to be ~2Vpp. The minicircuits mixer selection guide recommends choosing a diode mixer with LO level at least 10dBm above the expected RF input signal level, and we don't have any standalone mixers that are >Level 7. I've asked Steve to package the aLIGO demod board in the meantime, but even that might not be a plug and play replacement as the IF preamp stage has ~120degrees phase lag at 1MHz, which is significantly higher than the existing board which just has a SCLF5 low pass filter after the mixer and hence has <45degrees phase lag at 1MHz.

  13691   Tue Mar 20 16:56:01 2018 KiraUpdatePEMtest setup

The MOSFET was getting pretty hot, so I switched it out to a larger heat sink and it's fine now. I then used a function generator in place of the DAC to provide ~3.5V. I got the current in the circuit to 1.7A, which is as expected, since we have 24V input, the heater resistance is 12.5ohm and the resistor we are using is 1ohm, so 24V/(12.5+1)ohm = 1.7A. The temperature inside the can rose about 5 degrees in half an hour. The only issue now is the voltage regulators and OP amp inside the box get hot, though it doesn't seem to be dangerous. I switched the function generator input to a DAC and Gautam set it to 1.5V. If it works, then we'll leave this on overnight and work on the PID control tomorrow. I've attached images of the current heater circuit box when it is open and the new heat sink for the MOSFET.


gautam: we also tried incorporating the EPICS channels from the Acromag into the RTCDS so that we can implement PID control by using Foton. I tried doing this using the "EpicsIn" and "EpicsOut" blocks from CDS_PARTS. While the model recompiled smoothly, I saw no signals in the filter module i had connected in series with the EpicsIn block. So I just reverted c1pem to its original state and recompiled the model. Guess we will stick to python script PID reading EPICS channels to implement the PID servo.

  13692   Tue Mar 20 19:48:10 2018 gautamUpdatePEMtest setup

according to the temp sensor readout, which was ~-3.35V which corresponds to ~335K, the temperature of the can is now 60 deg C. This is a bit warm for my liking so i'm turning the heater current down to 0 now by writing 0 to C1:PEM-SEIS_EX_TEMP_CTRL

  13693   Tue Mar 20 21:08:03 2018 gautamUpdateIOOIMC loop checkup

This elog by koji inspired me to consider power supply as a possible issue.

The demod board receives +/-24V DC (which is regulated down to +/-15V DC by 7815/7915), and also +15V DC via the backplane. The ERA-5SM receives DC power from the latter (unregulated) +15V DC. I can't think of why this is the case except perhaps the regulators can't source the current the amp wants? In any case, it doesn't look feasible to change this by cutting any traces on the PCB to me. While I had the board out, I decided to replace the JMS-1H mixers in a last ditch effort to improve the demod board noise. Unfortunately I'm having trouble de-soldering these MCL components from the board. So for now, I'm leaving the demod board out, IMC unlocked. Work will continue tomorrow. 

  13694   Tue Mar 20 22:44:45 2018 gautamUpdateIOOIMC loop checkup

After some persistence, I managed to get the mixers off.

  • Having gotten the mxiers off, I decided to temporarily solder on 50ohms between the LO pin pad and ground on the demod board and measure the RF signal levels in the LO chain with the active probe again.
  • Today, with this change, I confirmed that the ERA-5SM begins to saturate closer to the +19dBm advertised on its datasheet. So we need only 2dB of attenuation at the input to have 17dBm at the LO pin of the mixer, assuming 50ohm input impedance.
  • But this begs the question - what does minicircuits mean by a Level-YY mixer? Do they expect YY dBm delivered to a 50ohm load? Or do we need to supply YY dBm accounting for the dynamically changing input impedance of the mixer, as monitored by a high impedance probe?
  • I soldered on some new mixers (JMS-1H) I procured from Downs earlier today.
  • Re-installed the demod board in the eurocrate.

Unfortunately, the coherent noise between the arms persists so the sensing noise injection must be happening elsewhere. frownIMC seems to lock fine though so I'm leving the autolocker on

  13695   Wed Mar 21 10:00:35 2018 steveUpdateGeneralprojector light bulb replaced

Light bulb replaced.

Quote:

Bulb went out ~10am today. Looks like the lifetime of this bulb was <100 days.

Steve: bulb is arriving next week

 

  13696   Wed Mar 21 15:52:45 2018 gautamUpdateIOOMC error point calibration

As discussed at the meeting, I decided to calibrate the MC error point into physical units of Hz/rtHz (a.k.a. the PDH discriminant). This is to facilitate the debugging of the hypothesized excess IMC sensing noise. I did this as follows.

  1. Trust the POX calibration that was last updated in Aug 2017.
  2. Hook up spare DAC channel (piped from LSC rack to 1X2) to IN2 of IMC CM board.
  3. Inject excitation into MC error point via "IN2" input of the common board. For an excitation of 30cts with the IN2 gain at -32dB, I was able to see a peak in the calibrated X arm control signal that was ~x10 above the nominal noise level around 150Hz without seeing any nonlinear coupling effects in the DTT spectrum (I'm assuming 150Hz is sufficiently above the UGF of the X arm locking loop such that no loop correction is necessary).
  4. Took a spectrum of the IMC error signal, teed off into the SR785 at the I output of the demod board with the same linewidth as the DTT spectrum.
  5. Confirmed that without any excitation,
  6. Did the math to make these two peaks line up. The resulting calibration is: 13kHz/Vrms.

Math details:

  • DTT peak height @ 150 Hz with Hanning window, 25 avgs = 1.97e-4 nm/rtHz (See Attachment #1).
  • X arm cavity length = 37.79m, using which the above number becomes 1.47 Hz/rtHz.
  • Peak height in SR785 spectrum with Hanning window, 25 avgs = 1.13e-4 Vrms/rtHz (See Attachment #2).
  • Dividing, we get 13kHz/Vrms.

Using this, I can now make up a noise budget of sorts for the IMC sensing.


gautam 20180327 4.30pm: I re-checked the PDH error signal calibration using the oscilloscope method. Attachment #3 shows the PDH I and Q error signals and also the output of the RF monitor port, during a TEM00 flash. This attachment should be compared to Attachment #2 of elog 12822, and the answer lines up quite well. From my Finesse model of the IMC, I calculated that the x-axis of the PDH horn-to-horn is ~12.3kHz. Comparing to the top row of Attachment #3, I get a PDH error signal calibration of ~12.4kHz/Vrms, which lines up well with the number quoted above. So I trust my calibration, and hence, the y-axis of my noise budgets in reply to this elog.

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