40m QIL Cryo_Lab CTN SUS_Lab TCS_Lab OMC_Lab CRIME_Lab FEA ENG_Labs OptContFac Mariner WBEEShop
  40m Log, Page 256 of 339  Not logged in ELOG logo
ID Date Author Type Category Subject
  4219   Fri Jan 28 11:08:44 2011 josephbUpdateGreen Lockingno transmission of ALS signals

As you've correctly noted, the source of the C1:GCV-SCX_ETMX_ALS channels is in the c1gcv model. The first 3 letters of the channel name indicate this (GCV).

The destination of this channel is c1scx, the 2nd 3 letters indicate this (SCX). If it passed through the c1rfm model, it would be written like C1:GCV-RFM_ETMX_ALS.

This particular channel doesn't pass through the c1rfm model, because the computers these two run on (c1ioo and c1scx) are directly connected via our old VMIC 5565 RFM cards, and don't need to pass through the c1sus computer. This is in contrast to all communications going to or from the c1lsc machine, since that is only connected the c1sus machine by the Dolphin RFM. The c1rfm also handles a bunch of RFM reads from the mode cleaner WFS, since each eats up 3-4 microseconds and I didn't want to slow the c1mcs model by 24 microseconds (and ~50 microseconds before the c1sus/c1scx computer switch).

So basically c1rfm is only used for LSC communications and for some RFM reads for local suspensions on c1sus.

As for the reason we have no transmission, that looks to be a problem on c1ioo's end. I'm also noticing that MCL is not updating on the MC2 suspension screen as well as no changes to MC PIT and YAW channels, which suggests we're not transmitting properly.

I rebooted the c1ioo machine and then did a burt restore of the c1ioo and c1gcv models. These are now up and running, and I'm seeing both MCL and ALS data being transmitted now.

Its possible that when we were working on the c1gfd (green frequency divider model) on c1ioo machine we disturbed the RFM communication somehow. Although what exactly, I'm not sure.

Quote:

No signal is transmitted from C1:GCV-SCX_ETMX_ALS (on c1gcv) to C1:GCV-SCX_ETMX_ALS (on c1scx)

I can't find RFM definition for ALS channels in c1rfm. Where are they???

 

  4218   Fri Jan 28 10:27:46 2011 Aidan, JoeSummaryGreen LockingDigital Frequency Discriminator - calibration

 One more thing ... we can calibrate the output of the LP filter to give a result in Hz with the following calibration:

LP_OUT = -1/(2*dt)*(LP_IN -1), where dt is 1/16384, the delay time of the delayed path.

Therefore LP_OUT = -8192*(LP_IN-1).

  4217   Fri Jan 28 09:03:38 2011 AidanSummaryGreen LockingDigital Frequency Discriminator

Quote:

That's some pretty fast work! I thought we would be taking up to a week to get that happening. I wonder what's the right way to measure the inherent frequency noise of this thing?

Also, should the comparator part have some hysteresis (ala Schmidt trigger) or is it best to just let it twirl as is? Is it sensitive to DC offsets on the input or is there a high pass filter? What's the correct low pass filter to use here so that we can have a low phase lag feedback to the ETM?

 

We could try inputing a 4kHz carrier modulated width a depth of a few Hz at a modulation frequency of F1. Then we could take an FFT of the output of the discriminator and measure the width of the peak at F1 Hz. This seems like an arduous way to measure the frequency noise at a single frequency though.

It'll definitely be sensitive to DC offsets but there is already a filter bank on the INPUT filter so we can shape that as necessary. We could probably band-pass that from [4.5 - 5.3kHz] (which would correspond to a range of [73,87] MHz into a 2^14 frequency divider.

 

  4216   Thu Jan 27 23:21:50 2011 ranaSummaryGreen LockingDigital Frequency Discriminator

That's some pretty fast work! I thought we would be taking up to a week to get that happening. I wonder what's the right way to measure the inherent frequency noise of this thing?

Also, should the comparator part have some hysteresis (ala Schmidt trigger) or is it best to just let it twirl as is? Is it sensitive to DC offsets on the input or is there a high pass filter? What's the correct low pass filter to use here so that we can have a low phase lag feedback to the ETM?

  4215   Thu Jan 27 21:43:37 2011 KojiUpdateGreen Lockingno transmission of ALS signals

No signal is transmitted from C1:GCV-SCX_ETMX_ALS (on c1gcv) to C1:GCV-SCX_ETMX_ALS (on c1scx)

I can't find RFM definition for ALS channels in c1rfm. Where are they???

  4214   Thu Jan 27 21:10:47 2011 OsamuUpdate40m UpgradingCalibrated noise of green

I calibrated noise spectrum of green lock.

1. Measurement of conversion factor of ADC input from V to ct:

As a preparation, first I measured a conversion factor at ADC input of C1;GCX1SLOW_SERVO1.

It was measured while the output of AI ch6 as the output of C1;GCX1SLOW_SERVO2 with 1Hz, 1000ct(2000ct_pp) was directly connected into AA ch7 as the input of C1;GCX1SLOW_SERVO1. Amplitude at the output at AI ch6 was 616mVpp measured by oscilloscope, and C1;GCX1SLOW_SERVO1_IN1 read as 971.9ct_pp. So the conversion factor is calculated as 6.338e-4[V/ct].

2. Injection of a calibration signal:

When Green laser was locked to cavity with fast PZT and slow thermal, I injected 100Hz, 1000ct EXC at ETMX ASL. The signal was measured at C1:GCX1SLOW_SERVO1_IN1 as 5.314ct_rms. It can be converted into 3.368e-3Vrms using above result, and then converted into 3368Hz_rms using PZT efficiency as 1MHz/V. This efficiency was obtained from Koji's knowledge, but he says that it might have 30% or higher error. If somebody get more accurate value, put it into the conversion process from V to Hz here.

3. Conversion;

Frequency of green f=c/532nm=5.635e14[Hz] is fluctuating with above 3368Hz_rms,so the fluctuation ratio is 3368/5.635=5.977e-12, and it corresponds to length fluctuation of 37.5m. So, cavity fluctuation will be 5.977e-12*37.5=2.241e-10m_rms by 100Hz, 1000ct EXC at ETMX ASL.

4. Results;

Finally, we knew 5.314ct corresponds to 3368Hz and 2.241e-10m, so conversion factor from ct to Hz and ct to m are ;

633.8[Hz/ct] @ C1:GCX1SLOW_SERVO1

4.217e-11[m/ct] @ C1:GCX1SLOW_SERVO1

 

5. Calibration:

You can measure green noise spectrum at C1;GCX1SLOW_SERVO1_IN1 during lock,  and mutiply above result to convert Hz or m.

This calibration is effective above corner frequency of slow and fast servo around 0.5Hz and UGF of fast servo around 4kHz.

I show an example of calibrated green noise.

20110127_Calibrated_grrennoise.jpg

20110127_Calibrated_grrennoise.pdf

Each color show different band-width. Of course this results of calibration cactor does not depend on band-width. Noise around 1.2Hz is 6e-8Hz/rHz. It sounds a bit too good by factor ~2. The VCO efficiency might be too small.

 

Note that there are several assumptions in this calibration;

1. TF from actual PZT voltage to PZT mon is assumed to be 1 in all frequency. Probably this is not a bad assumption because circuit diagram shows monitor point is extracted PZT voltage directly.

2. However above assumption is not correct if the input impedance of AI is low.

3. As I said, PZT efficiency of 1MHz/V might be wrong.

 

I also measured a TF from C1:SUS-ETMX_ALS_EXC to C1:GCX1SLOW_SERVO1_IN1. It is similar as calibration injection above but for wide frequency. This shows a clear line of f^-2 of suspension.

20110127_TF_ETMXSUSEXC_to_PZTOUT.pdf

 

Files are located in /users/osamu/:20110127_Green_calibration.

  4213   Thu Jan 27 17:12:02 2011 Aidan, JoeSummaryGreen LockingDigital Frequency to Amplitude converter

Joe and I built a very simple digital frequency to amplitude converter using the RCG. The input from an ADC channel goes through a filter bank (INPUT), is rectified and then split in two. One path is delayed by one DAQ cycle (1/16384 s) and then the two paths are multiplied together. Then the output from the mixer goes through a second filter bank (LP) where we can strip off twice the beat frequency. The DC output from the LP filter bank should be proportional to the input frequency.

Input Channel: C1:GFD-INPUT_xxx

Output Channel: C1:GFD-LP_xxx

Joe compiled the code and we tested it by injecting a swept sine [100, 500]Hz in the input filter bank. We confirmed that output of the LP filter bank changed linearly as a function of the input frequency.

The next thing we need to do is add a DAC output. Once that's in place we should inject the output from a 4kHz VCO into the ADC. Then we can measure the transfer function of the loop with an SR785 (driving the VCO input and looking at the output of the DAC) and play around with the LP filter to make sure the loop is fast enough.

The model is to be found here:

/opt/rtcds/caltech/c1/core/advLigoRTS/src/epics/simLink/c1gfd.mdl

The attached figures show the model file in Simulink and a realtime dataviewer session with injecting a swept sine (from 500Hz to 100Hz) into the INPUT EXC channel. We've had some frame builder issues so the excitation was not showing on the green trace and, for some reason, the names of the channels are back to front in dataviewer (WTF?), - the lower red trace in dataviewer is actually displaying C1:GFD-LP_OUT_DAQ, but it says it is displaying C1:GFD-INPUT_OUT_DAQ - which is very screwy.

However, the basic principle (frequency to amplitude) seems to work.

  4212   Thu Jan 27 15:16:43 2011 josephbUpdateCDSUpdated generate_master_screens.py

I modified the generate_master_screens.py script in /opt/rtcds/caltech/c1/medm/master/ to handle changing the MCL (and MC_L) listings to ALS for the two ETM suspension screens and associated sub-screens.

The relevant added code is:

custom_optic_channels = ['ETMX',
{'MCL':'ALS','MC_L':'ALS'},
'ETMY',
{'MCL':'ALS','MC_L':'ALS'}]

 

for index in range(len(custom_optic_channels)/2):
   if optic == custom_optic_channels[index*2]:
     for swap in custom_optic_channels[index*2+1]:
       sed_command = start_sed_string + swap + "/" + custom_optic_channels[index*2+1][swap] + middle_sed_string + optic + file
       os.system(sed_command)

When run, it generates the correctly named C1:SUS-ETMX_ALS channels, and replaces MCL and MC_L with ALS in the matrix screens.

 

  4211   Thu Jan 27 11:04:27 2011 KojiUpdateGreen Lockingbeat freq scan

Experiment in the night of Jan 26.

o The arm was locked for the IR beam and was aligned for it.
o The green was aligned to the arm
o The beat freq was observed with the RF analyzer and the webcam.
o Engaged the ALS servo
o Compared the fluctuation of the beat freq with and without ALS
o Scanned the beat freq in order to find an IR resonance

The beat freq was scanned. A resonance for IR was found.
However, the residual motion of the arm was not within the line width of the IR resonance.

 To Do
- Improve the ALS servo (==>Koji)
- VCO noise characterization (==>Suresh is on it)
- Calibrate the PLL feedback (i.e. ALS error) into Hz/rtHz (==>Suresh)
- Calibrate the end green PZT fb into Hz/rtHz (==>Osamu is on it)
- Tuning of the suspension filters to reduce the bounce mode coupling.


DETAILS

o How to lock the arm with IR

  • Coarsely align the arm without lock. Transmittion was ~300 with MCTRANS ~40000
  • REFL11I is the error signal. unWhiten filter (FM1) should be on.
  • Unlock the MC and null the error and the arm trans offset by running the following commands

ezcaservo -g -0.1 -r C1:LSC-REFL11_I_OUTPUT C1:LSC-REFL11_I_OFFSET
ezcaservo -g -0.1 -r C1:LSC-REFL11_Q_OUTPUT C1:LSC-REFL11_Q_OFFSET
ezcaservo -g 0.1 -r C1:LSC-TRX_OUTPUT C1:LSC-TRX_OFFSET

  • Confirm the input matrix to pass REFL11I to MC path (why don't we use XARM path...?)

ezcawrite C1:LSC-MTRX_81 1.0

  • Servo configuration
    • For acquisition: Gain of 2. Only FM1 (1000:10) has to be on.
    • After the acquisition (TRX>200): The gain is to be changed to 1. FM2 and FM3 can be turned on for the LF boost.
  • Actuator matrix: connect MC path to ETMX and MC2

ezcawrite C1:LSC-OM_MTRX_18 1.0
ezcawrite C1:LSC-OM_MTRX_78 1.0

 

o How to align the green beam

  • After the alignment I went the end and aligned the last two steering mirrors.


o The beat freq monitor

  • Put the RF analyzer at the RF splitter of the RFPD output.
  • Used Zonet webcam (http://192.168.113.201:3037) for the remote monitoring

 

o How to engage the ALS servo

  • Preparation:
    • VCO PLL feedback comes to X_FINE path.
    • Put an offset of -850 to cancel too big offset (when the VCO is unlocked)
    • Use Y_FINE channel for the offset addtion. FM1 is 10mHz LPF in order to make the offset smooth.
    • Add X_FINE and Y_FINE by the matrix.
  • Control
    • Turn off X_FINE out. Leave Y_FINE output turned on.
    • Turn on ETMX ALS path.
    • Servo setting: FM1 1000:30 ON, others OFF, gain1
    • Wait for the beat comes in to the locking range at around 80MHz.
    • If the peak is too far, sweep Y_FINE offset in order to . Or change GCV slow thermal offset to let the beat freq jump.
    • You may have ambiguity of the feedback sign depending on which green has higher freq.
    • After the capture of the ALS lock, increse the gain up to 20. Turn on 0.1:boost at FM3.

 

o Comparison of the stability of the beat freq (Attachment3)

  • The spectra of the VCO PLL feedback was measured.
  • First of all, the signal was measured without ALS (blue).
    The PLL lost lock quite frequently, so the careful adjustment of the offset was necessary.Still I think there was slight saturation upconversion.
  • Then, the ALS was turned on (red). The gain was 20. This is an in-loop evaluation of the servo. The suppression was ~1000 at 1Hz.

o Beat freq scanning

  • The following command was used for the beat note scanning 

ezcastep -- "C1:GCV-YARM_FINE_OFFSET" "5,500"

  • Once the IR transmission was found, the scan was stopped.
  • Because the resultant rms stability of the arm was not within the line width of the cavity, the smooth resonant curve was not obtained.
  • From the shape of the error signal the peak-to-peak displacement (f>1Hz) was estimated to be +/-0.7nm. The dominant displacement
    in the period is 16Hz component.

 

  4210   Thu Jan 27 03:24:56 2011 KevinUpdateElectronicsPOY Optical Transfer Function

[Rana and Kevin]

I measured the optical transfer function of POY and fit the data using LISO. The fit can be found at http://lhocds.ligo-wa.caltech.edu:8000/40m/Electronics/POY. POY was missing the RF cage and back cover so I took those parts from AS55 in order to make these measurements.

POY does not have the unwanted oscillations at 225 MHz that POX has. Attachment 1 shows the transfer functions of POX and POY.

To measure the transfer functions, I used a 50/50 beam splitter to send half the light from an AM laser to POY and half the light to a New Focus 1611 reference photodiode. The transfer function for POY was measured as the transfer function of the signal from POY divided by the signal from the 1611. When I was measuring the transfer function for POX, I failed to ensure that the photodiodes were operating linearly. Before making the measurements for POY, I varied the RF power modulating the AM laser and recorded the magnitude of the transfer function at the 11 MHz peak. Attachment 2 shows these values. The measurements for POY were made in the linear region at an RF power of -10 dBm. The measurements for POX were made at 0 dBm and were most likely not in the linear region for POX.

  4209   Wed Jan 26 14:49:48 2011 AidanUpdateEnvironmentTurned on Control room AC

80 degrees is too uncomfortable in the control room so I turned on the AC. The set point is 74F.

  4208   Wed Jan 26 12:04:31 2011 josephbUpdateCDSExplanation of why c1sus and c1lsc models crash when the other one goes down

So apparently with the current Dolphin drivers, when one of the nodes goes down (say c1lsc), it causes all the other nodes to freeze for up to 20 seconds.

This 20 seconds can force a model to go over the 60 microseconds limit and is sufficiently long enough to force the FE to time out.  Alex and Rolf have been working with the vendors to get this problem fixed, as having all your front ends go down because you rebooted a single computer is bad.

[40184.120912] c1rfm: sync error my=0x3a6b2d5d00000000 remote=0x0
[40184.120914] c1rfm: sync error my=0x3a6b2d5d00000000 remote=0x0
[44472.627831] c1pem: ADC TIMEOUT 0 7718 38 7782
[44472.627835] c1mcs: ADC TIMEOUT 0 7718 38 7782
[44472.627849] c1sus: ADC TIMEOUT 0 7718 38 7782
[44472.644677] c1rfm: cycle 1945 time 17872; adcWait 15; write1 0; write2 0; longest write2 0
[44472.644682] c1x02: cycle 7782 time 17849; adcWait 12; write1 0; write2 0; longest write2 0
[44472.646898] c1rfm: ADC TIMEOUT 0 8133 5 7941

The solution for the moment is to start the computers at exactly the same time, so the dolphin is up before the front ends, or start the models by hand after the computer is up and dolphin running, but after they have timed out.  This is done by:

sudo rmmod c1SYSfe

sudo insmod /opt/rtcds/caltech/c1/target/c1SYS/bin/c1SYSfe.ko

 

Alex and Rolf have been working with the vendors to get this fixed, and we may simply need to update our Dolphin drivers.  I'm trying to get in contact with them and see if this is the case.

  4207   Wed Jan 26 12:03:45 2011 KojiUpdateCDSFront End multiple crash

This is definitely a nice magic to know as the rebooting causes too much hustles.

Also, you and I should spend an hour in the afternoon to add the suspension swtches to the burt requests.

Quote:

I killed the dead c1lsc model by typing:

sudo rmmod c1lscfe

I then tried starting just the front end model again by going to the /opt/rtcds/caltech/c1/target/c1lsc/bin/ directory and typing:

sudo insmod c1lscfe.ko

This started up just the FE again

 

  4206   Wed Jan 26 10:58:48 2011 josephbUpdateCDSFront End multiple crash

Looking at dmesg on c1lsc, it looks like the model is starting, but then eventually times out due to a long ADC wait. 

[  114.778001] c1lsc: cycle 45 time 23368; adcWait 14; write1 0; write2 0; longest write2 0
[  114.779001] c1lsc: ADC TIMEOUT 0 1717 53 181

I'm not sure what caused the time out, although there about 20 messages indicating a failed time stamp read from c1sus (its sending TRX information to c1lsc via the dolphin connection) before the time out.

Not seeing any other obvious error messages, I killed the dead c1lsc model by typing:

sudo rmmod c1lscfe

I then tried starting just the front end model again by going to the /opt/rtcds/caltech/c1/target/c1lsc/bin/ directory and typing:

sudo insmod c1lscfe.ko

This started up just the FE again (I didn't use the restart script because the EPICs processes were running fine since we had non-white channels).  At the moment, c1lsc is now running and I see green lights and 0x0 for FB0 status  on the C1LSC_GDS_TP screen.

At this point I'm not sure what caused the timeout.  I'll be adding some more trouble shooting steps to the wiki though.  Also, c1scx, c1scy are probably in need of restart to get them properly sync'd to the framebuilder.

I did a quick test on dataviewer and can see LSC channels such as C1:LSC-TRX_IN1, as well other channels on C1SUS such as BS sensors channels.

Quote:

STATUS:

  • Rebooted c1lsc and c1sus. Restarted fb many times.
  • c1sus seems working.
  • All of the suspensions are damped / Xarm is locked by the green
  • Thermal control for the green is working
  • c1lsc is frozen
  • FB status: c1lsc 0x4000, c1scx/c1scy 0x2bad
  • dataviewer not working 

 

  4205   Wed Jan 26 10:11:47 2011 AidanUpdateGreen Lockingcavity scan

Quote:

cavity_scan.png

 

Whether or not it's as clean as we'd like, it's really nice to see this result with real data.

  4204   Wed Jan 26 02:18:12 2011 KojiUpdateSUSETMX length to angle matrix

I have put an offset of 1000 counts to C1:SUS-ETMX_ALS_OFFSET. This actually misalign the mirror a lot.

While the offset is applied. I adjusted the balance of the coil matrix.
UL 1.580 UR 0.620
LL 0.420 LR 1.380

> ezcaread C1:SUS-ETMX_TO_COIL_0_0_GAIN
C1:SUS-ETMX_TO_COIL_0_0_GAIN = 1.58
> ezcaread C1:SUS-ETMX_TO_COIL_0_1_GAIN
C1:SUS-ETMX_TO_COIL_0_1_GAIN = 0.62
> ezcaread C1:SUS-ETMX_TO_COIL_0_2_GAIN
C1:SUS-ETMX_TO_COIL_0_2_GAIN = 0.42
> ezcaread C1:SUS-ETMX_TO_COIL_0_3_GAIN
C1:SUS-ETMX_TO_COIL_0_3_GAIN = 1.38

Now, we can keep TEM00 for green with +/-1000counts of push although the fast step of the offset make the lock lost.

It turned out that the step longitudinal input temporary misalign the mirror in pitch because the length and pitch are coupled.
I guess that we don't excite pitch if we push the mirror slowly. Eventually, we need f2p transfer function adjusted in the output matrix.

Kiwamu told us that:
(2)  Length to Alignment coupling. Pushing ETMX causes a misalignment.

 

  4203   Tue Jan 25 22:49:13 2011 KojiUpdateCDSFront End multiple crash

STATUS:

  • Rebooted c1lsc and c1sus. Restarted fb many times.
  • c1sus seems working.
  • All of the suspensions are damped / Xarm is locked by the green
  • Thermal control for the green is working
  • c1lsc is frozen
  • FB status: c1lsc 0x4000, c1scx/c1scy 0x2bad
  • dataviewer not working

1. DataViewer did not work for the LSC channels (liek TRX)

2. Rebooted LSC. There was no instruction for the reboot on Wiki. But somehow the rebooting automatically launched the processes.

3. However, rebooting LSC stopped C1SUS processes working

4. Rebooted C1SUS. Despite the rebooting description on wiki, none of the FE processes coming up.

5. Probably, I was not enough patient to wait for the completion of dorphine_wait? Rebooted C1SUS again.

6. Yes. That was true. This time I wait for everything going up automatically. Now all of c1pemfe,c1rfmfe,c1mcsfe,c1susfe,c1x02fe are running.
FB status for c1sus processes all green.

7. burtrestored c1pemfe,c1rfmfe,c1mcsfe,c1susfe,c1x02fe with the snapshot on Jan 25 12:07, 2010.

8. All of the OSEM filters are off, and the servo switches are incorrectly on. Pushing many buttons to restore the suspensions.

9. I asked Suresh to restore half of the suspensions.

10. The suspensions were restored and damped. However, c1lsc is still freezed.

11. Rebooting c1lsc freezed the frontends on c1sus. We redid the process No. 5 to No.10

12. c1x04 seems working. c1lsc, however, is still frozen. We decided to leave C1LSC in this state.

 

  4202   Tue Jan 25 21:57:59 2011 KojiUpdateGreen LockingSlow servo for green laser

1. The dewhitening filter CH6 had no output. I disconnected the cable and put it to the monitor out of the AI filter.
So the dewhitening is not in the loop.

2. I have made a thermal control filter

BANK1: pole 0Hz, zero 1mHz / LF boost stage
BANK2: pole 1mHz, zero 30mHz / LPF stage
BANK3: pole 1Hz, zero 0.1Hz / phase compensation stage
Gain: 0.05

It seems working with the gain of 0.05. As the thermal is very strong, the output has less than 10.
This means the we are effectively only using ~4bit. We need external filter.

Note that output of 30000counts were about 3V at  CH6.

3. Measured End PZT feedback with and without the thermal control. The UGF seems to be 0.2Hz.
The suppression at 10mHz is ~100. This is so far OK.

Quote:

I implemented a slow servo for green laser thermal control on c1scx.mdl. Ch6,7 of ADC and ch6 of DAC are assigned for this servo as below;

 

Ch6 of ADC: PDH error signal

CH7 of ADC: PZT feedback signal

CH6 of DAC: feedback signal to thermal of green laser

 

Note that old EPICS themal control cable is not hooked anymore.

I made a simple MEDM screen(...medm/c1scx/master/C1SCX_BCX_SLOW.adl) linked from GREEN medm screen (C1GCV.adl) on sitemap.

During this work, I noticed that some of the epics switch is not recovered by autoburt. What I noticed is filter switch of SUSPOS, SUSPIT, SUSYAW, SDSEN, and all coil output for ETMX.

I had no idea to fix them, probably Joe knows. I guess other suspensitons has the same problems.

 

  4201   Tue Jan 25 20:42:46 2011 OsamuUpdateGreen LockingSlow servo for green laser

I implemented a slow servo for green laser thermal control on c1scx.mdl. Ch6,7 of ADC and ch6 of DAC are assigned for this servo as below;

 

Ch6 of ADC: PDH error signal

CH7 of ADC: PZT feedback signal

CH6 of DAC: feedback signal to thermal of green laser

 

Note that old EPICS themal control cable is not hooked anymore.

I made a simple MEDM screen(...medm/c1scx/master/C1SCX_BCX_SLOW.adl) linked from GREEN medm screen (C1GCV.adl) on sitemap.

During this work, I noticed that some of the epics switch is not recovered by autoburt. What I noticed is filter switch of SUSPOS, SUSPIT, SUSYAW, SDSEN, and all coil output for ETMX.

I had no idea to fix them, probably Joe knows. I guess other suspensitons has the same problems.

  4200   Tue Jan 25 15:20:38 2011 josephbUpdateCDSUpdated c1rfm model plus new naming convention for RFM/Dolphin

After sitting down for 5 minutes and thinking about it, I realized the names I had been using for internal RFM communication were pretty bad.  It was because looking at a model didn't let you know where the RFM connection was coming from or going to.  So to correct my previous mistakes, I'm instituting the following naming convention for reflected memory, PCIE reflected memory (dolphin) and shared memory names.  These don't actually get used anywhere but the models, and thus don't show up as channel names anywhere else.  They are replaced by raw hex memory locations in the actual code through the use of the IPC file (/opt/rtcds/caltech/c1/chans/ipc/C1.ipc).  However it will make understanding the models easier for anyone looking at them or modifying them.

 

The new naming convention for RFM and Dolphin channels is as follows.

SITE:Sending Model-Receiving Model_DESCRIPTION_HERE

The description should be unique to that data being transferred and reused if its the same data.  Thus if its transfered to another model, its easy to identify it as the same information.

The model should be the .mdl file name, not the subsystem its a part of.  So SCX is used instead of SUS.  This is to make it easier to track where data is going.

In the unlikely case of multiple models receiving, it should be of the form SITE:Sending Model-Receiving Model 1-Receiving Model 2_DESCRIPTION_HERE.  Seperate models by dashes and description by underscores.

Example:

C1:LSC-RFM_ETMX_LSC

This channel goes from the LSC model (on c1lsc) to the RFM model (on c1sus).  It transfers ETMX LSC position feedback.  The second LSC may seem redundant until we look at the next channel in the chain.

C1:RFM-SCX_ETMX_LSC

This channel goes from the RFM model to the SCX model (on c1iscex). It contains the same information as the first channel, i.e. ETMX LSC position feedback.

 

I have updated all the models that had RFM and SHMEM connections, as well as adding all the LSC communciation connections to c1rfm.  This includes c1sus, c1rfm, c1mcs, c1ioo, c1gcv, c1lsc, c1scx, c1scy.  I have not yet built all the models since I didn't finish the updates until this afternoon.  I will build and test the code tomorrow morning.

 

 

 

  4199   Tue Jan 25 06:48:55 2011 kiwamuUpdateGreen LockingTo do list

Here are some tasks that I want someone to work on during my absence.

1. Y-arm alignment for IR

 Basically we gradually have to move onto the Y-arm locking at some point.

Prior to it we need to align the Y arm for IR. Probably we have to touch PZT1 and PZT2.

It would be very nice if the X-arm alignment also gets improved together with this work. 

 

2. Temperature feedback with a digital control for X end PDH lock

  Need a temperature feedback not with an analog way but with a digital way because we want to put an offset and the feedback signal at the same time (#4198).

 Right now the temperature control input of the laser is connected to a slow DAC (#3850).

Probably we should plug the feedback signal from the PDH box to the fast ADC (i.e. c1iscex), and then connect a fast DAC to the laser temperature.

This entry maybe helpful.

 

3. Calibration of optical gain for IR arm locking

 In order to evaluate the performance of the green locking, one of the key points is the IR PDH signal.

Because it tells us how much the motion of the X arm is suppressed at IR when the green lock is engaged.

To get this information in m/sqrtHz, we need to know the optical gain.

 

4. MC servo characterization and PSL frequency noise measurement

 SInce the green beat note tells us the frequency difference between the MC and the arm in the current configuration, we should know how the MC servo is.

Along with this work, I need someone to measure the PSL frequency noise, when it is locked to the MC over the frequency range from 0.01Hz to 1kHz.

 

5. PLL characterization 

 Solve this issue (#4195) and make it reliable.

  4198   Tue Jan 25 05:26:51 2011 kiwamuUpdateGreen Lockingcavity scan

cavity_scan.png

I scanned the X arm by changing an offset for the feedback to ETMX while the arm stayed locked by the green locking.

But the resultant plot is still far away from a beautiful one.

Changing the offset broke the lock frequently, so eventually I couldn't measure the stability of the IR-PDH signal at the resonance. 

 

 The plot above is a result of the scanning. You can see there is a clear resonance at the center of the plot.

However the lock frequently became unstable when I was changing the offset.

It looked like this unstability came from the end PDH lock. I guess there are two possible reasons:

  (1)  feedback range for the laser PZT is not wide enough. Right now the range is limited by a SR560, which has been used for a summing amplifier.

  (2)  Length to Alignment coupling. Pushing ETMX causes a misalignment.

The issue (1) can be easily solved by engaging the temperature feedback, which helps actuating the laser frequency a lot at DC.

The issue (2) will be also solved by well align the IR beam, the arm cavity and the green beam.

  4197   Tue Jan 25 00:09:54 2011 KojiUpdateGeneralJenne laser is at PSL Lab

I found Tara's elog entry that Jenne laser is at PSL Lab.
Since we recently use it frequently, we should be aware where it is now.

  4196   Mon Jan 24 14:27:13 2011 kiwamuUpdateGreen LockingRe: X arm locked !

Quote: #4193

So, how is the IR error signal stabilized when the IR is brought in to the resonance?

I can see the linear trend of 0.1V/s from 5s to 10s.  This corresponds to 100kHz/s and 13nm for the residual beat drift and the arm length motion, respectively. That sounds huge.

 I haven't yet taken any data for the IR fluctuation when the Xarm is locked by the green locking.

You are right, the DC drift was due to a lack of the DC gain. But don't worry about that, because this issue has been solved.

 


(DC gain issue)

  The lack of DC gain was because I put an IIR filter called ''DC block" that I made. It has 1/f shape below 30mHz and becomes flat above it.

The purpose of this filter was to avoid a DC kick when it starts feeding back to ETMX.

Usually the output signal from the PLL has an offset, typically ~5V, then this offset is also acquired into the ADC and eventually kicks ETMX through the feedback.

So when I took the time series data I enabled the 'DC block', that's why it drifts slowly.

 After taking the time series, I found that without this 'DC block' technique, the lock can be achieved by appropriately subtracting the offsets with epics numerical values.

This subtraction technique, of course, gave me more stable lock at DC.

 


(open loop transfer function)

Here is the open-loop TF of the arm locking I measured last night:

masslock_oltf.png

The IIR filter chain has the following poles and zeros:

     pole 0.1Hz, 1000Hz,

   zero 1Hz, 30Hz

For the fitting I assume that the ETMX pendulum has a resonance at 1Hz with Q of 5. Also I put the cavity pole at 24 kHz, assuming the finesse is 80 at 532 nm.

I just fitted the gain and the time delay by my eyes.

If I believe the result of the fitting, whole time delay is 330 usec, which sounds pretty large to me.

  4195   Mon Jan 24 13:08:07 2011 kiwamuUpdateGreen LockingRe: X arm locked !

Quote: #4192

Also, the PLL diagram seems to show that you have a 1/f^2 loop: 1/f from the SR560 and 1/f from the Hz->rad conversion ??

Well, the diagram I drew is true. I also have been confused by this 1/f^2 issue in our PLL.

As Rana pointed out, the open-loop TF should become 1/f^2 over most of the frequency range, but it still remains 1/f above 5kHz for some reasons. 

 Need more investigations.

e_pll_oltf.png

 At the beginning I tried phase-locking the VCO to the beat note without any external filters (i.e. SR560 see here), but I never succeeded.

It was because the hold-in range of the PLL was not sufficiently wide, it could stay locked within frequency range of less than +/- 1MHz from the center frequency of 80 MHz.

This is obviously not good, because the beat note typically fluctuates by more than +/- 3MHz in time scale of 1 sec or so.

  So I decided to put an external filter, SR560,  in order to have a larger DC gain and a higher UGF.

Somehow I unconsciously tuned the SR560 to have a pole at 1Hz with the gain of 2000, which shouldn't work in principle because the open-loop will be 1/f^2.

However I found that the PLL became more robust, in fact it can track the input frequency range of +/- 5MHz.

The open-loop TF is shown above. For comparison I plotted also the open-loop TF wehn it's without the SR560.

I checked the frequency of the VCO output when it was phase-locked to a Marconi, it was healthy (i.e. the same frequency as the input signal from Marconi).

  4194   Mon Jan 24 10:39:16 2011 josephbHowToDAQDAQ Wiki Failure

Actually both port 8087 and 8088 work to talk to the frame builder.  Don't let the lack of a daqd prompt fool you.

 

Here's putting in the commands:

rosalba:~>telnet fb 8088 Trying 192.168.113.202...

Connected to fb.martian (192.168.113.202). Escape character is '^]'.

shutdown

0000Connection closed by foreign host.

rosalba:~>date Mon Jan 24 10:30:59 PST 2011

 

Then looking at the last 3 lines of restart.log in /opt/rtcds/caltech/c1/target/fb/

daqd_start Fri Jan 21 15:20:48 PST 2011

daqd_start Fri Jan 21 23:06:38 PST 2011

daqd_start Mon Jan 24 10:30:29 PST 2011

 

So clearly its talking to the frame builder, it just doesn't have the right formatting for the prompt.  If you try typing in "help" at the prompt, you still get all the frame builder commands listed and can try using any of them.

However, I'll edit the DAQ wiki and indicate 8087 should be used because of the better formatting for the prompt.


Quote:
Apparently, 8087 is the right port. Various elog entries from Joe and Kiwamu say 8087 or 8088. Not sure what's going on here.

After figuring this out, I activated the C1:GCV-XARM_COARSE_OUT_DAQ and C1:GCV-XARM_FINE_OUT_DAQ and set both of them to be recorded at 2048 Hz. We are loading filters and setting gains into these filter modules such that the OUT signals will be calibrated into Hz (that's why we used the OUT instead of the IN1 as there was last night).

 

  4193   Mon Jan 24 10:19:21 2011 KojiUpdateGreen LockingX arm locked !

Well... The ALS loop is engaged and the error was suppressed.
So, how is the IR error signal stabilized when the IR is brought in to the resonance?

I can see the linear trend of 0.1V/s from 5s to 10s.  This corresponds to 100kHz/s and 13nm
for the residual beat drift and the arm length motion, respectively. That sounds huge. The DC gain must be increased.

  4192   Mon Jan 24 09:33:08 2011 ranaUpdateGreen LockingX arm locked !

Very cool.

But the PLL seems very fishy to me. The ZP-3MH needs 13 dBm to operate correctly. You should change the MODLEVEL input of the VCO so as to make the LO input of the mixer go up to 13 dBm. Then the input from the PD should be ~0 dBm.

Also, the PLL diagram seems to show that you have a 1/f^2 loop: 1/f from the SR560 and 1/f from the Hz->rad conversion ??

  4191   Mon Jan 24 02:58:46 2011 kiwamuUpdateGreen LockingX arm locked !

I succeeded in green-locking the X arm by feeding back the beat signal to ETMX.

Here are some quick reports. Some more details will be posted tomorrow.

 

The below shows a time series data of the PLL feedback signal when the servo was acquiring the lock.

time_series.png

At t = -2 sec. I started feeding back the signal to ETMX with the gain 50 times smaller than its nominal.

Then at t = 0 sec.I switched on a low frequency boost (pole 0.1Hz and zero 1Hz) to make it more robust.

At t = 3 sec. I increased the gain to the nominal.

Finally the UGF became ~ 60 Hz according to my open loop measurement by diaggui.

However I couldn't make the UGF higher than 60Hz because the more gain caused a instability for some reasons.

 

Here is a diagram for the green locking.

I used the same VCO box as we setup on the last Friday (see #4189).

 green_one_arm.png

  4190   Sat Jan 22 02:23:26 2011 KojiUpdateGreen Lockingsome more progress

What is the point to use the error instead of the feedback? It does not make sense to me.

If the cable is flaky why we don't solder it on the circuit? Why we don't put a buffer just after the test point?

It does not make sense to obtain the error signal in order to estimate the freeruning noise without the precise loop characterization.
(i.e. THE FEEDBACK LOOP TRINITY: Spectrum, Openloop, Calibration)

RA: I agree that feedback would be better because we could use it without much calibration. But the only difference between the "error signal" and the "feedback signal" in this case is a 1.6:40 pole:zero stage with DC gain of 0 dB. So we can't actually use either one without calibration and the gain between these two places is almost the same so they are both equally bad for the SNR of the measurement. I think that Suresh and Kiwamu are diligently reading about PLLs and will have a more quantitative result on Monday afternoon.

 

  4189   Sat Jan 22 02:11:09 2011 kiwamuUpdateGreen Lockingsome more progress

[Rana, Suresh, Kiwanu]

 We did the following things:

   *  taking the VCO stability data from the error signal instead of the feedback

   *  tried calibrating the signal but confused

   *  increased the modulation depth of the green end PDH.

--

 We found that a cable coming out from the VCO box was quite touchy. This cable was used for taking the feedback signal.

When we touched the cable it made a big noise in the feedback. So we decided to remove the cable and take the signal from the error point (i.e. just after the mixer and the LPF.)

In order to correct that signal to the one in terms of the feedback signal, we put a digital filter which is exactly the same as that of the PLL (pole at 1.5 Hz, zero at 40 Hz, G=1) .

However for some reasons the signal shown in the digital side looked completely mis-calibrated by ~ 100. We have no idea what is going on.

Anyway we are taking the data over tonight because we can correct the signal later. The 2nd round data started from AM1:40

  4188   Sat Jan 22 02:03:55 2011 KojiUpdateGreen LockingExamining the stability of VCO PLL at low frequencies

Damn. If this figure is true, we were looking at wrong signal. We should look at the feedback signal to the VCO.

  4187   Sat Jan 22 01:56:04 2011 SureshUpdateGreen LockingExamining the stability of VCO PLL at low frequencies

[Kiwamu, Suresh, Rana]

Our goal:

        We wished to determine the performance of the VCO PLL at low frequencies,. 

The procedure we followed:

        The scheme is to use the Marconi (locked to Rb Clock) as an 80MHz reference and lock to it using the PLL. 

        We set up the VCO PLL as in the diagram shown in the attachment and obtained the spectra shown below.

Results:

          We need to figure out the PLL servo gain profile in order to build the Inv PLL filter....

 

   

 

 

VCO_PLL_stability.png

 

 

  4186   Fri Jan 21 23:55:25 2011 ranaConfigurationLSCPhase Noise Measurement filter

We've set up a beat note measurement between the VCO driver and the Marconi (see Suresh's elog).

Here's the 'unWhiten' filter for compensating the SR560 TF.

It has poles = 1 mHz, 5 kHz, 5 kHz

and  zeros = 30 mHz, 1 kHz

The gain is set to be ~0.001 in the 1-100 Hz band to compensate the G=1000 of the SR560.

  4185   Fri Jan 21 23:17:54 2011 ranaHowToDAQDAQ Wiki Failure

The DAQ Wiki pages say to use port 8088 for restarting the Frame Builder. I tried this to no avail.

op440m:daq>telnet fb 8088
Trying 192.168.113.202...
Connected to fb.martian.
Escape character is '^]'.
^]
telnet> quit
Connection to fb.martian closed.
op440m:daq>telnet fb 8087
Trying 192.168.113.202...
Connected to fb.martian.
Escape character is '^]'.
daqd> shutdown
OK
Connection to fb.martian closed by foreign host.

Apparently, 8087 is the right port. Various elog entries from Joe and Kiwamu say 8087 or 8088. Not sure what's going on here.

After figuring this out, I activated the C1:GCV-XARM_COARSE_OUT_DAQ and C1:GCV-XARM_FINE_OUT_DAQ and set both of them to be recorded at 2048 Hz. We are loading filters and setting gains into these filter modules such that the OUT signals will be calibrated into Hz (that's why we used the OUT instead of the IN1 as there was last night).

  4184   Fri Jan 21 17:59:27 2011 josephb, alexUpdateCDSFixed Dolphin transmission

The orientation of the Dolphin cards seems to be opposite on c1lsc and c1sus.  The wide part is on top on c1lsc and on the bottom on c1sus.  This means, the cable is plugged into the left Dolphin port on c1lsc and into the right Dolphin port on c1sus.  Otherwise you get a wierd state where you receive but not transmit.

  4183   Fri Jan 21 15:26:15 2011 josephbUpdateCDSc1sus broken yesterday and now fixed

[Joe, Koji]
Yesterday's CDS swap of c1sus and c1iscex left the interfometer in a bad state due to several issues.

The first being a need to actually power down the IO chassis completely (I eventually waited for a green LED to stop glowing and then plugged the power back in) when switching computers.  I also plugged and plugged the interface cable from the IO chassis and computer while powered down.  This let the computer actually see the IO chassis (previously the host interface card was glowing just red, no green lights).

Second, the former c1iscex computer and now new c1sus computer only has 6 CPUs, not 8 like most of the other front ends.  Because it was running 6 models (c1sus, c1mcs, c1rms, c1rfm, c1pem, c1x02) and 1 CPU needed to be reserved for the operating system, 2 models were not actually running (recycling mirrors and PEM).  This meant the recycling mirrors were left swinging uncontrolled.

To fix this I merged the c1rms model with the c1sus model.  The c1sus model now controls BS, ITMX, ITMY, PRM, SRM.  I merged the filter files in the /chans/ directory, and reactivated all the DAQ channels.  The master file for the fb in the /target/fb directory had all references to c1rms removed, and then the fb was restarted via "telnet fb 8088" and then "shutdown".

My final mistake was starting the work late in the day.

So the lesson for Joe is, don't start changes in the afternoon.

Koji has been helping me test the damping and confirm things are really running.  We were having some issues with some of the matrix values.  Unfortunately I had to add them by hand since the previous snapshots no longer work with the models.

  4182   Fri Jan 21 11:45:01 2011 AidanConfigurationLockingBallpark figures for Green Locking PLLs (Digital vs Analogue)

Quote:

If we use a digital PLL for locking the frequency of the PSL and END green lasers then we can expect a UGF of around 1kHz (assuming a sampling rate of 16kHz). Let's assume a simple 1/f loop giving a loop gain of ~1000x at 1Hz. If the free-swinging ETM pendulum motion at 1Hz is of the order of 1 micron, then the residual motion at 1Hz, once we lock the digital PLL by actuating on the ETM position, will be of the order of 1nm. This is bordering on too high.

Alternatively, is we use an analogue PLL then we can expect a much higher UGF and many orders of magnitude more gain at 1Hz (see here). So we would expect the residual motion of the pendulum to be much smaller - probably limited by some other noise source somewhere in the system (I doubt it's going to be reduced by 12 orders of magnitude).

RA: I think ballpark's not good enough for this. To see what's good enough, we need to to an analysis similar to what Bram has for the ALS. Get the 40m seismic spectrum from the arm locking spectrum or the green laser feedback signal and then correct it for a realistic loop shape.

KA: For this purpose I have made the simulink model for the green locking more than a year ago, but the entire green team has consistently neglected its presence...
https://nodus.ligo.caltech.edu:30889/svn/trunk/docs/upgrade08/Green_Locking/Servo_modeling/091121/

 Agreed. It doesn't completely rule out the digital PLL. I'll check out Kiwamu's model.

  4181   Fri Jan 21 02:45:43 2011 kiwamuUpdateGreen Lockinginterface for PLL to ADC

 [Suresh, Kiwamu]

  We did the following things:

     - installed a 1/10 voltage divider such that the signal won't be saturated at the AA board (see here)

     - put a Ithaco preamplifier 1201 as a whitening filter

     - checked the entire beat detection system without using the real beat note

Here are some items to be done before the sun goes down tomorrow:

       - calibration of ADC and the interfaces including the voltage divider and the whitening filter.

     - fine matching of unwhitening filter at the digital side

         - PLL response measurement ( freq to voltage response ) over the frequency range of interest

         - plotting an well calibrated spectrum of the PLL output 


(whitening filter)

The Ithaco 1201 was setup to have a zero at 0 Hz and two poles at 0.1 Hz and 10 Hz in order to emphasize the signal over the frequency range of interest.

Around 1Hz it is supposed to have a gain of 1000. These settings have done by tweaking the knobs on the front panel of the Ithaco 1201.

In addition to that, we made an unwhitening filter in digital filter banks. This filter was designed to cancel the analog whitening filter.

(system check) 

 To check the entire beat detection system, we phase-locked the VCO to a Marconi running at 80 MHz, which is the center frequency of the VCO.

Then we imposed a frequency modulation on the Marconi to see if the signal is acquired to ADC successfully or not. It's quite healthy.

According to the spectra corrected by the unwhitening filter, we confirmed that the noise floor at 1Hz is order of 1Hz/sqrt Hz, which is already quite good.

Then we took several spectra while putting a modulation on the Marconi at a different frequency in each measurement.

The peak due to the artificial modulation essentially works as a calibration peak in the spectra.

So in this way we briefly checked the flatness of the response of the system in the frequency domain.

As a result we found that the response is not perfectly flat in the range of 0.05 - 30Hz, probably due to a mismatch of the combination of the whitening and unwhitening filters.

We will check it tomorrow.

 

  4180   Thu Jan 20 22:17:12 2011 ranaSummaryLSCFPMI Displacement Noise

I found this old plot in an old elog entry of Osamu's (original link).

It gives us the differential displacement noise of the arms. This was made several months after we discovered how the STACIS made the low frequency noise bad, so I believe it is useful to use this to estimate the displacement noise of the arm cavity today. There are no significant seismic changes. The change of the suspension and the damping electronics may produce some changes around 1 Hz, but these will be dwarfed by the non-stationarity of the seismic noise.

  4179   Thu Jan 20 18:20:55 2011 josephbUpdateCDSc1iscex computer and c1sus computer swapped

Since the 1U sized computers don't have enough slots to hold the host interface board, RFM card, and a dolphin card, we had to move the 2U computer from the end to middle to replace c1sus.

We're hoping this will reduce the time associated with reads off the RFM card compared to when its in the IO chassis.  Previous experience on c1ioo shows this change provides about a factor of 2 improvement, with 8 microseconds per read dropping to 4 microseconds per read, per this elog.

So the dolphin card was moved into the 2U chassis, as well as the RFM card.  I had to swap the PMC to PCI adapter on the RFM card since the one originally on it required an external power connection, which the computer doesn't provide.  So I swapped with one of the DAC cards in the c1sus IO chassis.

But then I forgot to hit submit on this elog entry..............

  4178   Thu Jan 20 17:00:39 2011 AidanConfigurationLockingBallpark figures for Green Locking PLLs (Digital vs Analogue)

If we use a digital PLL for locking the frequency of the PSL and END green lasers then we can expect a UGF of around 1kHz (assuming a sampling rate of 16kHz). Let's assume a simple 1/f loop giving a loop gain of ~1000x at 1Hz. If the free-swinging ETM pendulum motion at 1Hz is of the order of 1 micron, then the residual motion at 1Hz, once we lock the digital PLL by actuating on the ETM position, will be of the order of 1nm. This is bordering on too high.

Alternatively, is we use an analogue PLL then we can expect a much higher UGF and many orders of magnitude more gain at 1Hz (see here). So we would expect the residual motion of the pendulum to be much smaller - probably limited by some other noise source somewhere in the system (I doubt it's going to be reduced by 12 orders of magnitude).

RA: I think ballpark's not good enough for this. To see what's good enough, we need to to an analysis similar to what Bram has for the ALS. Get the 40m seismic spectrum from the arm locking spectrum or the green laser feedback signal and then correct it for a realistic loop shape.

KA: For this purpose I have made the simulink model for the green locking more than a year ago, but the entire green team has consistently neglected its presence...
https://nodus.ligo.caltech.edu:30889/svn/trunk/docs/upgrade08/Green_Locking/Servo_modeling/091121/

  4177   Thu Jan 20 15:39:59 2011 AidanUpdateLockingUpper limit on frequency noise of ADC

[Aidan, Kiwamu]

Kiwamu and I plugged the output from a DS3456 function generator into the ADC and started recording the data. The func. generator output a 237.8Hz, 1Vpp sine wave. We chose this value because it corresponds to the FSR of a 38.5m cavity (=3.896MHz) divided by 2^14, the frequency divider amount we intend to use.

Since 1 FSR divided down is 237.8Hz and corresponds to a length change of the cavity of 532nm/2 = 266nm, then we can, roughly, say that a frequency change of 1Hz corresponds to a length change in the cavity of approximately 1nm. The width of the 237.8Hz peak in the spectra corresponds to an upper limit on the noise floor due to digitizing the signal (this could be limited by the ADC, or the function generator, or the windowing on the FFT).

The FWHM of the peak in the spectrum was approximately 5mHz, corresponding to an uncertainty in the length of the cavity of about 6pm (we used a Hanning Window, 50% overlap and a BW of 2.92mHz, 7 averages). Regardless of what is the dominant contribution to the width of the peak, this implies that the frequency noise associated with digitizing a signal in the ADC is much smaller than we require and will not limit our performance if we choose to use a frequency divider and digital PLL with the Green Locking.

RA: Here's the previous measurement

  4176   Thu Jan 20 15:15:39 2011 kiwamuUpdateGreen Lockingstatus update: PLL connected to ADC

I realized that the black AA board I mentioned on the last entry has the same range issue as Valera reported before (see #3911)

Basically our ADC card has +/- 10V input range, but on the other hand the AA board is already limited by approximately +/- 2V.

We have to fix it.

Quote: #4174

  The output signal from the VCO box goes to a black beakout board on 1X2 rack though a BNC cable.  

Then the signal comes out from the back side of the board with DB39 style, so I put a DB39 to SCSI adapter so that we can take it to the IO chasis.

Now the SCSI is connected to ADC_1 (the second ADC card) on the IO chasis at 1X1. 

  4175   Thu Jan 20 10:15:50 2011 josephbUpdateCDSc1scy error

This is caused by an insufficient number of active DAQ channels in the C1SCY.ini file located in /opt/rtcds/caltech/c1/chans/daq/.  A quick look (grep -v # C1SCY.ini) indicates there are no active channels.  Experience tells me you need at least 2 active channels.

Taking a look at the activateDAQ.py script in the daq directory, it looks like the C1SCY.ini file is included, by the loop over optics is missing ETMY.  This caused the file to improperly updated when the activateDAQ.py script was run.  I have fixed the C1SCY.ini file (ran a modified version of the activate script on just C1SCY.ini).

I have restarted the c1scy front end using the startc1scy script and is currently working.

Quote:
 Here is the error messages in the dmesg on c1iscey
[   39.429002] c1scy: Invalid num daq chans = 0
[   39.429002] c1scy: DAQ init failed -- exiting
 

 

  4174   Thu Jan 20 04:43:28 2011 kiwamuUpdateGreen Lockingstatus update: PLL connected to ADC

 I connected the PLL signal to the ADC on c1ioo. 

So now we are able to take the data into the digital world, and will be able to feedback signals to the suspensions.

 The output signal from the VCO box goes to a black beakout board on 1X2 rack though a BNC cable.  

Then the signal comes out from the back side of the board with DB39 style, so I put a DB39 to SCSI adapter so that we can take it to the IO chasis.

Now the SCSI is connected to ADC_1 (the second ADC card) on the IO chasis at 1X1. 

 

  Additionally I modified the green locking simulink model, C1GCV, in order to pick the right ADC channels.

A medm screen for green locking is now under the construction. I put a link on the sitemap screen, so anyone can look at the half-baked green locking screen.

Any comments and suggestions are really welcome.

  4173   Thu Jan 20 04:03:02 2011 kiwamuUpdateCDSc1scy error

 I found that c1scy was not running due to a daq initialization error.

 I couldn't figure out how to fix it, so I am leaving it to Joe.


 Here is the error messages in the dmesg on c1iscey
[   39.429002] c1scy: Invalid num daq chans = 0
[   39.429002] c1scy: DAQ init failed -- exiting
 
 
Before I found this fact, I rebooted c1iscey in order to recover the synchronization with fb.
The synchronization had been lost probably because I shutdowned the daqd on fb.
  4172   Thu Jan 20 01:50:30 2011 KevinUpdateElectronicsPOX Transfer Functions

[Koji, Kevin]

We fit the entire POX optical transfer function from 1 MHz to 500 MHz in LISO. The fit is on the wiki at http://lhocds.ligo-wa.caltech.edu:8000/40m/Electronics/POX. Using LISO's root fitting mode, we found that the transfer function has five poles and four zeros.

I will work on making plots of the residuals. This is difficult because by default, LISO does not calculate the fitting function at the frequencies of the data points themselves and I haven't figured out how to force it to do this yet.

  4171   Thu Jan 20 00:39:22 2011 kiwamuHowToCDSDAQ setup : another trick

Here is another trick for the DAQ setup when you add a DAQ channel associated with a new front end code.

 

 Once you finish setting up the things properly according to this wiki page (this page ), you have to go to 

      /cvs/cds/rtcds/caltech/c1/target/fb

and then edit the file called master

This file contains necessary path where fb should look at, for the daqd initialization.

Add your path associated with your new front end code on this file, for example:

        /opt/rtcds/caltech/c1/chans/daq/C1LSC.ini

       /opt/rtcds/caltech/c1/target/gds/param/tpchn_c1lsc.par

After editing the file, restart the daqd on fb by the usual commands:

             telnet fb 8088

             shutdown

  4170   Wed Jan 19 17:00:23 2011 KevinUpdateElectronicsPOX Transfer Functions

 The value of I_dc was a mistake. The value should be 240 µA.

The widths of the resonance peaks are listed below the fits to each peak on the wiki.

ELOG V3.1.3-