The plots in the previous Elog includes delay and a little attenuation by RF cables and the RF mux.

Today I separately calculated the delay and attenuation for an RG405 cable (550 cm) and the RF mux(using really small RF cables). These delays should be accounted for when fitting the transfer function of Demodulator boards and transimpedance of PDs.

The plots are in both semilogx and linear.

 A time delay can be modeled as the exponential transfer function :  e^(-sT_d)  as seen HERE . Therefore the slope of the phase gives us the time delay.

A RG405 coaxial cable, exactly 5.5 meters in length, was fit to an ideal delay function e^(-sT_d) , with T_d = 150 ns.

The plots shows the actual data, fit data and data after correction using the ideal model stated above.

Conclusion:

Delay in RG405 cables is approximately 27.27 ns per meter. This value can be used to correct the phase in measurements of transimpedance for each PD by dividing out the ideal transfer function for time delay.

[EDIT: This looks like we have about 12 % the speed of light inside the RF cables. Too small to be true. I will check tomorrow if the Network analyzer itself has some delay and update this value.]

The varying attenuation of about 1dB due to the cable is not compensated by this. We need to separately include this.

Things to do:

1) Get the length of RF cables that is being used by each PD, so that the compensation can be made.

2) Calculate the attenuation and delay caused by RF multiplexer and Demodulator boards. Include these in the correction factor for transimpedance measurements. 

A time delay can be modeled as the exponential transfer function :  e^(-sT_d)  as seen HERE . Therefore the slope of the phase gives us the time delay.

The transfer function of RF multiplexer in rack 1Y1 (NI PXI-2547) was fit to an ideal delay function e^(-sT_d) , with T_d = 59 ns.

The plots shows the actual data, fit data and data after correction using the ideal model stated above.

Conclusion:

Delay the RF Multiplexer is approximately 59 ns. This value can be used to correct the phase in measurements of transimpedance for each PD by dividing out the ideal transfer function for time delay.

 I used vector fitting to fit the transfer functions between RF input and PD RF MON of demodulator boards. These fittings can certainly do a lot better on LISO, but for the time being I will assume these to be good enough and change the main PDFR scripts to calibrate out this factor and get a decent reading of PD transimpedance. Then it will just be a matter of changing the transfer function parameters. A lot of work needs to be done on the PDFR interface and plot features.

Attached: The plots showing data and fits.

 Koji asked me to get the calibration of the PZT counts to Volts for the the X and Y ends. Yesterday, I went inside the lab and took some measurements from the digital readout of the PZT by giving in a DC offset(-5 to +5 volts) to PZT_Out and read out from these channels:

For X-end:  C1:ALS-X-SLOW_SERVO1_IN1

For Y-end:  C1:ALS-Y-SLOW_SERVO1_IN1

Since a 20dB attenuator was placed in the path of X-arm readout while taking the Transfer functions(Detail), I did the calibration measurements without removing it from the path. However, for the Y arm there was no attenuator in the readout path.

The obtained calibration values are :

X- arm PZT : [146.3 +/- 2.37 ]  counts/Volt 

Y- arm PZT :  [ 755.1 +/- 3.6]    counts/Volt

The attached are the fit and data plots for the above calibration.

1) Don't be brainless. Redo the fitting of the Y arm. Obviously the fit is not good.

2) How can you explain the value from the ADC bit and range?

e.g. +/-10V range 16bit ADC => 2^16/20 = 3276.8 count/V

 The PZT seems to saturate at around +/- 3500 counts. So for the Y arm, I excluded the saturated points and fitted the data points again.

As for the calibration number, we expect the 3276.8 count/V for +/- 10 V range of a 16 bit ADC but the number is ~800 count/V. I couldn't figure out a reason why the number is so different.

The new calibration values are :

X- arm PZT : [146.3 +/- 2.37 ]  counts/Volt   (with a 20 dB attenuator included in the path)

Y- arm PZT :  [ 797 +/- 3.6]    counts/Volt  

I will get the calibration in MHz/V of PZT actuation and check whether these numbers make any sense.

 The PZT actuation on the laser frequency in MHz/V ( assuming the previous calibration here of the PZT count/V) is :

X- arm: 33.7 MHz/V

Y- arm: 14.59 MHz/V

This number seems to be wrong by a factor of 10. 

So we[I and EricQ] decided to trace the cables that run into the ADC from the PZT Out. We found a black LEMO box in the path to ADC,which is  an anti-aliasing filter for each input channel. However,in theory the response of this filter should be flat up until a few kHz i.e. for  the DC gain it should be 1. But we will manually test it and look at the DC gain of the LEMO box.

Sitting down to work on the IFO, I couldn't lock the Yarm.  I looked at the error signal as well as the transmission on Dataviewer, as usual, and saw that the POY error signal was almost non-existant. 

Since there was work on the POY table today (Steve removed the oplev test setup, elog 10489 and Q centered the SRM oplev after doing SRMI alignment, no elog yet), I went out to have a look at the table. 

There was nothing occluding the POY beam, which I traced back to the edge of the table.  The beam looked nice and round, so I decided that wasn't it.  I jiggled the PD cables, and lo and behold, the POY RF out cable almost came off in my hand it was so loose.  My suspicion is that whomever was the last to put the POY RF out back didn't tighten the cable and then the work today jiggled the cable loose.  I tightened the cable, and by the time I was back to the control room the arm was locked and Koji was already running the alignment scripts.

In April, Koji logged that he had made some changes to the Yend QPD whitening board (elog 9854).  Today, I pulled the Xend board to see if it had the same modifications.  The filter shapes all seem to be the same (as in, the capacitors at the output filters were removed, etc.), and the final gain is the same.  I just realized that I didn't explicitly check if the whitening switches were pulled to ground to permanently turn on the whitenening, but hopefully I'll be able to see that in the photo. 

I have not made any changes today (yet) to the board, so the overall gain is still accessible via EPICS.  I wanted to do a quick check that we won't be saturating things at full power with the maximum gain, before I make a change.

EDIT:  After comparing the photos here and in elog 9854, the X end board has the filter shape modifications that were done some time ago, but the whitening is not permanently enabled.  For the Yend board, Koji added a jumper wire connecting (for example) R97 and R106 to the grounded side of C69.  This jumper wire is not in place on the X qpd board.

Before I re-pull the board and modify it, I want to make sure I know what I'm going to do for the gain slider override.

Here is a little PDF of what I plan to do to both of the transmission QPD whitening boards later today.  The idea is to take away the remote gain slider inputs, and force the gains to always be at +30dB.

The red and blue notes are from Koji's elog 9854, and the green are my plans for today. 

I will cut the traces from the gain slider inputs, and pull the negative input of the AD620 to ground.  The positive input will be connected to the +5 voltage line, with a divider so that the positive input to the AD620 is about 666mV. 

The AD602 will be maxed out at +30dB with anything over 625mV. 

Unless there are objections, I will start these modifications in an hour or so.  I will also make the Xarm whitening always-on, just like Koji has already done for the Yend.

EDIT, JCD, 12Dec2014:  These are not the modifications that were made.  Please see ____ for actual modifications.

Okay, I have finished modifying the Xend QPD whitening board, although I will likely need to change the gain on Monday.

Rather than following my plan in elog 10782, I removed the AD602's entirely, and just use the AD620's as the amplifiers.  We don't need remotely adjustable gains, and the AD620s are a less noisy part.

I set the gain to be 30dB using a 1.65k resistor for R_G, which turns out to be too high.  After I installed the board and realized that my counts were much higher than they used to be, I realized that what we had been calling +30dB was in fact +13.2dB. ( I am assuming that the ADC for the gain sliders were putting out a maximum of +10V.  The AD620 used to have a 1/10 voltage divider at the input, and an overall gain of 1, so the output of the AD620 was 100mV.  This goes into pin 16 of the AD602, which has gain of 32*V_set + 10.  Which gives 32*0.1+10=13.2dB.  Ooops.  We've been lying to ourselves. )

Anyhow, before I made the gain realization, I was happily going along, setting the AD620s' gains all to 30dB. I also copied Koji's modification from April of this year, and permanently enabled the whitening filters.

Here is the schematic of what ended up happening.  The red modifications were already in place, and the greens are what I did today.

You can see the "before" picture in my elog Wednesday, elog 10774.  Here is an "after" photo:

Here is a spectrum comparing the dark noise of the Xend QPD after modification to the current Yend QPD (which is still using the AD602 as the main instrumentation amplifier).  I have given the Yend data an extra 16.8dB to make things match.

And, here is a set of spectra comparing both ends, dark noise versus single arm lock.  While I'll have to sacrifice a lot of it, there's oodles more SNR in the Xend now.  The Yend data still has the "gain fixing" extra 16.8dB.

The Xend quadrant input counts (before the de-whitening filters) now go up to peak values of about 1,000 at single arm lock.  If (optimistically) the we got full power recycling and the arms got to powers of 300, that would mean we would have 300,000 counts, which is obviously way more than we actually have ADC range for.  Currently, the Yend quadrant input counts go as high as 50, which with arm powers of 300 would give 15,000 counts.  I think I need to bring the Xend gain down to about the level of the Yend, so that we don't saturate at full arm powers.  I can't remember right now - are the ends 14-bit or 16-bit ADCs?  If they're 16-bit, then I can set the gain somewhere between the current X and Y values.

 Finally, I added a section of the 40m's DCC document tree for the QPD whitening:  E1400473, with a page for each end.  Xend = D1400414, Yend = D1400415.

 16 bit. There aren't any 14-bit ADCs anywhere in LIGO. The aLIGO suspensions have 18-bit DACs.

The Y-End gains seem reasonable to me. I think that we only use TRX/Y as error signals once we have arm powers of >5 so we should consider if the SNR is good enough at that point; i.e. what would be the actual arm motion if we are limited only by the dark noise?

I seem to remember that the estimate for the ultimate arm power is ~200, considering that we have such high losses in the arms.

Details later - empty entry for a reply.

Short story - Yend is now same as Xend filters-wise and lack of gain sliders -wise.  Both ends have 13.7k resistors around the AD620 to give them gains of ~4.5.

Xend seems fine.

Yend seems not fine.  Even the dark noise spectrum sees giganto peaks.  See Diego's elog 10801 for details on this investigation.

 [Jenne, Rana, Diego]

We did some test on the modified QPD board for the Yend; we saw some weird oscillations at high frequencies, so we went and check more closely directly within the rack. The oscillations disappear when the cable from the QPD is disconnected, so it seems something is happening within the board itself; however, looking closely at the board with an oscilloscope in several locations, with the QPD cable connected or disconnected, there is nothing strange and definitely nothing changing if the cable is connected or not. In the plots there are the usual channels we monitor, and the 64kHz original channels before they are downsampled.

Overall it doesn't seem being a huge factor, as the RMS shows at high frequencies, maybe it could be some random noise coming up, but anyway this will be investigated further in the future.

Here's a summary of the changes made to the D990511 serial 115 (formerly known as REFL 33), as well as a short procedure. It needed tuning to 29.5MHz and also had some other issues that we found along the way. 

So here's a picture of it as built:

The changes made are:

1. U11 and U12 changed from 5MHz LP to 10 MHz LP filters.

2. Resistors R8 and R9 moved from their PCB locations to between pins 1 (signal) and 3 (ground) of U11 and U12, respectively. These were put in the wrong place for proper termination so it made sense to shift them while I was already replacing the filters.

Also, please note- whoever labeled the voltages on this board needed an extra cup of coffee that day. There are two separate 15V power supplies, one converted from 24V, one directly supplied. The directly supplied one is labeled 15A. This does NOT mean 15 AMPS.

Transfer functions:

Equipment: 4395A, Signal generator (29.5 MHz), two splitters, one mixer

You can't take the TF from PD in to I/Q out directly. Since this is a demod board, there's a demodulating (downconverting) mixer in the I and Q PD in paths. Negligible signal will get through without some signal applied to the L input of the mixer. In theory, this signal could be at DC, but there are blocking capacitors in the LO in paths. Therefore, you have to upconvert the signal you're using to probe the board's behavior before it hits the board.  Using the 4395A as a network analyzer, split the RF out. RFout1 goes to input R, RFout2 goes to the IF port of the mixer. Split the signal generator (SG). SG1 goes to LO in, SG2 goes to the L port of the mixer. The RF port of the mixer (your upconverted RFout2) goes to PD in, and the I/Q out goes back to the A/B port of the 4395A - at the same frequency as the input, thanks to the board's internal downconversion. 

Phase measurement:

Equipment: Signal generator (29.5 MHz), signal generator (29.501 MHz), oscilloscope

Much simpler: 29.5 MHz to the LO input (0 dBm), 29.501 MHz to the PD input (0 dBm), compare the phases of the I/Q outputs on the oscilloscope. There are four variable capacitors in the circuit that are not on the DCC revision of the board - C28-31. On the LO path, C28 tunes the I phase, C30 tunes the Q phase. On the PD path, C29 and 31 appear to be purely decorative - both are in parallel with each other on the PD in Q path, I'm guessing C29 was supposed to be on the PD in I path. Fortunately, C28 and C30 had enough dynamic range to tune the I/Q phase difference to 90 degrees.

Before tuning:

After tuning:

The RF amplifier panel on the IOO rack (Attachment 1) will be used to also hold the RF amplfiers for the frequency counters. The amplifiers mounted on it right now are getting +15 (orange wire) and GND (black wire) from the rack power supply (Attachment 2).

Proposed plan to install RF amplifiers:

1. Disconnect the D sub connector that powers the amplifiers and pull out the panel. The rack power supplies will NOT be shut down for this. 

2. Mount the RF amplifiers with bypass capacitors. There will be 4 amplifiers ZFL-500LN mounted on the same panel (2 for each frequency counter).

3. While putting back the panel on the IOO rack, we will need to shut down the +15V and -15V sources to connect the amplifiers to the rack power supply.

I will do this over this weekend so that we dont lose any locking time. If anybody has any concerns, let me know

I have re-enabled the second whitening stage switching on each quadrant of each end's QPD whitening board, to try and avoid saturations at full power. Looking at the spectra while single arm locked, I confirmed that the FM2 whitening switch works as expected. FM1 should be left on, as it is still hard-wired to whiten. 

The oscillations in the Y QPD still exist. Jenne is updating the schematics on the DCC.

Went to zero CARM offset on ALS; transmission QPDs are still saturating :(

Maybe we need to switch off all whitening.

I first updated the DCC branches for the Xend and Yend to reflect the as-built situation from December 2014, and then I updated the drawings after Q's modifications today.

Depends on the plots of the whitening I guess; if its low freq sat, then we lower the light level with ND filters. If its happening above 10 Hz, then we switch off the whitening.

X end QPD has recieved 0.2+0.4 absorptive ND filters. Y end QPD got one at 0.6. This appears to have mitigated the saturations for now; the unwhitened signals no longer go negative. The digital gains have been reset. 

Does anyone know where the Busby or Rai low noise pre-amp boxes are? 

I think I need one in order to measure the noise of the Marconi.  Right now, I am trying to measure the amplitude noise, but I'm not seeing anything on the SR785 above the analyzer's noise level.

The Rai box was in the Cryo lab, and the Busby box was in the TCS lab.  Neither had been signed out.  Lame.  Anyhow, thanks to Evan and Zach's memories of having seen them recently, they have been returned to the 40m where they belong.  (Also, I grabbed a spare Marconi while I was over there, for the phase noise measurement).

+1 to both Evan and Zach for prompt info and +2 to you for getting more stuff than you started looking for. -2 karma to whomever had swiped them and hoarded without signing. You should put a 40m sticker on both of them. Make sure to check / use fresh batteries. The Busby box is BJT based and works on low impedance sources, the Rai box works on anything, but (I am guessing) has less CMRR.

Just randomly found this old entry from 3 years ago. We should never have installed a GAP 2000 - they are an inferior type of InGaAs diode. We should add to our list replacing these with a 2 mm EG&G diode.

How many 2 mm EG&G InGaAs diodes do we have Steve? Can you please find a good clean diode case so that we can store them in the optics cabinet on the south arm?

RFpds box is moved from RF cabinet E4 to clean cabinet S15

Inventory updated at https://wiki-40m.ligo.caltech.edu/RF_Pd_Inventory

Large Area InGaAs PIN Photodiode -- C30642GH      6 pieces in stock

Large Area InGaAs PIN Photodiode with a 2,0 mm active diameter chip in TO-5 package with flat glass window

Large area InGaAs PIN photodiode with useful diameter of 2,0 mm in a T0-5 package with a flat glass window. The C30642GH provides high quantum efficiency from 800nm to 1700nm. It features high responsivity, high shunt resistance, low dark current, low capacitance for fast response time and uniformity within 2% across the detector active area.

I made a little box for the new RF amplifiers we'll be using for the green beatnotes, to keep things tidy on the PSL table. They are both Minicircuits model ZHL-3A-S.

I took TFs of their response with the agilient analyzer (calibrating out the cables, splitters, etc.) Powered at +24V, we get a solid ~27dB of gain up to around 200MHz, which is fine for our needs. The phase profile is mostly a 6-7 nsec delay, which is negligible for ALS. Data files are attached. 

Koji looked at me like I was crazy for using a BNC connector for the DC power. I haven't yet been able to find panel mount banana connectors, but when I do, I'll replace it. 

Banana'd:

As happened with the RF distribution box in the IOO rack a while back, the shiny blue power button in the LSC LO distribution box failed today. I replaced it with a simple switch, but since the original was a double throw, the replacement was way too big to fit without major panel surgery. So, instead, I installed it in the grille on the roof of the chassis. It a tight press/snap fit, though; I don't think it is at risk of easily coming loose. 

After reinstalling the box, I confirmed that POX POY and AS55 could all lock arms, so I deem the operation a success.

Before:

After:

I added the 0.1 uF and 47 nF caps that I mentioned so that we can now bypass the AA filters for these channels. (mistakenly installed 47 instead of 0.47 nF on the first round and we got 350 Hz poles instead of 35 kHz)

Gautam and I checked out the AA sit and it seems that the XYCOM-220 cable which ought to allow switching of the AA filter is not connected on the XYCOM side, so the LSC AA filters are always ON. In order to bypass them, we'll need to just short the bypass control pins or just set the +5V on the board to GND, by lifting the EMI3 filter and shorting C6.

I have so far only made the changes on s/n 115 (used for AS55, REFL55, and REFL165), other 2 boards to follow soon.

Before making the AA change, we want to measure the HF spectrum the ADC for each of our main signals in the PRFPMI state. In lieu of that, we'll measure the spectrum at the I/Q mon ports of the demod boards via SR785 and then use matlab to propagate the signals to the ADC to make our estimate of how much anti-aliasing we need.

Changes relative to D990694-B:

1. R215, R216, R217, R218, R219: 4.75k -> 9.53k.  This change was made long to make the DC gain of channels 4-8 be unity, the same as channels 1-3.
2. 0.1 uF NPO cap in parallel with R127, R128, R129, R130, R131, R132, R133, R134.
3. R127, R128, R129, R130, R131, R132, R133, R134 all 100k (was already like this) to keep LT1128 from floating up when input cables are disconnected.
4. C158, C159, C160, C161, C162, C163, C164, C165, C166, C167, C168, C169, C170, C171, C172, C173, all were empty, now are 0.47 nF NPO.

I also looked at the noise in a few different configurations to see what we ought to do next.

BLACK: AS55I_IN1 with 0 dB whitening gain and whitening filter OFF, so its all just ADC noise

RED: same but with +45 dB whitening gain and WF ON, so above 10 Hz this is now the noise of the PD / demod chain

BLUE: RED w/ the anti-WF applied

PURPLE: in-loop POX11_I spectrum with x-arm locked

The conversion from counts to volts 0.0006, so the black trace is ~5 uV/rHz as expected. Its clear that we would be sort of OK for most of our channels if we just had 1 stage of whitening. I think we ought to convert the input stage into a 100:20 stage and also change the other whitenings into a 100:20 instead of 150:15. Then we'll have less gain at 15 Hz, but more at 100 Hz.

We really need to buy some surface mount capacitors, Steve - we ought to have at least 100 of all the ones in that little gray cabinet.

At 1Y2 rack, I measured offset voltage of the common mode servo (D040180-B) with the gain of it varied.

For now, all signal cables that come into or go out of the common mode servo are not plugged.

I will upload the data I took and report the result later.

I report the results of the measurement to know how offset voltage of common mode servo changes when the gain is changed.

- Motivation: If discontinuous change of the offset happens when we change the gain, it could cause saturation somewhere and so make the length control down. So, we want to estimate effect of such discontinuous change.

- Method: In 1 (or In 2) was terminated with 50 ohm, and the output voltage at Out 2 was measured with a multimeter (D040180-B).

- Results are shown below. Acquired data are attached in .zip.

The upper shows input equiv. offset. The lower shows offset measured at Out 2.

As for both In1 and In2, strange behaviors can be seen between -17 dB and -16 dB.

This is because 5 amplifiers (or attenuators) are simultaneously enabled/disabled here. Similar situation occurs every change of 8 dB gain. 

Contacted Charles regarding use of Altium. Got to know that Altium is installed on cit40m iMac in Win7 on VirtualBox. Had to update Virtualbox to get it working. Altium now works for sometime, but then fails, saying that it is unlicensed.

I used a Eurocard extension board to peek at the inputs and outputs of each of the gain-ladder AD829s on input B of the CM board in the +31dB configuration with the input terminated. (i.e with the following stages active in this order: +16dB, +8dB, +4dB, +2dB, +1dB).

The voltages I observed imply that the +8dB stage has an input voltage offset of -2mV, whereas all the other positive gain stages show around +-0.5mV. This could explain the shift observed at the +15->+16 transition. (However, since both input channels show a jump here, maybe its something more systemic about the board...)

In any case, it should be simple enough to swap out a new AD829 in place of U9B and see if it improves things, before getting too deep into the muck. (In principle, the AD829 has offset nulling pins, but I'm not sure how to do it in a non-hacky way since the board doesn't have any pads for it.)

I replaced some of the AD829s with other AD829s, but the offset situation didn't improve.

However, I figured that we don't really need the ~100MHZ bandwidth of the AD829, since the IMC loop limits us to a ~10kHz CARM bandwidth. Also, since we don't routinely use IN2 for anything, I felt free to try something else. 

Specifically, I replaced all of the positive gain AD829s in the input 2 gain ladder with OP27s (U8B->U12B on D1500308), which should have input offset voltages ~30x lower than the AD829s. 

Here is a comparison of the outputs these configurations perform, normalized to the output at the +0dB gain setting - where all of the op amps in the gain ladder are bypassed. 

So, most of the transitions now result in an output offset change of less than 0.5mV, which is nice.

The exception seems to be where the +8dB stage is switched in or out. I may try replacing this one, as these transitions cause a lock loss now when trying to lock the arm with high bandwidth using POY.

Eric gave me a psd plot of a signal which would be the input of a channel of the AA filter. the Nyquist freq. is about 32.8kHz.

Following are plots depicting the ratio of the aliased downconverted signal and the signal below 32.8 kHz. The first plot is for (to-be) aliased signal frequencies from 32.8 to 65.5k, and the second plot is for (to-be) aliased signals from 65.5k to 98.3k. In case of the first plot, the 36kHz peak will alias to 29kHz, and is about 30 times (29.5dB) greater than the signal there. Hence, the filter should give about 70dB attenuation there. Since this attenuation is not required by most other frequencies up to 65.5k, an option could be to use a notch filter to remove the frequency peak at 36k, and put a requirement of 45-50 dB attenuation on other frequencies.

In case of the second plot, the frequencies between 90 to 100k again need to be attenuated by more than 70 dB. However, if there is a -20dB/decade slope in stop band, we already have about 10 dB attenuation here as compared to around 32k.

The X axis of both plots is in Hz.

Summary: The aim is to design an analog anti-aliasing (AA) filter placed before the ADC, whose function is to filter out components of the input spectrum that have frequencies higher than the Nyquist frequency. This needs to be done so that there is no contamination of aliased downconverted high-frequency signals into the ADC output. I have put down and simulated a circuit to do this, based on the spectra of a few interferometer signals that eric Provided. Attachment 1 shows such an input PSD, treated with whitening filter, before the AA. The sampling rate is 65536 Hz and hence the Nyquist freq. is 32768 Hz.

Motivation: Attachments 2 and 3 show the plot of required attenuation for various frequencies above the Nyquist. We can see a peak at 36 kHz, which will alias to about 29kHz. It will require about 70 dB attenuation here. This indicates that use of a notch filter combined with a low pass filter can be used.

Details of Schematic: Attachment 4 shows the schematic of a Boctor low pass notch filter, cascaded by a 2nd order LPF. The stopband frequency of the boctor filter can be tuned to around 36 kHz. Its main advantage for the boctor is better insensitivity to component value tolerances, use of a single op amp, and relatively independent tuning of parameters.  The various component values are calculated from here. The transfer functions for the circuit shown in attachment 4 were simulated using TINA - a spice based simulation software. The transfer function is shown in attachment 5.

A few more calculations: Attachment 6 shows the output psd after the signal has been treated with AA. Attachments 7 and 8 show the ratio of aliased downconverted signal and the unaliased signal of the output. Here, we can see that above about 13 kHz, the ratios go above -40dB, which is apparently undesirable. However, we also see from the transfer function of the filter that the gain falls to less than -20dB after about this frequency, and the aliased signals are atleast 20 dB lower than this, atleast upto about 29 kHz in attachment 7 and about 25 kHz in attachment 8. This means that the aliased signals are negligible as compared to the low frequencies even if they are not negligible as compared to the higher frequencies (above 13 kHz) into which they would get downconverted due to sampling. But these higher frequencies (above 13 kHz) themselves are small.

The filter overall, is 4th order. Considering this and the above discussion, I need to decide what changes to make in the existing schematic. For now, I could discuss with eric to finalize the opamp and start building the pcb board design.

I found an anti-aliasing circuit on the 40m wiki. It consists of A differential LPF made using THS4131 low noise differential op-amp (one of the main applications of which is preprocessing before the ADC), and a notch. I modified it to arrange for the desired bandwidth (about 8 kHz) and notch after the Nyquist frequency at 36 kHz. I simulated it to get the attached results:

Attachment 1: It shows the input PSD (same as the one posted in the previous elog), the filter transfer function, and The resulting output.

Attachment 2: The circuit schematic. The initial part using THS4131 is a differential LPF and the subsequent RC network is the notch.

Attachment 3: This shows the ratio of the aliased downconverted signal to the the in-band signal, representative of the contamination in each bin. Here too, the aliased signals are negligible as compared to the low frequencies but they are not negligible as compared to the higher frequencies (above 10 kHz) into which they would get downconverted due to sampling. However, here, the attenuation at 8kHz is less than 6 dB while in the previous circuit, it was about 12 dB. One problem with this circuit is at about 6kHz, there is aliased signal from the 65k to 98kHz band, but this can be taken care of by adding an LPF later.

There has been an ongoing memory error in optimus with the following messages:

controls@optimus|~ >
Message from syslogd@optimus at Jun 30 14:57:48 ...
 kernel:[1292439.705127] [Hardware Error]: Corrected error, no action required.

Message from syslogd@optimus at Jun 30 14:57:48 ...
 kernel:[1292439.705174] [Hardware Error]: CPU:24 (10:4:2) MC4_STATUS[Over|CE|MiscV|-|AddrV|CECC]: 0xdc04410032080a13

Message from syslogd@optimus at Jun 30 14:57:48 ...
 kernel:[1292439.705237] [Hardware Error]: MC4_ADDR: 0x0000001ad2bd06d0

Message from syslogd@optimus at Jun 30 14:57:48 ...
 kernel:[1292439.705264] [Hardware Error]: MC4 Error (node 6): DRAM ECC error detected on the NB.

Message from syslogd@optimus at Jun 30 14:57:48 ...
 kernel:[1292439.705323] [Hardware Error]: cache level: L3/GEN, mem/io: MEM, mem-tx: RD, part-proc: RES (no timeout)

Optimus is a Sun Fire X4600 M2 Split-Plane server. Based on this message, the issue seems to be in memory controller (MC) 6, chip set row (csrow) 7, channel 0. I got this same result again after installing edac-utils and running edac-util -v, which gave me:

mc6: csrow7: mc#6csrow#7channel#0: 287 Corrected Errors 

and said that all other DIMMs were working fine with 0 errors. Each MC has 4 csrows numbered 4-7. I shut off optimus and checked inside and found that it consists of 8 CPU slots lined up horizontally, each with 4 DIMMs stacked vertically and 4 empty DIMM slots beneath. I'm thinking that each of the 8 CPU slots has its own memory controller (0-7) and that the csrow corresponds to the position in the vertical stack, with csrow 7 being the topmost DIMM in the stack. This would mean that MC 6, csrow 7 would be the 7th memory controller, topmost DIMM. The channel would then correspond to which one of the DIMMs in the pair is faulty although if the DIMM was replaced, both channels 0 and 1 would be switched out. Here are some sources that I used:

http://docs.oracle.com/cd/E19121-01/sf.x4600/819-4342-18/html/z40007f01291423.html#i1287456

https://siliconmechanics.zendesk.com/hc/en-us/articles/208891966-Identify-Bad-DIMM-from-EDAC

http://martinstumpf.com/how-to-diagnose-memory-errors-on-amd-x86_64-using-edac/

I'll find the exact part needed to replace soon.

I am trying to design an antialiasing filter, which also has two switchable whitening stages. I have designed a first version of a PCB for this.

The board takes differential input through PCB mountable BNCs. It consists of an instrumentaiton amplifier made using quad opamp ADA4004, followed by two whitening blocks, also made using ADA4004, which can be bypassed if needed, depending upon a control input. The mux used for this purpose is Maxim MAX4158EUA. These two whitening blocks are followed by 2 the LPF stages. A third LPF stage could be added if needed. These use AD829 opamps. After the LPFs are two amplifiers for giving a differential output through two output BNCs. The schematic is shown in attachment 1: "AA.pdf". The top layers of the layout are shown in attachment 2 (AAtop.pdf), the bottom layers in attachment 3 (AAbottom.pdf), and the entire layout in attachment 4 (AAbrd.pdf). 

The board has 6 layers (in the order from top to bottom):

1) Top signal layer; 

2) Internal plane 1 (GND),

3) Internal plane 2 (+15V),

4) Internal plane 3 (-15V),

5) Internal plane 4 (GND),

6) Bottom signal layer. 

Power: +15, -15 and GND is given through a 4 pin header connector. 

The dimensions of the board are 1550 mil  6115 mil (38.1mm155.3mm) and the overall dimensions including the protruding BNC edges are 1550 mil  7675 mil (38.1mm194.9mm)

I would like to have inputs on the layout telling me if any component/trace needs to be changed/better placed, any other things about the board need to be changed, etc.

P.S.: I have also added a zipped folder "AA.zip" containing the schematic and board files, as well as the above pdfs.

Optimus' memory errors are back so I found the exact DIMM model needed to replace: http://www.ebay.com/itm/Lot-of-10-Samsung-4GB-2Rx4-PC2-5300P-555-12-L0-M393T5160QZA-CE6-ECC-Memory-/201604698112?hash=item2ef0939000:g:EgEAAOSwqBJXWFZh I'm not sure what website would be the best for buying new DIMMs but this is the part we need: Samsung 4GB 2Rx4 PC2-5300P-555-12-L0 M393T5160QZA-CE6.

Comments on the schematic:

1. Only the instrumentation amp should be made up of the ADA4004. Not the whitening parts.
2. Please think about the front panel design and make a drawing of the front and back panels. Power connectors, indicators, switches, etc. Take a look at some of our existing 1U rack electronics to see what standard arrangements are. Add a front and back panel drawing to the elog.
3. The whitening and anti-aliasing opamps can all be OP27 SOIC-8 for now. Later, if we need better noise performance or speed we can use faster opamps.
4. There should be a 3rd stage of AA. Each of the exisitng stages (U5, U6) can only be second order and we want the option to have a 6th order low pass.
5. There should be 100 nF decoupling capacitors on the power pins of all the single opamps.
6. There is a low noise power daugther board made by Ben Abbott which you can use on the DCC. It should accept the direct power connector from the back panel and supply regulated power to the board.
7. Take care to update the lower right hand corner info box with updated drawing version #'s and author name.
8. The MAX4158 is 16 years old. It may be good if you can find a newer parts so it doesn't go obsolete.
9. All of the R & C on the board should be sized 1206 for the SMD.
10. For the whitening and AA filtering stages, we want the capability to use larger size parts (e.g. the red WIMA caps that are in the blue spinny box). So you will have to use larger footprints for those.
11. The resistors should all be 0.1% thin film or metal film.

I recreated Den's microphone amplifier circuit on a solderless breadboard to test it and make sure it does what it's supposed to. So far it seems like everything is working- I'll do some testing tomorrow to see what the amplified output is like for some test noises. Here's the circuit diagram that Den made (his elog as well https://nodus.ligo.caltech.edu:8081/40m/6651):

I'm not sure why he set up the circuit the way he did- he has pin 7 grounded and pin 4 going to +12V while in the datasheet for the opamp (http://cds.linear.com/docs/en/datasheet/1677fa.pdf), pin 7 goes to positive voltage and pin 4 goes to negative voltage. There's some other strange things about the circuit that I don't really understand, such as the motivation for using no negative voltage source, but for now I'm going to stick with Den's design and then make some modifications after I have things working and a better understanding of the problem.

Here's my current plan:

-Make sure Den's amplifier works, test it out and make changes if necessary

-Make multiple amplifier circuits on soldering breadboard

-Either make a new amplifier box or reuse Den's old box depending on how many changes I make to the original circuit

-Solder EM172s to BNC connectors, set them up around the floor suspended

-Get the amplifier box hooked up, set up some data channels for the acoustic noise

-Add new acoustic noise tab to the summary pages

Den also mentioned that he wanted me to measure the coupling of acoustic noise to DARM.

I set up a test inverting amplifier circuit using the LT1677 opamp:

The input signal was a sine wave from the function generator with peak to peak amplitude of 20 mV and a frequency of 500 Hz and I received an output with an amplitude of about 670 mV and the same 500 Hz frequency, agreeing with the expected gain of -332k/10k = -33.2:

So now I know that the LT1677 works as expected with a negative supply voltage. My issue with Den's original circuit is that I was getting some clipping on the input to pin 2, which didn't seem to be due to any of the capacitors- I switched them all out. I set up a modified version of Den's circuit using a negative voltage input to see if I could fix this clipping issue:

I might reduce the input voltages to +5V and -5V- I couldn't get my inverting amp circuit to work with +12V and -12V. I'll start testing this new circuit next week and start setting up some amplifier boxes.

I could not get Den's circuit to work for some reason with microphone input, so I decided to try to use another circuit I found online. I made some modifications to this circuit and made a schematic:

Using this circuit, I have been able to amplify microphone input and adjust my passband. Currently, this circuit has a high-pass at about 7 Hz and a low-pass at about 23 kHz. I tested the microphone using Audacity, an audio testing program. I produced various sine waves at different frequencies using this program and confirmed that my passband was working as intended. I also used a function generator to ensure that the gain fell off at the cutoff frequencies. Finally, I measured the frequency response of my amplifier circuit:

ampTest_03-08-2016_180448.pdf

A text file with the parameters of my frequency response and the raw data is attached as well.

These results are encouraging but I wanted to get some feedback on this new circuit before continuing. This circuit seems to do everything that Den's circuit did but in this case I have a better understanding of the functions of the circuit elements and it is slightly simpler.

I took the spectrum of an EM172 connected to my amplifier inside and outside a large box filled with foam layers:

I also made a diagram with my plan for the microphone amplifier boxes. This is a bottom view:

The dimensions I got from this box: http://www.digikey.com/product-detail/en/bud-industries/CU-4472/377-1476-ND/696705

This seemed like the size I was looking for and it has a mounting flange that could make suspending it easier. Let me know if you have any suggestions.

I'll be doing a Huddle test next week to get a better idea of the noise floor and well as starting construction of the circuits to go inside the boxes and the boxes themselves.
 

I set up 3 of my circuits in the interferometer near MC2 to do a huddle test. I have the signals from my microphones going into C1:PEM-MIC_1_IN1, C1:PEM-MIC_2_IN1, and C1:PEM-MIC_3_IN1. These are channels C17-C19. Here are some pictures of my setup:

I'll likely be collecting data from this for a couple of hours. Please don't touch it for now- it should be gone soon. There are some wires running along the floor near MC2 as well.

In order to help Praful do his huddle test, I have temporarily arranged for the outputs of the 3 channels he wants to monitor to be acquired as DQ channels at 2048 Hz by editing the C1PEM model. No prior DQ channels were set up for the microphones. Data collected overnight should be sufficient for Praful's analysis, so we can remove these DQ channels from C1PEM before committing the updated model to the svn. There is in fact a filter that is enabled for these microphone channels that claims to convert the amplified microphone output to Pascals, but it is just a gain of 0.0005. 

In the long term, once we install microphones around the IFO, we can update C1PEM to reflect the naming conventions for the microphones as is appropriate.

The results of my first huddle test were not so good- one of the signals did not match the other two very well- so I changed the setup so that the mics would be better oriented to receive the same signal. Pictures of the new setup are attached.

I also noticed some problems with one of my microphones so I soldered a new mic to bnc and switched it out. Just judging from Dataviewer, the signals seem to be more similar now. I'll be taking data for another few hours to confirm.

I used the Wiener filtering method described by Ignacio and Jessica (https://dcc.ligo.org/DocDB/0119/T1500195/002/SURF_Final.pdf and https://dcc.ligo.org/public/0119/T1500194/001/Final_Report.pdf) and got the following results:

mic1_wiener.pdf

mic2_wiener.pdf

mic3_wiener.pdf

The channel readout has a gain of 0.0005 and the ADC is 16-bit and operates are 20V. The channel also reads the data out in Pa. I therefore had to multiply the timeseries by 1/0.0005=2000 to get it in units of counts and then by (20 Volts)/(2^16 counts) to get back to the original signal in volts. The PSDs were generated after doing this calibration. I also squared, integrated, and square rooted the PSDs to get an RMS voltage for each microphone as a sanity check:

Mic 1: 0.00036 V

Mic 2: 0.00023 V

Mic 3: 0.00028 V

These values seem reasonable given that the timeseries look like this:

timeseries_elog.pdf