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ID Date Author Type Category Subject
13645   Wed Feb 21 00:04:27 2018 gautamUpdateElectronicsTemporary RF power monitor setup

I made a voltage divider using a 20.47kohm and 1.07kohm (both values measured with a DMM). The whole thing is packaged inside a Pomona box I found lying around on the Electronics bench. I have hooked it up to the ALSY_I channel and will leave it so overnight. The INMON of this channel isn't DQed, but for this test, the 16Hz EPICS data will suffice. I've locked the EX laser to the arm, enabled slow temperature servo to allow overnight lock (hopefully) and disabled LSC mode (as locking the arm to the MC tends to break the green lock)

To convert the INMON counts to RF power, I will use (based on my earlier calibration of this monitor channel, see DCC document for the demod chassis).

$\mathrm{P_{RF}} (\mathrm{dBm}) = \frac{19.13 \times \frac{cts}{1638.4} - 10.23}{0.12}$

1AM update: Attachment #1 shows that the RF amplitude has been relatively stable (less than 10% of nominal value variation) over the course of the last hour or so. Even though there is some low frequency drift over timescales of ~20mins, no evidence of the wild ~20dB amplitude changes I saw last week. The signs are encouraging...

overnight update: See Attachment #2 - looking at the past 11 hours of second trend data during which the arm stayed locked, there actually seems to have been more significant variation in the beatnote amplitude. Swings of up to 6dBm are seen on a ~20min timescale, while there is also some longer term drift over 12 hours by a couple of dBm. There is probably a systematic error in the Y-axis, as I measured the RF power at the input of the power splitter at the LSC rack to be ~3dBm, so I expect something closer to 0dBm to be the LO input power which is what I am monitoring. So further debugging is required - I think I'll start by aligning the X fiber coupled beam to one of the fiber's special axes.

Attachment 1: RFbeatAmp.png
Attachment 2: BeatMouthX_RFAM_20180221.pdf
13649   Thu Feb 22 10:49:11 2018 SteveUpdateElectronicsrack power supplies checked

All rack power supplies labeled if their load changed.

Attachment 1: 1X1_DC.jpg
Attachment 2: 1X5_DC.jpg
Attachment 3: 1X9_DC.jpg
Attachment 4: 1X8_DC.jpg
Attachment 5: 1Y2_DC.jpg
Attachment 6: 1Y1_DC.jpg
Attachment 7: AUX_1Y2_DC.jpg
Attachment 8: AUX_OMC_DC.jpg
13665   Mon Mar 5 11:58:24 2018 gautamUpdateElectronicsThree opamps walked onto an AA board

For testing the new IR ALS noise, we had decided that we would like to use the differential output of the demodulated ALS beat signal, as opposed to a single-ended output, as measurements suggested the former to be a lower noise configuration than the latter. For this purpose, Koji and I acquired a couple of old AA boards from the WB electronics shop. These are however, rev2 of the board, whereas the latest version is v6. The main difference between v2 and v6 is that (i) the THS4131 instrumentation amplifier has the Vocm pin grounded in v6 but is floating in v2 and (ii) the buffer opamps are AD8622 in v6 but are AD8672 in v2. But in fact, the boards we have are stuffed with AD8682

I talked to Rich on Friday, and he seemed to think the AD8672 didn't have any issues noise-wise, the main reason they changed it was because its power consumption was high, and was causing overheating when several of these 1U chassis were packed closely together in an electronics rack. But the AD8682, which is what we have, has comparable power consumption to the AD8622. It is however a JFET opamp, and the voltage noise is a bit higher than the AD8622.

I am sure there is a way to LISO model a differential output opamp like the THS4131, but I thought I'd simulate the noise in LTSPICE instead. But I couldn't get that to work. So instead, I just measured the transfer function and noise of a single channel, for which Koji had expertly hacked together a custom shorting of the THS4131 Vocm pin to ground. Attachments #1 and #2 show the measurement. All looks good. Note that the phase is 180 at DC because I had hooked up the input signal opposite to what it should have been. The voltage noise of the differential outputs (each measured w.r.t. ground, with both inputs shorted to ground by a short patch cable) at 10 Hz is <100nV/rtHz, and the ADC noise is expected to be ~1uV/rtHz, so I think this is fine.

Conclusion: I think for the ALS test, we can just use the AA board in this config without worrying too much about replacing the buffer stage opamps, even though we've ordered 100pcs of AD8622.

Addendum 7 Mar 2018 11am: As per this document, the output noise of the AA board should be <75nV/rtHz from 10 Hz-50 kHz. So maybe the AD8682 noise is a little high after all. I've gotten the LTSpice model working now, will post the comparison of modelled output noise for various combinations here shortly.

Attachment 1: AA_TF.pdf
Attachment 2: AA_noise.pdf
13667   Wed Mar 7 12:04:14 2018 gautamUpdateElectronicsThree opamps walked onto an AA board

1. Measurement and model agree quite well .
2. Of the 3 OpAmps, the ones installed seem to be the noisiest (per model)
3. Despite #2, I don't think it is critical to replace the buffer opamps as we only win by ~10nV/rtHz in the 300-10kHz range.
4. I don't understand the spec given in T070146. It says the noise everywhere between 10Hz-50kHz should be <75nV/rtHz. But even the model suggests that at 10Hz, the noise is ~250nV/rtHz for any choice of buffer opamp, so that's a factor of 3 difference which seems large. Maybe I made a mistake in the model but the agreement between measurement and model for the AD8682 choice gives me confidence in the simulation. LTSpice files used are in Attachment #3. Could also be an artefact of the way I made the measurement - between an output and ground instead of differentially...

I like LTspice for such modeling - the GUI is nice to have (though I personally think that typing out a nodal file a la LISO is faster), and compared to LISO, I think that the LTspice infrastructure is a bit more versatile in terms of effects that can be modeled. We can also easily download SPICE models for OpAmps from manufacturers and simply add them to the library, rather than manually type out parameters in opamp.lib for LISO. But the version available for Mac is somewhat pared down in terms of the UI, so I had to struggle a bit to find the correct syntax for the various simulation commands. The format of the exported data is also not as amenable to python plotting as LISO output files, but i'm nitpicking...

 Quote: I've gotten the LTSpice model working now, will post the comparison of modelled output noise for various combinations here shortly.

Attachment 1: AA_TF.pdf
Attachment 2: AA_noise.pdf
Attachment 3: D070081_LTspiceFiles.zip
13671   Thu Mar 8 15:23:16 2018 gautamUpdateElectronicsNew DC power ports at c1lsc

[Koji, Gautam]

Yesterday, we installed some new DIN rail connectors at the LSC rack to provide 3 new outputs each for +24V DC and -24V DC. The main motivation was to facilitate the installation and powering of the differential receiving AA board. The regulators used inside the 1U chassis actually claims a dropout voltage of 0.5V and outputs 14V nominally, so a +/-15V DC supply would've perhaps been sufficient, but we decided to leave a bit more margin, and unfortunately, there are no +/-18V DC KEPCO linear power supplies to the LSC rack. Procedure:

1. Prepared a bunch of DIN rail connectors with tinned, daisy-chained wires in the office area. Checked continuity and isolation with DMM.
2. Checked that the two Sorensens at the bottom of the LSC rack were powering the RF distribution box and nothing else at the LSC rack.
3. Walked over to the little rack housing all the KEPCO DC power supplies that supply DC voltages to the LSC rack. After checking that the labelled voltage and current values were correct, we turned them off, first +/-5V, then +/-15V (2 sets), and finally +/-24V.
4. Installed the pre-assembled DIN connectors on the side rail at the LSC rack (we had to remove the side panel for the rack to do this work).
• We used the ports supplying power to the ALS 1U demod chassis (+/-24V DC) to tap these voltages to our newly installed connectors.
• The interconnecting wires are rather thick gauge, and especially for the ground wire, we found it impossible to push in our tap-off wire into the "correct/hot" side of the DIN blocks. So we had to use the other side instead. I'll upload a picture shortly which will make this more clear.
• Checked continuity and isolation with DMM.
• Turned the KEPCOs back on in reverse order to how they were turned off.
• Measured voltages on the hot side of the DIN blocks, confirmed that they were as expected.
5. Prepared a 12AWG aLIGO style power cable to connect to the 1U chassis. A reel of this cabling, with yellow shielding, is located ~halfway along under the EW arm. Koji prepared the actual connector and housed it in a DSUB shell as per aLIGO wiring color scheme.
6. Installed the power cabling to one set of our 3 newly installed +/-24V DC power supplies.
7. Inserted fuses into the hot DIN blocks, measured voltage at connector end of our newly installed power cable. At first, I forgot to check if the fuse blocks had fuses inside, but after this was rectified, voltages were as expected .

The c1lsc frontend models crashed for some reason during this procedure. Now the c1sus frontend model is also behaving weirdly. It is unclear to me if/how this work would have led to these problems, but the temporal correlation (but not causation?) is undeniable.

13802   Tue May 1 08:04:13 2018 Jon RichardsonConfigurationElectronicsPSL-Aux. Laser Phase-Locked Loop

[Jon, Gautam, Johannes]

Summary: In support of making a proof-of-concept RF measurement of the SRC Gouy phase, we've implemented a PLL of the aux. 700mW NPRO laser frequency to the PSL. The lock was demonstrated to hold for minutes time scales, at which point the slow (currently uncontrolled) thermal drift of the aux. laser appears to exceed the PZT dynamic range. New (temporary) hardware is set up on an analyzer cart beside the PSL launch table.

Next steps:

- Characterize PLL stability and noise performance (transfer functions).

- Align and mode-match aux. beam from the AS table into the interferometer.

- With the IFO locked in a signal-recycled Michelson configuration, inject broadband (swept) AM sidebands via the aux. laser AOM. Coherently measure the reflection of the driven AM from the SRC.

- Experiment with methods of creating higher-order modes (partially occluding the beam vs. misaligning into, e.g., the output Faraday isolator). The goal is identify a viable techinque that is also possible at the sites, where the squeezer laser serves as the aux. laser.

The full measurement idea is sketched in the attached PDF.

Attachment 1: IMG_2553.jpg
Attachment 4: src_gouy_phase_v3.pdf
13813   Thu May 3 20:29:39 2018 gautamConfigurationElectronicsPSL-Aux. Laser Phase-Locked Loop

Some notes about the setup and work at the PSL table today, Jon can add to / correct me.

• All equipment for the phase locking now sit on a cart that is on the west side of the MC beam tube, near ITMX chamber.
• Cables have been routed through the space between the PSL enclosure and the optical table.
• HEPA was turned up for this work, now it has been turned down to the nominal level of 30%.
• Alignment into the PMC had degraded a bit - I tweaked it and now MC transmission is up at ~15600 which is a number I am used to. We still don't have a PMC transmission monitor since the slow ADC failure.
13814   Fri May 4 13:24:56 2018 Jon RichardsonConfigurationElectronicsAUX-PSL PLL Implementation & Characterization

Attached are final details of the phase-locked loop (PLL) implementation we'll use for slaving the AUX 700 mW NPRO laser to the PSL.

The first image is a schematic of the electronics used to create the analog loop. They are curently housed on an analyzer cart beside the PSL table. If this setup is made permanent, we will move them to a location inside the PSL table enclosure.

The second image is the measured transfer function of the closed loop. It achieves approximately 20 dB of noise suppression at low frequencies, with a UGF of 50 kHz. In this configuration, locks were observed to hold for 10s of minutes.

Attachment 1: PLL_Schematic.pdf
Attachment 2: PLL_AUX-PSL_40m.pdf
13816   Fri May 4 19:06:28 2018 ranaConfigurationElectronicsAUX-PSL PLL Implementation & Characterization

this doesn't make much sense to me; the phase to frequency conversion (mixer-demod to PZT ) should give us a 1/f loop as Johannes mentioned in the meeting. That doesn't agree with your loop shape.

How about give us some more details of the setup including photos and signal/power levels? And maybe measure the LB1005 TF by itself to find out what's wrong with the loop.

13845   Tue May 15 20:51:27 2018 gautamConfigurationElectronicsMaking PLL setup more permanent

[jon, steve, gautam]

Some points which Jon will elaborate upon (and put photos of) in his detailed elog about this setup:

• PLL electronics (mixer, coupler, ZFL500HLN amplifier and DC power supply for the beatnote, SR560 servo) all reside on the newly installed lower level PSL shelf.
• Cross connect channel C1:PSL-126MOPA_126CURADJ hijacked for remote temperature control of the AUX NPRO. Note that shield of front panel BNC is ground and so even though the manual says the controller accepts +/-10V, this is not a differential input. BNC cable was routed from cross connect to PSL enclosure, MEDM slider will be setup.
• There was an SMA cable running from the VEA to the control room which we decided to use for monitoring of the beatnote amplitude on the control room analyzer. Yesterday, Steve and I routed the end of this inside the VEA, near 1X2 originally, to inside the PSL table where it is hooked up to the (20dB) coupled amplifier output. This required some work on the cable tray, we were careful but in case there is some wonkiness in some signals, perhaps this work is to blame.

We are now in a state where the PLL can be locked remotely from the control room by tweaking the AUX laser temperature . Tomorrow, Keerthana will work on getting Craig's/Johannes' Digital Frequency Counter script working here, I think we can easily implement a PLL autolocker if we have some diagostic that tells us if the PLL us locked or not.

Steve informed me that there is an acoustic hum inside the PSL enclosure which wasn't there before. Indeed, it is at ~295Hz, and is from the Bench power supply used to power the ZFL500HLN amplifier. This will have to go...

13848   Wed May 16 18:52:50 2018 gautamConfigurationElectronicsPLL mysteries solved

[Koji, Gautam]

Summary:

As I suspected, when the SR560 is operated in 1 Hz, first order LPF mode, the (electronic) transfer function has a zero at ~5kHz (!!!).

Details:

This is what allowed the PLL to be locked with this setting with UGF of ~30kHz. On the evidence of Attachment #3, there is also some flattening of the electrical TF at low frequencies when the SR560 is driving the NPRO PZT. I'm pretty sure the flattening is not a data download error but since this issue needs further investigation anyway, I'm not reading too much into it. I fit the model with LISO but since we don't have low frequency (~1Hz) data, the fit isn't great, so I'm excluding it from the plots.

We also did some PLL loop characterization. We decided that the higher output range (10Vp bs 10Vpp for the SR560) of the LB1005 controller means it is a better option for the PLL. The lock state can also be triggered remotely. It was locked with UGF ~ 60kHz, PM ~45deg.

We also measured the actuation coefficient of the NPRO laser PZT to be 4.89 +/- 0.02 MHz/V. Quoted error is (1-sigma) from the fit of the linear part of the measured transfer function to a single pole at DC with unknown gain. I used the "clean" part of the measurement that extends to lower frequencies for the fit, as can be seen from the residuals plot. Good to know that even though the LDs are dying, the PZT is still going strong :D.

Remaining loop characterization (i.e. verification of correct scaling of in loop suppression with loop gain etc.) is left to Jon.

Measurement schemes:

1. OLG (Attachment #1) was measured using the usual IN1/IN2 technique.
2. PZT calibration (Attachment #2) was measured by injecting an excitation at the PLL control point.
• The ratio of the PLL error point (Volts) to Excitation (Volts) was measured using the SR785.
• The error point was calibrated by looking at the PLL open loop Vpp (corresponds to pi radians of phase shift).
• Dividing the fitted gain of the phase->Frequency conversion by the error point calibration, we get the PZT actuation coefficient.

Some other remarks:

1. In the swept-sine mode, the SR785 measures transfer functions by taking the ratio of complex FFT values of its inputs at the drive frequency. So the phase in particular is a good indicator of whether the measurement is coherent or not.
2. In all these measurements, the PLL gain is huge at low frequencies, and hence, the excitation is completely squished on propagating through the loop. E.g. a 10mV excitation is suppressed by a factor of ~60dB = 1000 to 10uV, and if the analyzer autoRange is set to UpOnly, it is easy to see how this is drowned at the IN1 input. This is why the measurements lose coherence below ~1 kHz.
3. It is easy to imagine implementing an EPICS servo that offloads the DC part of the LB box control signal to the SLOW frequency input on the Lightwave controller. This would presumably allow us to extend the lock timescales. We can also easily implement a PLL autolocker.
4. Preliminary investigation of the SR560 situation suggests that individual filter stages can only achieve a maximum stopband attenuation of 60dB relative to the passband. When we cascade two stages together, 120dB seems possible...
Attachment 1: PLLanalysis.pdf
Attachment 2: PZTcal.pdf
Attachment 3: SR560_funkiness.pdf
13858   Thu May 17 13:51:35 2018 Jon RichardsonConfigurationElectronicsDocumentation & Schematics for AUX-PSL PLL

[Jon, Gautam]

Attached is supporting documentation for the AUX-PSL PLL electronics installed in the lower PSL shelf, as referenced in #13845.

Some initial loop measurements by Gautam and Koji (#13848) compare the performance of the LB1005 vs. an SR560 as the controller, and find the LB1005 to be advantageous (a higher UGF and phase margin). I have some additional measurements which I'll post separately.

## Loop Design

Pickoffs of the AUX and PSL beams are routed onto a broadband-sensitive New Focus 1811 PD. The AUX laser temperature is tuned to place the optical beat note of the two fields near 50 MHz. The RF beat note is sensed by the AC-coupled PD channel, amplified, and mixed-down with a 50 MHz RF source to obtain a DC error signal. The down-converted term is isolated via a 1.9-MHz low-pass filter in parallel with a 50 Ohm resistor and fed into a Newport LB1005 proportional-integral (PI) servo controller. Controller settings are documented in the below schematic. The resulting control signal is fed back into the fast PZT actuator input of the AUX laser.

## Hardware Photos

13863   Fri May 18 14:18:03 2018 gautamConfigurationElectronicsBasic MEDM Control Screen setup

I setup a basic MEDM screen for remote control of the PLL.

The Slow control voltage slider allows the frequency of the laser to be moved around via the front panel slow control BNC.

The TTL signal slider provides 0/5V to allow triggering of the servo. Eventually this functionality will be transferred to the buttons (which do not work for now).

The screen can be accessed from the PSL dropdown menu in sitemap. We can make this better eventually, but this should suffice for initial setup.

Attachment 1: AUX_PLL_CTRL.png
13867   Fri May 18 19:59:55 2018 Jon RichardsonConfigurationElectronicsAUX-PSL PLL Characterization Measurements

Below is analysis of measurements I had taken of the AUX-PSL PLL using an SR560 as the servo controller (1 Hz single-pole low-pass, gain varied 100-500). The resulting transfer function is in good agreement with that found by Gautam and Koji (#13848). The optimal gain is found to be 200, which places the UGF at 15 kHz with a 45 deg phase margin.

For now I have reverted the PLL to use the SR560 instead of the LB1005. The issue with the LB1005 is that the TTL input for remote control only "freezes" the integrator, but does not actually reset it. This is fine if the lock is disabled in a controlled way (i.e., via the medm interface). However, if the lock is lost uncontrollably, the integrator is stuck in a garbage state that prevents re-locking. The only way to reset this integrator is to manually flip a switch on the controller box (no remote reset). Rana suggests we might be able to find a workaround using a remote-controlled relay before the controller.

Attachment 1: SR560_OL.pdf
Attachment 2: SR560_CL.pdf
13869   Sun May 20 17:43:01 2018 ranaUpdateElectronicsHow to choose resistors

Article from EE Times, describing why metal foil (NOT metal film) resistors are really better than wirewound when it comes to everything except high power dissipation.

Need to do some diggin to see if we can find ~1k metal foil resistors which can handle ~1W of heat.

Steve: here it is

13873   Mon May 21 15:34:19 2018 gautamConfigurationElectronicsChannel hijacking history

Since we've been hijacking channels like there is no tomorrow for the AUX-PLL setup, I'm documenting the channel names here. The next time c1psl requires a reboot, I'll rename these channels to something more sensible. To find the channel mapping, Koji suggested I use this. Has worked well for us so far... We've labelled all pairs of wires pulled out of the cross connects and insulation taped the stripped ends, in case we ever need to go back to the original config.

### Previously unused C1PSL Channels now used for AUX PLL

Channel name AI/AO Function
C1:PSL-126MOPA_126PWR AI PLL error signal monitor
C1:PSL-126MOPA_DMON AI PLL control signal monitor
C1:PSL-FSS_PHCON AO

To mitigate integrator railing

13876   Tue May 22 10:14:39 2018 Jon RichardsonConfigurationElectronicsDocumentation & Schematics for AUX-PSL PLL

Quote:

[Jon, Gautam]

Attached is supporting documentation for the AUX-PSL PLL electronics installed in the lower PSL shelf, as referenced in #13845.

Some initial loop measurements by Gautam and Koji (#13848) compare the performance of the LB1005 vs. an SR560 as the controller, and find the LB1005 to be advantageous (a higher UGF and phase margin). I have some additional measurements which I'll post separately.

## Loop Design

Pickoffs of the AUX and PSL beams are routed onto a broadband-sensitive New Focus 1811 PD. The AUX laser temperature is tuned to place the optical beat note of the two fields near 50 MHz. The RF beat note is sensed by the AC-coupled PD channel, amplified, and mixed-down with a 50 MHz RF source to obtain a DC error signal. The down-converted term is isolated via a 1.9-MHz low-pass filter in parallel with a 50 Ohm resistor and fed into a Newport LB1005 proportional-integral (PI) servo controller. Controller settings are documented in the below schematic. The resulting control signal is fed back into the fast PZT actuator input of the AUX laser.

## Hardware Photos

Attachment 1: Schematic_PLL.pdf
13891   Fri May 25 13:06:33 2018 Jon RichardsonConfigurationElectronicsImproved Measurements of AUX-PSL PLL

Attached are gain-variation measurements of the final, in situ AUX-to-PSL phase-locked loop (PLL).

Attachment 1: Figure of open-loop transfer function

Attachment 2: Raw network analyzer data

The figure shows the open-loop transfer function measured at several gain settings of the LB1005 PI servo controller. The shaded regions denote the 1-sigma sample variance inferred from 10 sweeps per gain setting. This analysis supercedes previous posts as it reflects the final loop architecture, which was slightly modified (now has a 90 dB low-frequency gain limit) as a workaround to make the LB1005 remotely operable. The measurements are also extended from 100 kHz to 1 MHz to resolve the PZT resonances of the AUX laser.

Conclusions:

• Gain variation confirms response linearity.
• At least two PZT resonances above the UGF are not far below unity (150 kHz and 500 kHz).
• Recommend to lower the proportional gain by 3 dB. This will place the UGF at 30 kHz with 55 degrees of phase.
Attachment 1: LB1005_OL_transfer.pdf
Attachment 2: data.tar.gz
13998   Thu Jun 21 15:32:05 2018 gautamUpdateElectronicsEX AA filter range change

[steve, gautam]

I took this opportunity of EX downtime to change the supply voltage for the AA unit (4-pin LEMO front panel) in 1X9 from +/-5V to +/-15V. Inside the AA board are INA134 and DRV135 ICs, which are rated to work at +/-18V. In the previous state, the inputs would saturate if driven with a 2.5Vpp sine wave from a DS345 func. gen. After the change, I was able to drive the full range of the DS345 (10Vpp), and there was no saturation seen. This AA chassis is only used for the OSEM signals and also some ALS signals. Shadow sensor levels and spectra are consistent before and after the change. The main motivation was to not saturate the Green PDH Reflection signal in the digital readout. The steps we took were:

1. Confirm (by disconnecting the power cable at the back of the AA box) that the power supplied was indeed +/- 5 V.
2. Remove DIN fuse blocks from DIN rail for the relevant blocks.
3. Identify a +15 V, -15 V and GND spot to plug the wires in.
4. Effect the swap.
5. Re-insert fuses, checked supply voltage at connector end of the cable was now +/- 15 V as expected.
6. Re-connect power cable to AA box.
14024   Wed Jun 27 18:12:04 2018 gautamUpdateElectronicsCoil driver dewhitening

Summary:

I've been thinking about what we need to do to the de-whitening boards for the ITMs and ETMs, in order to have low noise actuators. Noting down what I have so far, so that people can comment / point out things I've overlooked.

Attachment #1: Block diagram schematic of the de-whitened signal path on D000183 as it currently exists. I've omitted the unity gain buffer stage at the output, though this is important for noise considerations.

Some considerations, in rough order of priority:

1. Why do we need de-whitening?
• Because we want the Johnson noise of the series resistor (4.5 kohm) in the coil driver path to dominate the current noise to the coils at ~200 Hz where we want to measure the squeezing.
2. What should the shape of this de-whitening filter be?
• The DAC noise was measured to be ~1 uV/rtHz at 200 Hz.
• The Johnson noise spectral density of 4.5 kohm at 300 K is ~9 nV/rtHz
• So we need ~60dB of attenuation at 200 Hz relative to DC. Currently, they have ~80dB of attenuation at 200 Hz.
• However, we also need to consider the control signal multiplied by the inverse of this shape in the digital domain (required for overall flat shape). This should not saturate the DAC range.
• Furthermore, we'd like for the shape to be such that we don't have a large transient when transitioning between high range and low noise modes. We should use the DARM control signal estimate to inform this choice.
3. What about the electronics noise of the de-whitening filter itself?
• This shows up at the input of the coil driver stage, and gets transmitted to the coil with unity gain.
• So we should aim for < 3nV/rtHz at 200 Hz, such that we are dominated by the Johnson noise of the 4.5 kohm series resistance [the excess will be 5%].
• This can be realized by using the passive network which is the final stage in the de-whitening (there is a unity gain output buffer stage implemented with LT1128, which we also have to account for).

I will experiment with a few different shapes and investigate noise and de-whitened digital signal levels based on these considerations. At the very least, I guess we should remove the x3 gain on the ETM boards, they have already been bypassed for the ITMs.

Attachment 1: DeWhiteningSketch.pdf
14112   Sun Jul 29 00:59:54 2018 KojiUpdateElectronicsCharacterization of Transimpedance Amplifier

You have this measurement problem when the IF bandwidth is larger than the measurement frequency. I suspect the IF bandwidth is 30kHz.

14125   Thu Aug 2 20:47:29 2018 gautamSummaryElectronicsX Green "Mystery" solved

I walked down to the X end and found that the entire AUX laser electronics rack isn't getting any power. There was no elog about this.

I couldn't find any free points in the power strip where I think all this stuff was plugged in so I'm going to hold off on resurrecting this until tomorrow when I'll work with Steve.

 Quote: The X arm green does not stay locked to the cavity - the alignment looks fine, and the green flashes are strong, but the lock does not hold. This shouldn't be directly connected to anything we did today since the Green PDH servo is entirely analog.
14128   Fri Aug 3 14:35:56 2018 gautamSummaryElectronicsEX AUX electronics power restored

Steve and I restored the power to the EX AUX electronics rack. The power strip on the lowest shelf of the AUX rack now goes to another power strip laid out vertically along the NW corner of 1X9. The EX green locks to the arm just fine now.

14175   Wed Aug 22 00:22:05 2018 KojiSummaryElectronicsInspection of the possible dual backplane interfaces for Acromag DAQ

[Johannes, Koji]

We went around the LSC, PSL, IOO, and SUS racks to check how many dual backplane interfaces will be required.

Euro card modules are connected to the backplane with two DIN 41612 connectors (as you know). The backplane connectors provide DC supplies and GND connections.
In addition, they are also used for the input and output connections with the fast and slow machines.

According to the past inspection by Johannes, most of the modules just use the upper DIN41612 connector (called P1). But there are some modules exhibited the possibility of the additional use of the other connector (P2).

Tuesday afternoon Johannes and I made the list of the modules with the possible dual use. And I took a time to check the modules with DCC, Jay's schematics, and the visual inspection of the actual modules.

LSC Rack

• Common mode servo (D040180 Rev B)
• Schematic source D040180 Rev B D1500308
• Assesment: Both P1 and P2 are to be connected to Acromag, but there are only a few channels on P2
• P1: 1A-32A Digital In
• P2: 1A-3A Analog Out (D32/33/34, SLOW MON and spare?)
9A Digital Out for D35 (Limitter)
10A-15A Spare
16A Digital In (Latch Enable/Disable)
• PD Interface (D990543 Rev B)
• Schematic source D990543 RevB
• Assesment: No connection necessary. We don't monitor/control anything of any LSC PDs from Acromag.

PSL Rack

• Generic DAQ Interface (D990155) - This is a DAC interface.
• Schematic source: Jay's page D990155 Rev.B All the lines between P2 and P3 are connected.
• Assesment: Only P2 is to be connected to Acromag.
• P1 DAC mon -> not necessary
• P2 A1-A16, Connected to DAC in P2-P3
• PMC Servo
• Schematic source: LIGO DCC D980352
• Assesment: Only P1 (1A-9A) is to be connected to Acromag. (Just one DSub is sufficient)
• P1 1A-9A
• Crystal Ref (D980353)
• Schematic source: LIGO DCC D980353
• Assesment: Only P1 (1A-4A) is to be connected to Acromag. (Just one DSub is sufficient)
• P1 1A-4A
• TTFSS REV A
• Assesment: Probably Only P1 is sufficient. We need to analyze the board to figure out the channel assignment.

IOO Rack

• PD Interface (D990543 Rev B)
• Schematic source D990543 RevB
• Assesment: Only P1 connection is sufficient.
• Generic DAQ Interface (D990155)
• Assesment: Remove the module. We already have the same module in PSL Rack. This is redundant.
• Common mode servo (D040180 Rev B)
• See above
• Pentek Generic Input Board D020432
• Schematic source Jay's page D020432-A
• Assesment: No connection. There is no signal on the backplane.

SUS Rack

• SUS Dewhitening
• Schematic source: Jay's page D000316-A
• Assesment: No connection.
• We can omit Mon CHs.
• Bypass/Inputs are already connected to the fast channels.

14177   Wed Aug 22 12:22:27 2018 ranaSummaryElectronicsInspection of the possible dual backplane interfaces for Acromag DAQ

I think we don't need to keep Crystal Ref: we can change this into a regular Wenzel box with no outside control or monitoring.

 Quote: Crystal Ref (D980353) Schematic source: LIGO DCC D980353 Assesment: Only P1 (1A-4A) is to be connected to Acromag. (Just one DSub is sufficient) P1 1A-4A

14273   Tue Nov 6 10:03:02 2018 SteveUpdateElectronicsContec board found

The Contec test board with Dsub37Fs was on the top shelf of E7

Attachment 1: DSC01836.JPG
14414   Wed Jan 23 18:11:56 2019 gautamUpdateElectronicsEthernet Power Strip IP conflict

For the last week, I noticed that I was unable to turn the EY chamber illuminator on using the remote python scripts. This was turning out to be really annoying, having to turn the light on/off manually. Today, I looked into the problem and found that there is a conflict in the IP addresses of the EY Ethernet Strip (which Chas assigned a static IP but did not include detailed procedures for) and the vertex area laptop, paola. The failure of the python control of the power strip coincided exactly with when Chub and I turned on paola for working at the IY chamber - but how was I supposed to know these events are correlated? I tried shutting down paola , power cycling the Ethernet power strip, and restarting the bind9 services on chiara, but remote control of the ethernet power strip remains elusive. I suspect reconfiguring the static IP for the Ethernet switch will require some serial port enabled device...

14417   Thu Jan 24 22:55:50 2019 gautamUpdateElectronicsSatellite box S/N 102 investigation

I had taken Satellite box S/N 102, from the SRM suspension, down to the Y-end as part of debugging. However, at some point, I stopped getting readbacks from the shadow sensor PDs, even with the Sat. Box tester hooked up (so as to rule out anything funky with the actual OSEMs). Today evening, I did a more systematic investigation. Schematic with component references is here.

1. Used mini-grabbers and a bench power supply to connect +/-24V to C57 and C58.
2. Checked that all ICs were getting +/- 15 V to the supply pins.
3. Debugged individual channels, checking voltages at various nodes
• Found that the "PD K" bias voltage was anomalosly low.
• Found that the inverting input of U3C wasn't ground.
• The above findings are summarized in Attachment #2.
• This suggested something was wrong with the Quad OpAmp LT1125 IC, so I elected to switch it out.
• During the desoldering process, the pads for the "NC" pins came off (Attachment #1) - this has happened to me before on these old boards. I don't think I applied excess heat during the desoldering (I used 650F).
• Replaced the IC, and measured the expected 10V at the "PD K" node.
4. I then connected the tester box and verified all the shadow sensor channels (LED + PD) work as expected, using the front panel J3 and the "octopus cable".
5. It remains to verify that the coil driver signals get correctly routed through the Satellite box before giving this box a pass certification.

The question remains as to what caused this failure mode - I can't think of why that particular IC was damaged during the Satellite box swapping process - is this indicative of some problem elsewhere in the ETMY OSEM/coil driver electronics chain?

Attachment 1: IMG_7294.JPG
Attachment 2: D961289-B2.pdf
14418   Fri Jan 25 12:49:53 2019 gautamUpdateElectronicsEthernet Power Strip IP conflict resolved

To avoid the annoying excercise of having to manually toggle the illuminators, I solved the IP conflict. Made a wiki page for the ethernet power strips since the documentation was woeful (the way the power strips are mounted in the racks, you can't even see the manufacturer/model/make). All chamber illuminators can now be turned on/off by the MEDM scripts . Note that there is a web interface available too, which can be useful in case of some python socket issues. The main lesson is: avoid using the "reset" button on the power strips, it destroys the static IP config.

Unrelated to this work: The EY laptop, asia, won't boot up anymore, with a "Fan Error" message being the red flag. I've temporarily recommissioned the vacuum rack laptop, belladonna, to be the EY machine for this vent. Can we get 3 netbooks that actually work and don't need to be tethered to a power strip for the VEA?

14421   Tue Jan 29 17:19:16 2019 gautamUpdateElectronicsSatellite box S/N 105 repaired

[chub, koji, gautam]

Attachment #1 shows the signal routing near the Satellite box. Somehow, the female 64 pin IDC connector that brings the signals from the coil driver board wasn't mating well with the mail connector on the Satellite box front panel. This is a connector specific problem - plugging the female end into one of the male connectors inside the Satellite box yielded signal continuity. The problem was resolved by re-making both connections -by driving the EPICS bias slider through its full range, we were able to see the full voltage swing at the DB connectors going to the flange

This kind of flakiness could be all around the lab, and could be responsible for many of the suspension "mysteries". To re-iterate, the problem seems to be the way the female sockets of the connector mates with the male pins - while the actual crimping points may look secure, there may not be signal continuity.

Now that this problem is resolved, tomorrow we will recover the cavity alignment and possibly start a pumpdown.

Unrelated to this work - the spare satellite box (S/N #100), which had a note on it that said "low voltages", was tested. The "low voltages" referred to the OSEM shadow sensor voltages being low when the LED was completely unobscured. The reason was that the mod to increase the drive current to 25 mA had not yet been implemented on this unit. I added the appropriate 806 ohm resistors, and verified that the voltages were correct, so now we have a working spare. It is stored in the "photodiode" cabinet along the east arm, together with the tester boxes.

Attachment 1: IMG_7301.JPG
14555   Fri Apr 19 12:06:31 2019 awadeBureaucracyElectronicsBorrowed Busby Box May 19th 2019

I've borrowed the Busby Box for a day or so.  Location: QIL lab at Bridge West.

Edit  Sat Apr 20 21:16:46 2019 (awade): returned.

14584   Mon Apr 29 16:34:27 2019 gautamUpdateElectronicsITMX/IMTY mis-labelling fixed at 1X4 and 1X5

After the X and Y arm naming conventions were changed, the labelling of the electronics in the eurocrates was not changed 😞 😔 😢 . This meant that when we hooked up the new Acromag crate, all the slow ITMX channels were in fact connected to the physical ITMY optic. I ♦️fixed♦️ the labelling now - Attachments #1 and #2 show the coil driver boards and SUS PD whitening boards correctly labelled. Our electronics racks are in desperate need of new photographs.

The "Y" arm runs in the EW direction, while the "X" arm runs in the NW direction as of April 29 2018.

ITMX was freed. ITMY is being worked on is also free..

Attachment 1: IMG_7400.JPG
Attachment 2: IMG_7401.JPG
14669   Thu Jun 13 15:08:31 2019 MilindUpdateElectronicsVCO pickup by Rich

Rich dropped by at around 3:00 PM today and picked up the VCO in Attachment #1 and left the note in Attachment #2 on Gautam's desk with the promise of bringing it back soon.

Attachment 1: WhatsApp_Image_2019-06-13_at_15.06.57.jpeg
Attachment 2: WhatsApp_Image_2019-06-13_at_15.06.57(1).jpeg
14718   Tue Jul 2 12:30:53 2019 gautamUpdateElectronicsAcromag crate switched to Sorensens

[chub, gautam]

We crossed off another couple of bullets today.

It took me ~1 hour to realize that c1susaux requries the running of sudo /sbin/ifup eth0 to be run in order to see the martian network - why???

Activity:

1. Stopped the c1susaux machine:
• Moved alignment sliders of ITMX and ITMY to 0 as a precaution.
• Shutdown the c1susaux machine so that it doesn't become unhappy with the missing Acromags when we power the unit down.
2. Dialled down supply voltages on the +/- 15 V and +/- 20 V DC Sorensens. Current draw became 0 A on the front panel indicators.
3. Chub tapped some new terminal blocks for +15 V DC and +20 V DC
• This required some additional daisy chaining, which is why we dialled down the Sorensens.
• New cables were made using the "standard" LIGO color scheme, which isn't really applicable in this case because we are using +15 V DC (orange sheath wire) and + 20 V DC (yellow sheath wire) whereas the closest LIGO standard voltages are +18 V DC and +24 V DC.
• A test cable, presumably meant to be used in the electronics area (orange for +15 V DC) was destroyed for this work as we opted for speed rather than making a new cable.
4. Disconnected bench power supplies that were powering the Acromags, and connected the new cables.
• I opted to use 5 A fuses in the terminal blocks for these supplies as the current draw is pretty significant.
5. Dialled the Sorensens back up to the nominal voltages:
• Attachment #1 shows the front panels of the Sorensens before and after this work.
• The current limit on the +20 V DC Sorensen had to be raised, because the Acromag box draws ~2.3 A on its own, whereas the previous current draw was 2.8 A.
6. Brought the c1susaux machine back online. Took me a while to get to the bottom of why I wasn't able to see c1susaux on the martian, but eventually, I figured out the whole sbin/ifup thingy.

I don't understand the exact chain of causation, but during this work, the fast c1sus model crashed. I had to go through a few iterations of the scripted vertex machine rebooting, but things seem to be back in a normal state now, see Attachment #2. Should probably run the IFO test suite to make sure everything is a-okay, but for now, I am able to lock the IMC so I'm moving on.

The main task remaining here is to take new pictures of everything and upload to the wiki. Also, need to update the Sorensen labels to reflect their current values, some of them are outdated.

 Quote: Take photos of the new setup, cabling. Remove the old c1susaux crate from the rack to free up space, possibly put the PSL monitoring acromag chassis there. Test that the OSEM PD whitening switching is working for all 8 vertex optics.(verified as of 5/3/19 5pm) New 15V and 24V power cables with standard LIGO connectors need to be run from the Sorensenn supplies in 1X5. The chassis is currently powered by bench supplies sitting on a cart behind the rack. All 24 new DB-37 signal cables need to be labeled. New 96-pin DIN connectors need to be put on two ribbon cables (1Y5_80 B, 1Y5_81) in the 1X4 rack. We had to break these connectors to remove them from the back of the eurcrates. General cleanup of any cables, etc. left around the rack. We cleaned up most things this evening. Rename the host computer c1susaux2 --> c1susaux, and update the DNS lookup tables on chiara.
Attachment 1: 1X5Sorensens.pdf
Attachment 2: CDS_20190702.png
14754   Thu Jul 11 18:15:22 2019 gautamSummaryElectronicsPSL/IOO rack checkout

I looked at the PSL/IOO racks to check for which boards, if any, require an additional P2 interface, so that we can try and design a generic one for the IMC/CM boards and whatever else may require it. While searching the elog, I saw that Koji and Johannes had already done this, see Koji's elog in this thread. Some remarks:

1. D990155 seems to be unused in both PSL and IOO racks. The one in the PSL rack has some LEMO cables plugged in to the front panel, but they go nowhere. So I think that both of these are redundant (in the assessment below, only one was marked redundant).
2. In the PSL rack, the "TTFSS Interface", "PSL PMC SERVO", and "DAQ INTERFACE" (which I think is obsolete) cards all have their P2 connectors daisy chained together, going to a cross-connect. Kruthi and I traced this to be going to a cross connect marked "J23-PSLRACK-CCP". In the PSL wiring diagram of which we have a hardcopy in the control room, it looks like these channels are related to the RefCav? So I think this is not required to be interfaced to our new Acromag DAQ system.

Conclusion: Only the IMC Servo and CM boards need their P2 connectors connected to Acromag.It would be helpful to remove the TTFSS Interface board and figure out what exactly the pin-mapping for the backplane connectors are, but I didn't do this today because there is a "High Voltage" line going to the Interface Board and I'm not actually sure of the signal chain for the FSS servo.

14839   Fri Aug 9 20:58:33 2019 JonUpdateElectronicsBorrowed Variac transformer

I borrowed an old-looking Variac variable transformer from the power supplies cabinet along the y-arm. It is currently in the TCS lab.

14945   Mon Oct 7 14:51:20 2019 aaronUpdateElectronicsWFS head RF measurements

Mon Oct 7 14:51:53 2019. I closed the PSL shutter to measure the WFS head responsivity.

I made a thru calibration as in this elog, treating laser, reference PD, and WFS RF output as a three-port device. The DC current supplied to the laser is 20.0 mA in all cases. The Agilent spectrum analyzer supplies a -10 dBm excitation to Jenne laser's AM port, and A/B is measured with 20dB attenuation on each input port. Results are in /users/aaron/WFS/data/191007/. The calibration had 100 averages, all other measurements 32 averages; other parameters found in the yml file, same folder as the data.

 Measurement Reference PD DC (V) WFS Segment DC (V) WFS Segment DC, beam blocked (V) File Notes WFS 1 Segment 1 1.86 0.79 -0.23 TFAG4395A_07-10-2019_154446.txt WFS 1 Segment 2 1.86 0.72 -0.30 TFAG4395A_07-10-2019_155017.txt WFS 1 Segment 3 1.86 0.79 -0.21 TFAG4395A_07-10-2019_155645.txt WFS 1 Segment 4 1.86 0.70 -0.30 TFAG4395A_07-10-2019_160334.txt TFAG4395A_07-10-2019_160847.txt I noticed the BS-PRM illuminator was on, and turned it off for the second measurement WFS 2 Segment 1 1.86 0.56 -0.38 TFAG4395A_07-10-2019_162533.txt WFS 2 Segment 2 1.86 0.71 -0.21 TFAG4395A_07-10-2019_163402.txt WFS 2 Segment 3 1.86 0.68 -0.28 TFAG4395A_07-10-2019_164152.txt WFS 2 Segment 4 1.86 0.57 -0.42 TFAG4395A_07-10-2019_164745.txt

I normalized the result by the difference between the dark and bright DC levels of each segment.

Mon Oct 7 17:29:58 2019 opened PSL shutter.

14951   Tue Oct 8 16:00:06 2019 aaronUpdateElectronicsWFS head RF measurements

I simulated this circuit with zero, but haven't gotten the results to match the measurements above.

Removing the DC readout chain from the circuit does not affect the AC response.
Perhaps something to do with the (currently unmodeled) capacitance of the diode? I think this forms a necessary part of the resonant circuit. The gain is also suspiciously low.
Edit: Indeed, simply adding the 'typical' shunt capacitance (9pF) and a small series resistor (10 Ohm) gives the right qualitative response
The python notebook is in /users/aaron/WFS/electronics.
The DC response flattens off at ~20dB by ~mHz, which also seems longer than the timescales I saw while measuring; I'm not sure I have some of the AD827 parameters correct (eg 'delay')

I came across this nice note on photodiodes.

Attachment 1: WFS_ACresponse.pdf
Attachment 2: WFS_DCresponse.pdf
14959   Wed Oct 9 12:15:05 2019 ranaUpdateElectronicsWFS head RF measurements

It would be good if you and Shruti can look at how to change the parameters in Zero so as to do a fit to the measured data. Usually, in scipy.optimize we give it a function with some changeable params, so maybe there's a way to pass params to a zero object in that way. I think Ian and Anchal are doing something similar to their FSS Pockel's cell simulator.

15230   Thu Feb 27 15:50:37 2020 gautamUpdateElectronicsFSS box power cable removed

In 1X1, there is a box labelled "FSS REF" below a KEPCO HV supply. This box had a power cable that wasn't actually connected to any power. I removed said cable.

15238   Mon Mar 2 16:29:40 2020 gautamUpdateElectronicsc1psl VME crate removed, Acro-crate installed

[JV, JWR, YD, GV]

• The old c1psl VME crate, and all the ribbon cables connected to it were removed from 1X1. They are presently dumped in the office area - we will clear these in the next few days, once the c1iool0 crate also gets removed from the rack.
• The Acromag crate was capped on the top and bottom, had ears bolted on, and was installed on support rails in the newly cleared up space.
• The strange orientation of the crate (with the intended backside facing the front of the rack) is to facilitate easy access to the "spare" channels we have in this box, e.g. for a future ISS or laser amplifier.
• Remaining connections to make are (these will be done tomorrow along with the extrication of the c1iool0 VME crate):
• PMC trans PD
• FSS RMTEMP
• PSL shutter
• 2W Mephisto diagnostic connector
• 24 V DC from Sorensens via DIN connector (we are waiting on a new power cable to arrive).
Attachment 1: c1psl.pdf
15242   Tue Mar 3 17:20:14 2020 gautamUpdateElectronicsMore cabling removed

Jordan and I removed another 10 kg of cabling from 1X2. The c1iool0 crate now has all cabling to it disconnected - but it remains in the rack because I can't think of a good way to remove it without disturbing a bunch of cabling to the fast c1iool0 machine. We can remove it the next time the vertex FEs crash. Cross connects have NOT been removed - we will identify which cross connects are not connected to the fast system and trash those.

Do we want to preserve the ability to use the PZT driver in 1X2?

15243   Tue Mar 3 17:59:33 2020 YehonathanUpdateElectronicsPSL Shutter and PMC TRANSPD working

I used existing BNC cables running from the PSL table to the PSL rack and reassigned them to the PSL Shutter and PMC transmission PD channels.

The PSL shutter turned out to be a sinking channel. Jordan reconnected the PSL shutter wires to a sinking BIO Acromag. Channel list is updated.

Both channels have been tested to be working as expected.

• the PSL shutter channels were previously hosted on c1aux.
• I didn't comment out the original database entries on c1aux because we changed the prefix for all these channels - i.e. C1:AUX-PSL_Shutter --> C1:PSL-PSL_Shutter.
• Modified the LSC offset script to close/open the PSL shutter by writing to the correct channel now.
• there is some EPICS logic that checks the main volume pressure and prevents the opening of the PSL shutter if the main volume pressure is between 0.003 torr and 500 torr. I preserved this capability (so there are some associated soft channels in the database as well).

P.S - there is a problem we noticed - if the modbus process is started with the local subnet not having a fixed IP address, then all the EPICS channels will not be responsive. The way to fix this is to run the following sequence of commands:

sudo systemctl stop modbusIOC.service
sudo ifdown enp4s0
sudo ifup enp4s1
sudo ssytemctl start modbusIOC.service
15249   Wed Mar 4 16:18:31 2020 gautamUpdateElectronicsMore cabling removed

After discussing with Koji, I removed the PZT driver and associated AI card from the Eurocrate at 1X2. The corresponding backplane connectors were also removed from the cross connects. An additional cable going from the DAC to IDC adaptor on 1X2 was removed. Finally, some cables going to the backplane P1 and P2 connectors for slots in which there were no cards were removed.

Finally, there is the IMC WFS whitening boards. These were reconfigured in ~2016  by Koji to have (i) forever whitening, and (ii) fixed gain. So the signals from the P1 connector no longer have any influence on the operation of this board. So I removed these backplane cables as well.

Some pics attached. The only cross connect cabling remaining on the south side of 1X2 is going to the fast BIO adaptor box - I suspect these are the triggered fast whitening switching for the aforementioned WFS whitening board. If so, we could potentially remove those as well, and remove all the cross connects from 1X1 and 1X2.

Update 1720: indeed, as Attachment #2 shows, the RTCDS BIO channels were for the WFS whitening switching so I removed those cables as well. This means all the xconnects can be removed. Also, the DAC and BIO cards in c1ioo are unused.

 Quote: Do we want to preserve the ability to use the PZT driver in 1X2?
Attachment 1: 1X2EuroBefore.JPG
Attachment 2: IOO.png
15251   Wed Mar 4 20:42:53 2020 gautamUpdateElectronicsC1PSL acromag crate is sitting on the floor

Jon is going to write up the details of todays adventures. But the C1PSL Acromag chassis is sitting on the floor between the IMC beamtube and the 1X1 electronics rack, and is very much a trip hazard. Be careful if youre in that area.

15252   Wed Mar 4 21:02:49 2020 KojiUpdateElectronicsMore cabling removed

We are going to replace the old Sun c1ioo with a modernized supermicro. At the opportunity, remove the DAC and BIO cards to use them with the new machines. BTW I also have ~4 32ch BIO cards in my office.

15254   Thu Mar 5 11:27:48 2020 gautamUpdateElectronicsC1PSL acromag crate is no longer sitting on the floor

[jordan, gautam]

The C1PSL crate has now been installed in a more permanent way in the rack.

• Top and bottom covers were re-attached after work yesterday.
• +/- 24 V DC and +15 V DC power connectors were screwed on for better robustness (I had removed the fuse for the -24V supply as part of debugging yesterday, this was reconnected).
• PSL diagnostics DB 25 cable was re-run appropriately over the cable tray and connected to the unit.
• The chassis sits on some rails - these rails are mounted to the rack using rack nuts but that means the ears on the Acromag chassis no longer line up with any rack nut slots, and so the chassis is not bolted on to the rack.
• We also took this opportunity to remove the c1iool0 VME chassis from 1X2 - given that the DAC and BIO cards of c1ioo (rtcds system) are unused, I felt comfortable disconnecting them and that made the removal relatively easy. The CDS overview MEDM screen reports no errors after this work.

After this work, I disabled logging and restarted the modbus service (and copied the current version of the systemd service file to the target directory for backup). The PMC and IMC lock alright. The system is now ready to be tested in-situ. I will separately continue my IMC Servo board tests in the evening.

One thought about how to protect against this kind of silent failure - how about we always run the modbus service with logging enabled, and then send out a warning email and stop the service if the logfile size suddenly blows up (which is characteristic of when the communications process dies)? This should be done in addition to the ping-ing of the individual IPs.

Regarding the burt-restore step that the systemd service runs after starting up the IOC - this is not even that useful, at least in the way it is currently setup (restore the "latest" burt snapshot file). If the maintenance takes >1hour as it often does, the "latest" snapshot for the system under maintenance is just garbage. So either the burt-restore should be for a "known good time" (dangerous because this will require frequent updates of the systemd service every time we find a new safe state) or we should just do it manually (my preference). Then there is no need to install custom packages on the server machine. Anyway, for now, I have not commented this step out.

Jordan is going to take pictures of all the electronics racks and update the relevant wiki pages.

 Quote: Jon is going to write up the details of todays adventures. But the C1PSL Acromag chassis is sitting on the floor between the IMC beamtube and the 1X1 electronics rack, and is very much a trip hazard. Be careful if youre in that area.
15255   Thu Mar 5 15:03:48 2020 YehonathanUpdateElectronicsPSL Shutter and PMC TRANSPD working

[Jon, Yehonathan]

Summary

With the Acromag chassis now permanently installed, we tested the C1PSL channels going over the channel list one by one, excluding the IMC channels which Gautam is taking responsibility for (the servo board itself is also in question).

The strategy is to check the response of input channels to specific output channels for expected behaviour whenever is possible.

We marked on the channel list spreadsheet the status of the channels that were tested.

In more detail

FSS

 Channels under test What was done C1:PSL-FSS_SW1 Switched C1:PSL-FSS_SW1 and observed the IMC unlock C1:PSL-FSS_SW2, C1:PSL-FSS_MIXERM Connected a signal to Test2 on FSS box and observed a proportional change on C1:PSL-FSS_MIXERM C1:PSL-FSS_INOFFSET Disconnected feedback by switching C1:PSL-FSS_SW1. Tweaked C1:PSL-FSS_INOFFSET and observed a proportional response in C1:PSL-FSS_MIXERM C1:PSL-FSS_MGAIN, C1:PSL-FSS_PCDRIVE Disconnected feedback, turned on some offset using C1:PSL-FSS_INOFFSET. Tweaked C1:PSL-FSS_MGAIN and observed a response in C1:PSL-FSS_PCDRIVE C1:PSL-FSS_SLOWDC, C1:PSL-FSS_SLOWM Disconnected feedback. Tweaked C1:PSL-FSS_SLOWDC and obsereved a proportional response in C1:PSL-FSS_SLOWM C1:PSL-FSS_FASTGAIN, C1:PSL-FSS_FAST Disconnected feedback, turned on some offset using C1:PSL-FSS_INOFFSET. Tweaked C1:PSL-FSS_FASTGAIN and obsereved a response in  C1:PSL-FSS_FAST

Frequency Ref

 Channels under test What was done C1:PSL-PMC_PHCON Observed the PMC unlocks when a big change in C1: PSL-PMC_PHCON is made C1:PSL-PMC_RFADJ, C1:PSL-PMC_MODET Tweaked C1:PSL-PMC_RFADJ and obsereved a proportional response in C1:PSL-PMC_MODET C1:PSL-PMC_PHFLIP Observed the PMC unlock when C1:PSL-PMC_PHFLIP is switched

PMC Servo Card

 Channels under test What was done C1:PSL-PMC_SW1, C1:PSL-PMC_PMCERR, C1:PSL-PMC_INOFFSET, C1:PSL-PMC_PZT Unlocked the PMC by switching C1:PSL-PMC_SW1. Tweaked C1:PSL-PMC_INOFFSET and observed a proportional change in C1:PSL-PMC_PMCERR and C1:PSL-PMC_PZT C1:PSL-PMC_BLANK Observed the PMC unlock with when C1:PSL-PMC_BLANK is switched C1:PSL-PMC_GAIN Unlocked the PMC by switching C1:PSL-PMC_SW1. Turned on some offset using  C1:PSL-PMC_INOFFSET. Tweaked C1:PSL-PMC_GAIN and observed response in C1:PSL-PMC_PZT C1:PSL-PMC_SW2 Unlocked the PMC by switching C1:PSL-PMC_SW1. Connected a signal to TP2 on the PMC card and observed a proportional change in C1:PSL-PMC_PZT. C1:PSL-PMC_RAMP Unlocked the PMC by switching C1:PSL-PMC_SW1. Tweaked C1:PSL-PMC_RAMP and observed a change in C1:PSL-PMC_PZT. C1:PSL-PMC_RFPDDC Observed a high value 0.5V when PMC is unlocked and a low value 0.03V when it is locked

WFSs

 Channels under test What was done C1:IOO-WFS*_SEG*_ATTEN We misaligned MC1 to get a measurable signal in WFS channels. NDScoped the corresponding C1:IOO-WFS*_SEG*_I&Q channels and observed a change in those channels in response to switching the attenuation on and off. C1:IOO-WFS*_LO_LOCK_MON Disconnected the LO cable from the WFS boards and observed C1:IOO-WFS*_LO_LOCK_MON go to zero. C1:IOO-WFS*_SEG*_I&Q Connected a short SMA cable to the 29.5MHz frequency distribution board. Attenuated the signal by 20db and connected it to the different SEG channels one at a time and observed a response in C1:IOO-WFS*_SEG*_I&Q channels. C1:IOO-WFS*_SEG*_DC We shined a laser pointer to the different quadrants and observed saturation in the corresponding C1:IOO-WFS*_SEG*_DC with no cross talks.

MC Servo

 Channels under test What was done C1:IOO-MC_SW1, C1:IOO-MC_OPTIONA, C1:IOO-MC_POL, C1:IOO-MC_OPTIONB,C1:IOO-MC_FASTSW These switches unlocked the IMC when flipped. C1:IOO-MC_SW2, C1:IOO-MC_SUM_MON, C1:IOO-MC_SLOW_MON, C1:IOO-MC_FAST_MON A sine wave signal was injected in IN2 on the servo board. C1:IOO-MC_SW2 was switched on and the value of C1:IOO-MC_SUM_MON, C1:IOO-MC_SLOW_MON and C1:IOO-MC_FAST_MON changed accordingly. C1:IOO-MC_SW3 Connected a scope to OUT2 on the servo board. Switched C1:IOO-MC_SW3 on and observed a signal on the scope. C1:IOO-MC_EXCA_EN Unlocked the IMC by switching C1:IOO-MC_SW1 off. Connected a signal to EXC A and a scope to TP2A on the servo board and observed the signal on the scope when C1:IOO-MC_EXCA_EN was switched on. C1:IOO-MC_EXCB_EN Unlocked the IMC by switching C1:IOO-MC_SW1 off. Connected a signal to EXC B and a scope to TP2B on the servo board and observed the signal on the scope when C1:IOO-MC_EXCB_EN was switched on. C1:IOO-MC_REFL_OFFSET Unlocked the IMC by switching off. Tweaked C1:IOO-MC_REFL_OFFSET and observed a proportional change in C1:IOO-MC_SUM_MON. C1:IOO-MC_LATCH_EN Tweaked the VCO gain slider and observed the latch switch off and on. C1:IOO-MC_LIMIT Unlocked the IMC by switching C1:IOO-MC_SW1 off. Connected a sine wave signal to EXC B and enabled C1:IOO-MC_EXCB_EN. Ramped up the VCO gain. Raised the sine wave amplitude until C1:IOO-MC_LIMIT turned on. C1:IOO-MC_LIMITER We ramped the VCO such that C1:IOO-MC_LIMIT was switched on. We switched C1:IOO-MC_LIMITER on and observed C1:PSL-FSS_MIXERM high value go down.

NPRO Diagnostics

 Channels under test What was done C1:PSL-NPRO_* The signals were compared to previous values for consistency. Then they were unplugged from the Acromag chassis to confirm their values went to 0 and returned to the same values after being reconnected.
15257   Thu Mar 5 19:51:14 2020 gautamUpdateElectronicsIMC Servo board being tested

I am running some tests on the IMC servo board with an extender card so the IMC will not be locking for a couple of hours.

15258   Fri Mar 6 01:12:10 2020 gautamUpdateElectronicsIMC Servo IN2 path looks just fine

It seems like the AO path gain stages on the IMC Servo board work just fine. The weird results I reported earlier were likely a measurement error arising from the fact that I did not disconnect the LEMO IN2 cable while measuring using the BNC IN2 connector, which probably made some parasitic path to ground that was screwing the measurement up. Today, I re-did the measurement with the signal injected at the IN2 BNC, and the TF measured being the ratio of TP3 on the board to a split-off of the SR785 source (T-eed off). Attachments #1, #2 shows the result - the gain deficit from the "expected" value is now consistent with that seen on other sliders.

Note that the signal from the CM board in the LSC rack is sent single-ended over a 2-pin LEMO cable (whose return pin is shorted to ground). But it is received differentially on the IMC Servo board. I took this chance to look for evidence of extra power line noise due to potential ground loops by looking at the IMC error point with various auxiliary cables connected to the board - but got distracted by some excess noise (next elog).

Attachment 1: AO_inputTFs_5Mar.pdf
Attachment 2: sliderCal_5Mar.pdf
ELOG V3.1.3-