Actually, I just found out that there are different flavors of 'YAG-444'.

There's a YAG-444AH and also a YAG-444-4AH. I'm not sure which one we have or even which is better. The diode's internal resistance is not listed.

They also say explicitly that he 'YAG Enhancement' is just using thicker Silicon. Since the absorption of 1064 nm light in Silicon is very small, most of the light just goes in and then comes back out without depositing much of the power.

After Rana pointed me to Yoichi's MEDM snapshot script, I learned how to use Xvfb, which is what Yoichi used to write screens without a real screen.  With this I wrote a new cron script, which I added to Mafalda's cron tab to be run once a day at 6am.

The script is called webview_update.cron and is in /opt/rtcds/caltech/c1/scripts/AutoUpdate/.

#!/bin/bash
DISPLAY=:6
export DISPLAY
#Check if Xvfb server is already running
pid=`ps -eaf|grep vfb | grep $DISPLAY | awk '{print $2}'`
if [ $pid ]; then
        echo "Xvfb already running [pid=${pid}]" >/dev/null
else
# Start Xvfb
echo "Starting Xvfb on $DISPLAY"
Xvfb $DISPLAY -screen 0 1600x1200x24 >&/dev/null &
fi
pid=$!
echo $pid > /opt/rtcds/caltech/c1/scripts/AutoUpdate/Xvfb.pid
sleep 3

#Running the matlab process
/cvs/cds/caltech/apps/linux/matlab/bin/matlab -display :6 -logfile /opt/rtcds/caltech/c1/scripts/AutoUpdate/webview.log -r webview_simlink_update

There was a problem with running the webview report generator in matlab on Mafalada.  It complained of not having a spare report generator license to use, even though the report generator was working before and after on other machines such as Rosalba.  So I moved the old 32 bit matlab directory from /cvs/cds/caltech/apps/Linux/matlab to /cvs/cds/caltech/apps/Linux/matlab_old.  I installed the latest R2010b matlab from IMSS in /cvs/cds/caltech/apps/Linux/matlab and this seems to have made the cron job work on Mafalda now.

I renamed most of the filter banks in the c1lsc model.  The input filters are now labeled based on the RF photodiode's name, plus I or Q.  The last set of filters in the OM subsystem (output matrix) have had the TO removed, and are now sensibly named ETMX, ETMY, etc.

We also removed the redundant filter banks between the LSCMTRX and the LSC_OM_MTRX.  There is now only one set, the DARM, CARM, etc ones.

The webview of the LSC model can be found here.

 [Koji, Kiwamu]

 We succeeded in locking the X arm with the C1LSC digital control.

As we did on the day before yesterday, the feedback signal goes to MCL (#4141), but this time the signal is transfered from C1LSC through the RFM.

 (key points) 

- checking the state of the analog whitening filters at C1LSC rack.

   We took the transfer function of them and found that they were always on regardless of the clicking any buttons on medm.

To cancel the filter shape of the whitening, we put an unWhitening filter so that these transfer functions becomes flat in total.

The whitening filter approximately has : pole:150Hz, pole:150Hz, zero:15Hz, zero:15Hz (although these numbers came from by our eye ball fitting)   

 - demodulation phase adjustment

   We performed the same measurement as that of Suresh and Koji did yesterday (#4143) to adjust the phase of the PDH demodulation.

By changing the cable length we roughly adjusted the I-phase to eventually ~10 deg, which is close enough to 0 deg.

(probably some more efforts should be made as a part of daytime tasks)

Note that we are currently using the REFL33 demodulation board for this purpose (#4144). The LO power we put is about 16dBm.

The angle between I and Q at 11MHz is actually almost 90 deg.

This fact has been confirmed by putting a sinusoidal signal with a slightly different frequency (~100Hz) from that of the LO onto the RF input.

 - attenuation of RF signal

  Since the PDH signal taken by C1LSC's ADC had been saturated somewhat, we introduced a ND filter of 10 on the photo diode to attenuate the RF signal.

As a result the amplitude of the PDH signal on dataviewer became more reasonable. No more saturations.

(some notes)

 unWhitening filter           pole:15Hz. pole:15Hz, zero:150Hz, zero:150Hz

 C1LSC_MC_FM1   pole:1kHz, zero:10Hz

 Gain in digital control       G ~ -1

measured UGF  ~  200-300 Hz

 measured RFM delay ~ 125 usec 

Here shows a plot of the expected open loop transfer function (TF) for the X arm locking.

I assume that the delay time of the digital system associated with the ADC/DAC and the digital filtering process is ~100 usec independently from the RFM delay according to Yuta's measurement (#3961).

Also I assume the MC2 pendulum has a pole at 1Hz with Q of ~5, and the X arm has its cavity pole at ~3kHz.

When the lock acquisition takes place, we used the red curve shown above in order to avoid a big DC feedback onto MC2.

Once the X arm became resonant at TEM00, we manually switched FM3 on, which is a boost filter containing a pole at  1Hz and a zero at 50Hz in order to suppress the residual motion below 1Hz.

The expected curve for the boosted state is drawn by the blue curve in the plot. 

With this open loop TF, the UGF can be realized only around 100-300 Hz due to the phase margin condition.

This expectation of the UGF is consistent with our measurement because we obtained the UGF around 200-300Hz.

In fact above 300Hz we observed that the control became unstable and started oscillating.

These are the next steps for a better operation of the arm locking. They are suitable for the day time activities

Reconfiguration of the X-End table

- End transmission power monitor (CDS model exists, need to configure the PD)

- IR steering mirror for the transmon

- Restore/align end green beam

- Relocate the end trans CCD

- Connect the video output cable for the X-end CRT monitor

LSC Whitening

- LSC Whitening binary IO connection

They are not urgent but also good things to do

MC servo characterization

- Error signal: frequency noise

- Loop characterization

Arm cavity characterization with cavity sweep

- Arm finesse for 1064nm and 532nm

- Arm FSR measurement with 1064 (and optionally with 532nm simultaneously)

- Arm g-factor for 1064nm and 532nm

My feeling was that the saturation was caused by the LSC whitening filter which was always on.
Once the LSC whitening filter is controlled from C1LSC, we would be able to remove the attenuator.

After getting some help from the Basler technical support, I was directed to the following ftp link:

ftp://Pylon4Linux-ro:h50UZgkl@ftp.baslerweb.com

I went to the pylon 2.1.0 directory and downloaded the pylon-2.1.0-1748-bininst-64.tar.bz2 file.  Inside of this tar file was another one called pylon-bininst-64.tar.bz2 (along with some other sample programs). I ran tar -jxf on pylon-bininst-64.tar.bz2 and placed the results into the /opt/pylon directory.  It produced a directory of includes, libraries and binaries there.

After playing around with the make files for several sample programs they provided, I finally have been able to compile  them.  At several places I had to have the make files point to /opt/pylon/lib64 rather than /opt/pylon/lib.  I'll be testing the camera with these programs on Monday.  I'd also like to see if this particular distribution will work on Centos machines.  There's some comments in one of the INSTALL help files suggesting packages needed for an install on Fedora 9, which may mean its possible to get this version working on the Centos machines.

I like this activateDAQ script, but someone (Jenne with Joe's help) still needs to add the PEM channels - we still cannot see any seismic trends.

Objective:

      We wish to study the coherence of the two NPROs i.e. PSL and the X-end-NPRO by locking both of them to the X-arm and then observing the green beat frequency fluctuations. 

What we did:

   a) locked the PSL to the X-arm as described in 4153

   b) locked the x-end-NPRO to the X-arm with a PDH lock to the reflected green from the ETMX

   c) Obtained the green beat signal with a spectrum analyser as described in 3771

Observations:

   Please see the attached screen shots from the spectrum analyser.   They are taken with different BW and sweep range settings.  They give a estimate of the width of the green beat signal and the range of the frequency fluctuations of the beat-note.

Estimates:

   a) width of the beat note is less than 6KHz if measured over time scales of a few milli seconds

   b) the frequency fluctuations of the beat note are about 100KHz over time scales longer than 100ms

Next Step:

    We wish to record the beat note frequency as a function of time in order to establish the stability over time scale of a day.

The Basler acA640-100gm is a power over ethernet camera.  It uses a power injector to supply power over an ethernet cable to the camera.  Once I got past some initial IP difficulties, the camera worked fine out of the box.

You need to set some environment variables first, so the code knows where its libraries are located.

setenv PYLON_ROOT /opt/pylon
setenv GENICAM_ROOT_V1_1 /opt/pylon
setenv GENICAM_CACHE /cvs/cds/caltech/users/josephb/xml_cache
setenv LD_LIBRARY_PATH /opt/pylon/lib64:$LD_LIBRARY_PATH

I then run the /opt/pylon/bin/PylonViewerApp

Notes on IP:

Initially, you need to set the computer connecting to the camera to an ip in the 169.254.0.XXX range.  I used 169.254.0.1 on megatron's eth1 ethernet connection.  I also set mtu to 9000.

You can then run the IpConfigurator in /opt/pylon/bin/ to change the camera IP as needed.

I used 50 mA to drive the laser diode. The light is split 50/50 between the DUT (Device Under Test) and the New Focus 1611 (1 GHz BW) diode used as the reference.

This measurement is the TF of DUT/(New Focus). The resonances are there, but clearly there's an issue with instability around 200 MHz. The setup is still powered up, so please be careful around the RFPD testing table (don't stomp around yank the cables out of the power supplies).

I looked at the RF Photodiode wiki that Alberto has started - most of the TF features are replicated there. Todo:

* Update the 'schematic' with a real schematic instead of the cartoon.

* Change the circuit to remove the resistor in the RF path.

* Add compensation to avoid the 200 MHz instability.

* Make sure to include opamp current noise in the noise model (it is the dominant noise source but has been left out in the noise estimation plot).

* Make the output into a true 50 Ohms.

The crane people are here. The Vertex chambers are covered with plastic. The PSL HEPAs will be running on high during the day.

It is going to be disturbingly noisy and dirty during the day. Please try start working in the evening if it can not wait till next week.

 [Kiwamu, Suresh]

Today we attempted to convert the beat-note frequency into an analog voltage using the SR620 frequency counter.

First an observation: the stability of the green beat was seen to be much better than the 100kHz fluctuation seen yesterday. Probably because Kiwamu noticed that one of the MC mirrors had a large variance in its motion and changed the  gain and filter parameters to decrease this.  The PSL was therefore more stable and the green peak fluctuation was less than 10kHz over time scales of a few seconds. 

SR620 D/A output resolution given by the manufacturer is 5mV over the -10 to +10V range and this range corresponding to 300MHz.  We, however saw fluctuations of 100mV on the screen which looked as if they corresponded to the  least significant bit.  This would imply a resolution of 1.5MHz at this range.   Even if the manufacturer's claim was true it would lead to a resolution of 75kHz, far in excess of the required resolution a few hundred Hz.

We therefore require to set up the VCO-PLL to obtain a finer frequency resolution.

In the mean time the green beat drifted beyond the 100MHz detection band of the green-PD.  So we changed the x-end-NPRO temperature by -0.05 to bring it back into the detection band.

We are also considering, Rana and Koji's suggestion of using a set of 14 flip-flops to divide the ~80MHz beat frequency so that it comes down to about 4kHz.  This could then be sampled by the usual 16-bit, 64kSa/s ADC cards and brought into the digital domain where further digital processing would be needed to extract the the required frequency variations  in the 0 to 10kHz band.  Found a nice paper on this object

I redid the optical POX transfer functions and updated the wiki at http://lhocds.ligo-wa.caltech.edu:8000/40m/Electronics/POX.

I measured each transfer function several times to calculate uncertainties for each measured point. There is one large transfer function from 1 MHz to 500 MHz showing a resonance peak at 11 MHz and notches at 22 MHz and 55 MHz. I also made more detailed measurements around each of these resonance peaks. These measurements were fit to a resonance curve to determine the resonant frequency, transimpedance at resonance, and Q for each peak. These measurements agree with the shot noise measurement for the transimpedance at 11 MHz taken earlier considering that this measurement was made at 11 MHz instead of at the resonant frequency of 11.14 MHz.

I measured these transfer functions with the Agilent 4395a using the netgpib.py script last week. I realized that when using this script to save multiple copies of the same measurement after setting up the instrument, the first and second measurements are saved but all measurements saved after are identical to the second measurement until the instrument is physically reset. This happens because the analyzer switches the trigger from continuous to hold after making a measurement using this script. Kiwamu said that the script can be modified to return the trigger to continuous after saving the data so that multiple measurements can be saved without being at the analyzer physically. I did not want to waste more time figuring out how to modify the script to do this so I used one of the netbooks and sat at the analyzer manually returning the trigger to continuous after each measurement.

Elog wasn't responding at around 10 am this morning.  I killed the elogd process, then used the restart script.

TF looks fine except for the large peak at around 200MHz which has been reported by Rana. The time series and the spectrum without the light are pathetic...

I still prefer to see the fit by LISO as the pole/zero fitting of LISO as the fit result is more physically understandable.
Anyone can ask me about the instruction how to use LISO

I guess Idc of 24mA would be just a mistake. It looks like ~0.2mA from the plot that sounds normal for the transimpedance of 2kOhm.

Question: What is the HWHM of the reesonance when you have f0 and Q.

 The value of I_dc was a mistake. The value should be 240 µA.

The widths of the resonance peaks are listed below the fits to each peak on the wiki.

[Koji, Kevin]

We fit the entire POX optical transfer function from 1 MHz to 500 MHz in LISO. The fit is on the wiki at http://lhocds.ligo-wa.caltech.edu:8000/40m/Electronics/POX. Using LISO's root fitting mode, we found that the transfer function has five poles and four zeros.

I will work on making plots of the residuals. This is difficult because by default, LISO does not calculate the fitting function at the frequencies of the data points themselves and I haven't figured out how to force it to do this yet.

 I found that c1scy was not running due to a daq initialization error.

 I couldn't figure out how to fix it, so I am leaving it to Joe.

 I connected the PLL signal to the ADC on c1ioo. 

So now we are able to take the data into the digital world, and will be able to feedback signals to the suspensions.

 The output signal from the VCO box goes to a black beakout board on 1X2 rack though a BNC cable.  

Then the signal comes out from the back side of the board with DB39 style, so I put a DB39 to SCSI adapter so that we can take it to the IO chasis.

Now the SCSI is connected to ADC_1 (the second ADC card) on the IO chasis at 1X1. 

  Additionally I modified the green locking simulink model, C1GCV, in order to pick the right ADC channels.

A medm screen for green locking is now under the construction. I put a link on the sitemap screen, so anyone can look at the half-baked green locking screen.

Any comments and suggestions are really welcome.

This is caused by an insufficient number of active DAQ channels in the C1SCY.ini file located in /opt/rtcds/caltech/c1/chans/daq/.  A quick look (grep -v # C1SCY.ini) indicates there are no active channels.  Experience tells me you need at least 2 active channels.

Taking a look at the activateDAQ.py script in the daq directory, it looks like the C1SCY.ini file is included, by the loop over optics is missing ETMY.  This caused the file to improperly updated when the activateDAQ.py script was run.  I have fixed the C1SCY.ini file (ran a modified version of the activate script on just C1SCY.ini).

I have restarted the c1scy front end using the startc1scy script and is currently working.

I realized that the black AA board I mentioned on the last entry has the same range issue as Valera reported before (see #3911). 

Basically our ADC card has +/- 10V input range, but on the other hand the AA board is already limited by approximately +/- 2V.

We have to fix it.

[Aidan, Kiwamu]

Kiwamu and I plugged the output from a DS3456 function generator into the ADC and started recording the data. The func. generator output a 237.8Hz, 1Vpp sine wave. We chose this value because it corresponds to the FSR of a 38.5m cavity (=3.896MHz) divided by 2^14, the frequency divider amount we intend to use.

Since 1 FSR divided down is 237.8Hz and corresponds to a length change of the cavity of 532nm/2 = 266nm, then we can, roughly, say that a frequency change of 1Hz corresponds to a length change in the cavity of approximately 1nm. The width of the 237.8Hz peak in the spectra corresponds to an upper limit on the noise floor due to digitizing the signal (this could be limited by the ADC, or the function generator, or the windowing on the FFT).

The FWHM of the peak in the spectrum was approximately 5mHz, corresponding to an uncertainty in the length of the cavity of about 6pm (we used a Hanning Window, 50% overlap and a BW of 2.92mHz, 7 averages). Regardless of what is the dominant contribution to the width of the peak, this implies that the frequency noise associated with digitizing a signal in the ADC is much smaller than we require and will not limit our performance if we choose to use a frequency divider and digital PLL with the Green Locking.

RA: Here's the previous measurement

Since the 1U sized computers don't have enough slots to hold the host interface board, RFM card, and a dolphin card, we had to move the 2U computer from the end to middle to replace c1sus.

We're hoping this will reduce the time associated with reads off the RFM card compared to when its in the IO chassis.  Previous experience on c1ioo shows this change provides about a factor of 2 improvement, with 8 microseconds per read dropping to 4 microseconds per read, per this elog.

So the dolphin card was moved into the 2U chassis, as well as the RFM card.  I had to swap the PMC to PCI adapter on the RFM card since the one originally on it required an external power connection, which the computer doesn't provide.  So I swapped with one of the DAC cards in the c1sus IO chassis.

But then I forgot to hit submit on this elog entry..............

 [Suresh, Kiwamu]

  We did the following things:

     - installed a 1/10 voltage divider such that the signal won't be saturated at the AA board (see here)

     - put a Ithaco preamplifier 1201 as a whitening filter

     - checked the entire beat detection system without using the real beat note

Here are some items to be done before the sun goes down tomorrow:

       - calibration of ADC and the interfaces including the voltage divider and the whitening filter.

     - fine matching of unwhitening filter at the digital side

         - PLL response measurement ( freq to voltage response ) over the frequency range of interest

         - plotting an well calibrated spectrum of the PLL output 

(whitening filter)

The Ithaco 1201 was setup to have a zero at 0 Hz and two poles at 0.1 Hz and 10 Hz in order to emphasize the signal over the frequency range of interest.

Around 1Hz it is supposed to have a gain of 1000. These settings have done by tweaking the knobs on the front panel of the Ithaco 1201.

In addition to that, we made an unwhitening filter in digital filter banks. This filter was designed to cancel the analog whitening filter.

(system check) 

 To check the entire beat detection system, we phase-locked the VCO to a Marconi running at 80 MHz, which is the center frequency of the VCO.

Then we imposed a frequency modulation on the Marconi to see if the signal is acquired to ADC successfully or not. It's quite healthy.

According to the spectra corrected by the unwhitening filter, we confirmed that the noise floor at 1Hz is order of 1Hz/sqrt Hz, which is already quite good.

Then we took several spectra while putting a modulation on the Marconi at a different frequency in each measurement.

The peak due to the artificial modulation essentially works as a calibration peak in the spectra.

So in this way we briefly checked the flatness of the response of the system in the frequency domain.

As a result we found that the response is not perfectly flat in the range of 0.05 - 30Hz, probably due to a mismatch of the combination of the whitening and unwhitening filters.

We will check it tomorrow.

[Joe, Koji]
Yesterday's CDS swap of c1sus and c1iscex left the interfometer in a bad state due to several issues.

The first being a need to actually power down the IO chassis completely (I eventually waited for a green LED to stop glowing and then plugged the power back in) when switching computers.  I also plugged and plugged the interface cable from the IO chassis and computer while powered down.  This let the computer actually see the IO chassis (previously the host interface card was glowing just red, no green lights).

Second, the former c1iscex computer and now new c1sus computer only has 6 CPUs, not 8 like most of the other front ends.  Because it was running 6 models (c1sus, c1mcs, c1rms, c1rfm, c1pem, c1x02) and 1 CPU needed to be reserved for the operating system, 2 models were not actually running (recycling mirrors and PEM).  This meant the recycling mirrors were left swinging uncontrolled.

To fix this I merged the c1rms model with the c1sus model.  The c1sus model now controls BS, ITMX, ITMY, PRM, SRM.  I merged the filter files in the /chans/ directory, and reactivated all the DAQ channels.  The master file for the fb in the /target/fb directory had all references to c1rms removed, and then the fb was restarted via "telnet fb 8088" and then "shutdown".

My final mistake was starting the work late in the day.

So the lesson for Joe is, don't start changes in the afternoon.

Koji has been helping me test the damping and confirm things are really running.  We were having some issues with some of the matrix values.  Unfortunately I had to add them by hand since the previous snapshots no longer work with the models.

The orientation of the Dolphin cards seems to be opposite on c1lsc and c1sus.  The wide part is on top on c1lsc and on the bottom on c1sus.  This means, the cable is plugged into the left Dolphin port on c1lsc and into the right Dolphin port on c1sus.  Otherwise you get a wierd state where you receive but not transmit.

[Kiwamu, Suresh, Rana]

Our goal:

        We wished to determine the performance of the VCO PLL at low frequencies,. 

The procedure we followed:

        The scheme is to use the Marconi (locked to Rb Clock) as an 80MHz reference and lock to it using the PLL. 

        We set up the VCO PLL as in the diagram shown in the attachment and obtained the spectra shown below.

Results:

          We need to figure out the PLL servo gain profile in order to build the Inv PLL filter....

Damn. If this figure is true, we were looking at wrong signal. We should look at the feedback signal to the VCO.

[Rana, Suresh, Kiwanu]

 We did the following things:

   *  taking the VCO stability data from the error signal instead of the feedback

   *  tried calibrating the signal but confused

   *  increased the modulation depth of the green end PDH.

--

 We found that a cable coming out from the VCO box was quite touchy. This cable was used for taking the feedback signal.

When we touched the cable it made a big noise in the feedback. So we decided to remove the cable and take the signal from the error point (i.e. just after the mixer and the LPF.)

In order to correct that signal to the one in terms of the feedback signal, we put a digital filter which is exactly the same as that of the PLL (pole at 1.5 Hz, zero at 40 Hz, G=1) .

However for some reasons the signal shown in the digital side looked completely mis-calibrated by ~ 100. We have no idea what is going on.

Anyway we are taking the data over tonight because we can correct the signal later. The 2nd round data started from AM1:40

What is the point to use the error instead of the feedback? It does not make sense to me.

If the cable is flaky why we don't solder it on the circuit? Why we don't put a buffer just after the test point?

It does not make sense to obtain the error signal in order to estimate the freeruning noise without the precise loop characterization.
(i.e. THE FEEDBACK LOOP TRINITY: Spectrum, Openloop, Calibration)

RA: I agree that feedback would be better because we could use it without much calibration. But the only difference between the "error signal" and the "feedback signal" in this case is a 1.6:40 pole:zero stage with DC gain of 0 dB. So we can't actually use either one without calibration and the gain between these two places is almost the same so they are both equally bad for the SNR of the measurement. I think that Suresh and Kiwamu are diligently reading about PLLs and will have a more quantitative result on Monday afternoon.

I succeeded in green-locking the X arm by feeding back the beat signal to ETMX.

Here are some quick reports. Some more details will be posted tomorrow.

The below shows a time series data of the PLL feedback signal when the servo was acquiring the lock.

At t = -2 sec. I started feeding back the signal to ETMX with the gain 50 times smaller than its nominal.

Then at t = 0 sec.I switched on a low frequency boost (pole 0.1Hz and zero 1Hz) to make it more robust.

At t = 3 sec. I increased the gain to the nominal.

Finally the UGF became ~ 60 Hz according to my open loop measurement by diaggui.

However I couldn't make the UGF higher than 60Hz because the more gain caused a instability for some reasons.

Here is a diagram for the green locking.

I used the same VCO box as we setup on the last Friday (see #4189).

Very cool.

But the PLL seems very fishy to me. The ZP-3MH needs 13 dBm to operate correctly. You should change the MODLEVEL input of the VCO so as to make the LO input of the mixer go up to 13 dBm. Then the input from the PD should be ~0 dBm.

Also, the PLL diagram seems to show that you have a 1/f^2 loop: 1/f from the SR560 and 1/f from the Hz->rad conversion ??

Well... The ALS loop is engaged and the error was suppressed.
So, how is the IR error signal stabilized when the IR is brought in to the resonance?

I can see the linear trend of 0.1V/s from 5s to 10s.  This corresponds to 100kHz/s and 13nm
for the residual beat drift and the arm length motion, respectively. That sounds huge. The DC gain must be increased.

Well, the diagram I drew is true. I also have been confused by this 1/f^2 issue in our PLL.

As Rana pointed out, the open-loop TF should become 1/f^2 over most of the frequency range, but it still remains 1/f above 5kHz for some reasons. 

 Need more investigations.

 At the beginning I tried phase-locking the VCO to the beat note without any external filters (i.e. SR560 see here), but I never succeeded.

It was because the hold-in range of the PLL was not sufficiently wide, it could stay locked within frequency range of less than +/- 1MHz from the center frequency of 80 MHz.

This is obviously not good, because the beat note typically fluctuates by more than +/- 3MHz in time scale of 1 sec or so.

  So I decided to put an external filter, SR560,  in order to have a larger DC gain and a higher UGF.

Somehow I unconsciously tuned the SR560 to have a pole at 1Hz with the gain of 2000, which shouldn't work in principle because the open-loop will be 1/f^2.

However I found that the PLL became more robust, in fact it can track the input frequency range of +/- 5MHz.

The open-loop TF is shown above. For comparison I plotted also the open-loop TF wehn it's without the SR560.

I checked the frequency of the VCO output when it was phase-locked to a Marconi, it was healthy (i.e. the same frequency as the input signal from Marconi).

 I haven't yet taken any data for the IR fluctuation when the Xarm is locked by the green locking.

You are right, the DC drift was due to a lack of the DC gain. But don't worry about that, because this issue has been solved.

(DC gain issue)

  The lack of DC gain was because I put an IIR filter called ''DC block" that I made. It has 1/f shape below 30mHz and becomes flat above it.

The purpose of this filter was to avoid a DC kick when it starts feeding back to ETMX.

Usually the output signal from the PLL has an offset, typically ~5V, then this offset is also acquired into the ADC and eventually kicks ETMX through the feedback.

So when I took the time series data I enabled the 'DC block', that's why it drifts slowly.

 After taking the time series, I found that without this 'DC block' technique, the lock can be achieved by appropriately subtracting the offsets with epics numerical values.

This subtraction technique, of course, gave me more stable lock at DC.

(open loop transfer function)

Here is the open-loop TF of the arm locking I measured last night:

The IIR filter chain has the following poles and zeros:

     pole 0.1Hz, 1000Hz,

   zero 1Hz, 30Hz

For the fitting I assume that the ETMX pendulum has a resonance at 1Hz with Q of 5. Also I put the cavity pole at 24 kHz, assuming the finesse is 80 at 532 nm.

I just fitted the gain and the time delay by my eyes.

If I believe the result of the fitting, whole time delay is 330 usec, which sounds pretty large to me.

I found Tara's elog entry that Jenne laser is at PSL Lab.
Since we recently use it frequently, we should be aware where it is now.

I scanned the X arm by changing an offset for the feedback to ETMX while the arm stayed locked by the green locking.

But the resultant plot is still far away from a beautiful one.

Changing the offset broke the lock frequently, so eventually I couldn't measure the stability of the IR-PDH signal at the resonance. 

 The plot above is a result of the scanning. You can see there is a clear resonance at the center of the plot.

However the lock frequently became unstable when I was changing the offset.

It looked like this unstability came from the end PDH lock. I guess there are two possible reasons:

  (1)  feedback range for the laser PZT is not wide enough. Right now the range is limited by a SR560, which has been used for a summing amplifier.

  (2)  Length to Alignment coupling. Pushing ETMX causes a misalignment.

The issue (1) can be easily solved by engaging the temperature feedback, which helps actuating the laser frequency a lot at DC.

The issue (2) will be also solved by well align the IR beam, the arm cavity and the green beam.

Here are some tasks that I want someone to work on during my absence.

1. Y-arm alignment for IR

 Basically we gradually have to move onto the Y-arm locking at some point.

Prior to it we need to align the Y arm for IR. Probably we have to touch PZT1 and PZT2.

It would be very nice if the X-arm alignment also gets improved together with this work. 

2. Temperature feedback with a digital control for X end PDH lock

  Need a temperature feedback not with an analog way but with a digital way because we want to put an offset and the feedback signal at the same time (#4198).

 Right now the temperature control input of the laser is connected to a slow DAC (#3850).

Probably we should plug the feedback signal from the PDH box to the fast ADC (i.e. c1iscex), and then connect a fast DAC to the laser temperature.

This entry maybe helpful.

3. Calibration of optical gain for IR arm locking

 In order to evaluate the performance of the green locking, one of the key points is the IR PDH signal.

Because it tells us how much the motion of the X arm is suppressed at IR when the green lock is engaged.

To get this information in m/sqrtHz, we need to know the optical gain.

4. MC servo characterization and PSL frequency noise measurement

 SInce the green beat note tells us the frequency difference between the MC and the arm in the current configuration, we should know how the MC servo is.

Along with this work, I need someone to measure the PSL frequency noise, when it is locked to the MC over the frequency range from 0.01Hz to 1kHz.

5. PLL characterization 

 Solve this issue (#4195) and make it reliable.

After sitting down for 5 minutes and thinking about it, I realized the names I had been using for internal RFM communication were pretty bad.  It was because looking at a model didn't let you know where the RFM connection was coming from or going to.  So to correct my previous mistakes, I'm instituting the following naming convention for reflected memory, PCIE reflected memory (dolphin) and shared memory names.  These don't actually get used anywhere but the models, and thus don't show up as channel names anywhere else.  They are replaced by raw hex memory locations in the actual code through the use of the IPC file (/opt/rtcds/caltech/c1/chans/ipc/C1.ipc).  However it will make understanding the models easier for anyone looking at them or modifying them.

The new naming convention for RFM and Dolphin channels is as follows.

SITE:Sending Model-Receiving Model_DESCRIPTION_HERE

The description should be unique to that data being transferred and reused if its the same data.  Thus if its transfered to another model, its easy to identify it as the same information.

The model should be the .mdl file name, not the subsystem its a part of.  So SCX is used instead of SUS.  This is to make it easier to track where data is going.

In the unlikely case of multiple models receiving, it should be of the form SITE:Sending Model-Receiving Model 1-Receiving Model 2_DESCRIPTION_HERE.  Seperate models by dashes and description by underscores.

Example:

C1:LSC-RFM_ETMX_LSC

This channel goes from the LSC model (on c1lsc) to the RFM model (on c1sus).  It transfers ETMX LSC position feedback.  The second LSC may seem redundant until we look at the next channel in the chain.

C1:RFM-SCX_ETMX_LSC

This channel goes from the RFM model to the SCX model (on c1iscex). It contains the same information as the first channel, i.e. ETMX LSC position feedback.

I have updated all the models that had RFM and SHMEM connections, as well as adding all the LSC communciation connections to c1rfm.  This includes c1sus, c1rfm, c1mcs, c1ioo, c1gcv, c1lsc, c1scx, c1scy.  I have not yet built all the models since I didn't finish the updates until this afternoon.  I will build and test the code tomorrow morning.

I implemented a slow servo for green laser thermal control on c1scx.mdl. Ch6,7 of ADC and ch6 of DAC are assigned for this servo as below;

Ch6 of ADC: PDH error signal

CH7 of ADC: PZT feedback signal

CH6 of DAC: feedback signal to thermal of green laser

Note that old EPICS themal control cable is not hooked anymore.

I made a simple MEDM screen(...medm/c1scx/master/C1SCX_BCX_SLOW.adl) linked from GREEN medm screen (C1GCV.adl) on sitemap.

During this work, I noticed that some of the epics switch is not recovered by autoburt. What I noticed is filter switch of SUSPOS, SUSPIT, SUSYAW, SDSEN, and all coil output for ETMX.

I had no idea to fix them, probably Joe knows. I guess other suspensitons has the same problems.

1. The dewhitening filter CH6 had no output. I disconnected the cable and put it to the monitor out of the AI filter.
So the dewhitening is not in the loop.

2. I have made a thermal control filter

BANK1: pole 0Hz, zero 1mHz / LF boost stage
BANK2: pole 1mHz, zero 30mHz / LPF stage
BANK3: pole 1Hz, zero 0.1Hz / phase compensation stage
Gain: 0.05

It seems working with the gain of 0.05. As the thermal is very strong, the output has less than 10.
This means the we are effectively only using ~4bit. We need external filter.

Note that output of 30000counts were about 3V at  CH6.

3. Measured End PZT feedback with and without the thermal control. The UGF seems to be 0.2Hz.
The suppression at 10mHz is ~100. This is so far OK.

STATUS:

• Rebooted c1lsc and c1sus. Restarted fb many times.
• c1sus seems working.
• All of the suspensions are damped / Xarm is locked by the green
• Thermal control for the green is working
• c1lsc is frozen
• FB status: c1lsc 0x4000, c1scx/c1scy 0x2bad
• dataviewer not working

1. DataViewer did not work for the LSC channels (liek TRX)

2. Rebooted LSC. There was no instruction for the reboot on Wiki. But somehow the rebooting automatically launched the processes.

3. However, rebooting LSC stopped C1SUS processes working

4. Rebooted C1SUS. Despite the rebooting description on wiki, none of the FE processes coming up.

5. Probably, I was not enough patient to wait for the completion of dorphine_wait? Rebooted C1SUS again.

6. Yes. That was true. This time I wait for everything going up automatically. Now all of c1pemfe,c1rfmfe,c1mcsfe,c1susfe,c1x02fe are running.
FB status for c1sus processes all green.

7. burtrestored c1pemfe,c1rfmfe,c1mcsfe,c1susfe,c1x02fe with the snapshot on Jan 25 12:07, 2010.

8. All of the OSEM filters are off, and the servo switches are incorrectly on. Pushing many buttons to restore the suspensions.

9. I asked Suresh to restore half of the suspensions.

10. The suspensions were restored and damped. However, c1lsc is still freezed.

11. Rebooting c1lsc freezed the frontends on c1sus. We redid the process No. 5 to No.10

12. c1x04 seems working. c1lsc, however, is still frozen. We decided to leave C1LSC in this state.

I have put an offset of 1000 counts to C1:SUS-ETMX_ALS_OFFSET. This actually misalign the mirror a lot.

While the offset is applied. I adjusted the balance of the coil matrix.
UL 1.580 UR 0.620
LL 0.420 LR 1.380

> ezcaread C1:SUS-ETMX_TO_COIL_0_0_GAIN
C1:SUS-ETMX_TO_COIL_0_0_GAIN = 1.58
> ezcaread C1:SUS-ETMX_TO_COIL_0_1_GAIN
C1:SUS-ETMX_TO_COIL_0_1_GAIN = 0.62
> ezcaread C1:SUS-ETMX_TO_COIL_0_2_GAIN
C1:SUS-ETMX_TO_COIL_0_2_GAIN = 0.42
> ezcaread C1:SUS-ETMX_TO_COIL_0_3_GAIN
C1:SUS-ETMX_TO_COIL_0_3_GAIN = 1.38

Now, we can keep TEM00 for green with +/-1000counts of push although the fast step of the offset make the lock lost.

It turned out that the step longitudinal input temporary misalign the mirror in pitch because the length and pitch are coupled.
I guess that we don't excite pitch if we push the mirror slowly. Eventually, we need f2p transfer function adjusted in the output matrix.

Whether or not it's as clean as we'd like, it's really nice to see this result with real data.

Looking at dmesg on c1lsc, it looks like the model is starting, but then eventually times out due to a long ADC wait. 

[  114.778001] c1lsc: cycle 45 time 23368; adcWait 14; write1 0; write2 0; longest write2 0
[  114.779001] c1lsc: ADC TIMEOUT 0 1717 53 181

I'm not sure what caused the time out, although there about 20 messages indicating a failed time stamp read from c1sus (its sending TRX information to c1lsc via the dolphin connection) before the time out.

Not seeing any other obvious error messages, I killed the dead c1lsc model by typing:

sudo rmmod c1lscfe

I then tried starting just the front end model again by going to the /opt/rtcds/caltech/c1/target/c1lsc/bin/ directory and typing:

sudo insmod c1lscfe.ko

This started up just the FE again (I didn't use the restart script because the EPICs processes were running fine since we had non-white channels).  At the moment, c1lsc is now running and I see green lights and 0x0 for FB0 status  on the C1LSC_GDS_TP screen.

At this point I'm not sure what caused the timeout.  I'll be adding some more trouble shooting steps to the wiki though.  Also, c1scx, c1scy are probably in need of restart to get them properly sync'd to the framebuilder.

I did a quick test on dataviewer and can see LSC channels such as C1:LSC-TRX_IN1, as well other channels on C1SUS such as BS sensors channels.

This is definitely a nice magic to know as the rebooting causes too much hustles.

Also, you and I should spend an hour in the afternoon to add the suspension swtches to the burt requests.

So apparently with the current Dolphin drivers, when one of the nodes goes down (say c1lsc), it causes all the other nodes to freeze for up to 20 seconds.

This 20 seconds can force a model to go over the 60 microseconds limit and is sufficiently long enough to force the FE to time out.  Alex and Rolf have been working with the vendors to get this problem fixed, as having all your front ends go down because you rebooted a single computer is bad.

[40184.120912] c1rfm: sync error my=0x3a6b2d5d00000000 remote=0x0
[40184.120914] c1rfm: sync error my=0x3a6b2d5d00000000 remote=0x0
[44472.627831] c1pem: ADC TIMEOUT 0 7718 38 7782
[44472.627835] c1mcs: ADC TIMEOUT 0 7718 38 7782
[44472.627849] c1sus: ADC TIMEOUT 0 7718 38 7782
[44472.644677] c1rfm: cycle 1945 time 17872; adcWait 15; write1 0; write2 0; longest write2 0
[44472.644682] c1x02: cycle 7782 time 17849; adcWait 12; write1 0; write2 0; longest write2 0
[44472.646898] c1rfm: ADC TIMEOUT 0 8133 5 7941


The solution for the moment is to start the computers at exactly the same time, so the dolphin is up before the front ends, or start the models by hand after the computer is up and dolphin running, but after they have timed out.  This is done by:

sudo rmmod c1SYSfe

sudo insmod /opt/rtcds/caltech/c1/target/c1SYS/bin/c1SYSfe.ko

Alex and Rolf have been working with the vendors to get this fixed, and we may simply need to update our Dolphin drivers.  I'm trying to get in contact with them and see if this is the case.