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ID Date Authordown Type Category Subject
  16037   Thu Apr 15 17:24:08 2021 JonUpdateCDSUpdated c1auxey wiring plan

I've updated the c1auxey wiring plan for compatibility with the new suspension electronics. Specifically it is based on wiring schematics for the new HAM-A coil driver (D1100117), satellite amplifier (D1002818), and HV bias driver (D1900163).


  • The PDMon, VMon, CoilEnable, and BiasAdj channels all move from DB37 to various DB9 breakout boards.
  • The DB9 cables (x2) connecting the CoilEnable channels to the coil drivers must be spliced with the dewhitening switching signals from the RTS.
  • As suggested, I added five new BI channels to monitor the state of the CoilEnable switches. For lack of a better name, they follow the naming convention C1:SUS-ETMY_xx_ENABLEMon.

@Yehonathan can proceed with wiring the chassis.


I finished prewiring the new c1auxey Acromag chassis (see attached pictures). I connected all grounds to the DIN rail to save some wiring. The power switches and LEDs work as expected.

I configured the DAQ modules using the old windows machine. I configured the gateway to be The host machine still needs to be setup.

Next, the feedthroughs need to be wired and the channels need to be bench tested.

Attachment 1: C1AUXEY_Chassis_Feedthroughs_-_By_Connector.pdf
  16090   Wed Apr 28 11:31:40 2021 JonUpdateVACEmpty N2 Tanks

I checked out what happened on c1vac. There are actually two independent monitoring codes running:

  1. The interlock service, which monitors the line directly connected to the valves.
  2. A seaparate convenience mailer, running as a cronjob, that monitors the tanks.

The interlocks did not trip because the low-pressure delivery line, downstream of the dual-tank regulator, never fell below the minimum pressure to operate the valves (65 PSI). This would have eventually occurred, had Jordan been slower to replace the tanks. So I see no problem with the interlocks.

On the other hand, the N2 mailer should have sent an email at 2021-04-18 15:00, which was the first time C1:Vac-N2T1_pressure dropped below the 600 PSI threshold. N2check.log shows these pressures were recorded at this time, but does not log that an email was sent. Why did this fail? Not sure, but I found two problems which I did fix:

  • One was that the code was checking the sensor on the low-pressure side (C1:Vac-N2_pressure; nominally 75 PSI) against the same 600 PSI threshold as the tanks. This channel should either be removed or a separate threshold (65 PSI) defined just for it. I just removed it from the list because monitoring of this channel is redundant with the interlock service. This does not explain the failure to send an email.
  • The second issue was that the pyN2check.sh script appeared to be calling Python 3 to run a Python 2 script. At least that was the situation when I tested it, and this was causing it to fail partway through. This might well explain the problem with no email. I explicitly set python --> python2 in the shell script.

The code then ran fine for me when I retested it. I don't see any further issues.


Installed T2 today, and leaked checked the entire line. No issues found. It could have been a bad valve on the tank itself. Monitored T2 pressure for ~2 hours to see if there was any change. All seems ok.


When I came into the lab this morning, I noticed that both N2 tanks were empty. I had swapped one on Friday (4-16-21) before I left the lab. Looking at the logs, the right tank (T2) sprung a leak shortly shortly after install. I leak checked the tank coupling after install but did not see a leak. There could a leak further down the line, possibly at the pressure transducer.

The left tank (T1) emptied normally over the weekend, and I quickly swapped the left tank for a full one, and is curently at ~2700 psi. It was my understanding that if both tanks emptied, V1 would close automatically and a mailer would be sent out to the 40m group. I did not receive an email over the weekend, and I checked the Vac status just now and V1 was still open.

I will keep an eye on the tank pressure throughout the day, and will try to leak check the T2 line this afternoon, but someone should check the vacuum interlocks and verify.


  16093   Thu Apr 29 10:51:35 2021 JonUpdateCDSI/O Chassis Assembly


Yesterday I unpacked and installed the three 18-bit DAC cards received from Hanford. I then repeated the low-level PCIe testing outlined in T1900700, which is expanded upon below. I did not make it to DAC-ADC loopback testing because these tests in fact revealed a problem with the new hardware. After a combinatorial investigation that involved swapping cards around between known-to-be-working PCIe slots, I determined that one of the three 18-bit DAC cards is bad. Although its "voltage present" LED illuminates, the card is not detected by the host in either I/O chassis.

I installed one of the two working DACs in the c1bhd chassis. This now 100% completes this system. I installed the other DAC in the c1sus2 chassis, which still requires four more 18-bit DACs. Lastly, I reran the PCIe tests for the final configurations of both chassis.

PCIe Card Detection Tests

For future reference, below is the set of command line tests to verify proper detection and initialization of ADC/DAC/BIO cards in I/O chassis. This summarizes the procedure described in T1900700 and also adds the tests for 18-bit DAC and 32-channel BO cards, which are not included in the original document.

Each command should be executed on the host machine with the I/O chassis powered on:

$ sudo lspci -v | grep -B 1 xxxx

where xxxx is a four-digit device code given in the following table.

Device Device Code
General Standards 16-bit ADC 3101
General Standards 16-bit DAC 3120
General Standards 18-bit DAC 3357
Contec 16-channel BIO 8632
Contec 32-channel BO 86e2
Dolphin IPC host adapter 0101

The command will return a two-line entry for each PCIe device of the specified type that is detected. For example, on a system with a single ADC this command should return:

10:04.0 Bridge: PLX Technology, Inc. PCI9056 32-bit 66MHz PCI IOBus Bridge (rev ac)
             Subsystem: PLX Technology, Inc. Device 3101
  16116   Tue May 4 07:38:36 2021 JonUpdateCDSI/O Chassis Assembly

IOP models created

With all the PCIe issues now resolved, yesterday I proceeded to build an IOP model for each of new FEs. I assigned them names and DCUIDs consist with the 40m convention, listed below. These models currently exist on only the cloned copy of /opt/rtcds running on the test stand. They will be copied to the main network disk later, once the new systems are fully tested.

Model Host CPU DCUID
c1x06 c1bhd 1 23
c1x07 c1sus2 1 24

The models compile and install successfully. The RCG runtime diagnostics indicate that all is working except for the timing synchronization and DAQD data transmission. This is as expected because neither of these have been set up yet.

Timing system set-up

The next step is to provide the 65 kHz clock signals from the timing fanout via LC optical fiber. I overlooked the fact that an SPX optical transceiver is required to interface the fiber to the timing slave board. These were not provided with the timing slaves we received. The timing slaves require a particular type of transceiver, 100base-FX/OC-3, which we did not have on hand. (For future reference, there is a handy list of compatible transceivers in E080541, p. 14.) I placed a Digikey order for two Finisar FTLF1217P2BTL, which should arrive within two days.

Attachment 1: Screen_Shot_2021-05-03_at_4.16.06_PM.png
  16130   Tue May 11 16:29:55 2021 JonUpdateCDSI/O Chassis Assembly

Timing system set-up

The next step is to provide the 65 kHz clock signals from the timing fanout via LC optical fiber. I overlooked the fact that an SPX optical transceiver is required to interface the fiber to the timing slave board. These were not provided with the timing slaves we received. The timing slaves require a particular type of transceiver, 100base-FX/OC-3, which we did not have on hand. (For future reference, there is a handy list of compatible transceivers in E080541, p. 14.) I placed a Digikey order for two Finisar FTLF1217P2BTL, which should arrive within two days.

Today I brought and installed the new optical transceivers (Finisar FTLF1217P2BTL) for the two timing slaves. The timing slaves appear to phase-lock to the clocking signal from the master fanout. A few seconds after each timing slave is powered on, its status LED begins steadily blinking at 1 Hz, just as in the existing 40m systems.

However, some other timing issue remains unresolved. When the IOP model is started (on either FE), the DACKILL watchdog appears to start in a tripped state. Then after a few minutes of running, the TIM and ADC indicators go down as well. This makes me suspect the sample clocks are not really phase-locked. However, the models do start up with no error messages. Will continue to debug...

Attachment 1: Screen_Shot_2021-05-11_at_3.03.42_PM.png
  16154   Sun May 23 18:28:54 2021 JonUpdateCDSOpto-isolator for c1auxey

The new HAM-A coil drivers have a single DB9 connector for all the binary inputs. This requires that the dewhitening switching signals from the fast system be spliced with the coil enable signals from c1auxey. There is a common return for all the binary inputs. To avoid directly connecting the grounds of the two systems, I have looked for a suitable opto-isolator for the c1auxey signals.

I best option I found is the Ocean Controls KTD-258, a 4-channel, DIN-rail-mounted opto-isolator supporting input/output voltages of up to 30 V DC. It is an active device and can be powered using the same 15 V supply as is currently powering both the Acromags and excitation. I ordered one unit to be trialed in c1auxey. If this is found to be good solution, we will order more for the upgrades of c1auxex and c1susaux, as required for compatibility with the new suspension electronics.

  16166   Fri May 28 10:54:59 2021 JonUpdateCDSOpto-isolator for c1auxey

I have received the opto-isolator needed to complete the new c1auxey system. I left it sitting on the electronics bench next to the Acromag chassis.

Here is the manufacturer's wiring manual. It should be wired to the +15V chassis power and to the common return from the coil driver, following the instructions herein for NPN-style signals. Note that there are two sets of DIP switches (one on the input side and one on the output side) for selecting the mode of operation. These should all be set to "NPN" mode.

Attachment 1: optoisolator.jpeg
  16167   Fri May 28 11:16:21 2021 JonUpdateCDSFront-End Assembly and Testing

An update on recent progress in the lab towards building and testing the new FEs.

1. Timing problems resolved / FE BIOS changes

The previously reported problem with the IOPs losing sync after a few minutes (16130) was resolved through a change in BIOS settings. However, there are many required settings and it is not trivial to get these right, so I document the procedure here for future reference.

The CDS group has a document (T1300430) listing the correct settings for each type of motherboard used in aLIGO. All of the machines received from LLO contain the oldest motherboards: the Supermicro X8DTU. Quoting from the document, the BIOS must be configured to enforce the following:

• Remove hyper-threading so the CPU doesn’t try to run stuff on the idle core, as hyperthreading simulate two cores for every physical core.
• Minimize any system interrupts from hardware, such as USB and Serial Ports, that might get through to the ‘idled’ core. This is needed on the older machines.
• Prevent the computer from reducing the clock speed on any cores to ‘save power’, etc. We need to have a constant clock speed on every ‘idled’ CPU core.

I generally followed the T1300430 instructions but found a few adjustments were necessary for diskless and deterministic operation, as noted below. The procedure for configuring the FE BIOS is as follows:

  1. At boot-up, hit the delete key to enter the BIOS setup screen.
  2. Before changing anything, I recommend photographing or otherwise documenting the current working settings on all the subscreens, in case for some reason it is necessary to revert.
  3. T1300430 assumes the process is started from a known state and lists only the non-default settings that must be changed. To put the BIOS into this known state, first navigate to Exit > Load Failsafe Defaults > Enter.
  4. Configure the non-default settings following T1300430 (Sec. 5 for the X8DTU motherboard). On the IPMI screen, set the static IP address and netmask to their specific assigned values, but do set the gateway address to all zeros as the document indicates. This is to prevent the IPMI from trying to initiate outgoing connections.
  5. For diskless booting to continue to work, it is also necessary to set Advanced > PCI/PnP Configuration > Load Onboard LAN 1 Option Rom > Enabled.
  6. I also found it was necessary to re-enable IDE direct memory access and WHEA (Windows Hardware Error Architecture) support. Since these machines have neither hard disks nor Windows, I have no idea why these are needed, but I found that without them, one of the FEs would hang during boot about 50% of the time.
    • Advanced > PCI/PnP configuration > PCI IDE BusMaster  > Enabled.
    • Advanced > ACPI Configuration > WHEA Support > Enabled.

After completing the BIOS setup, I rebooted the new FEs about six times each to make sure the configuration was stable (i.e., would never hang during boot).

2. User models created for FE testing

With the timing issue resolved, I proceeded to build basic user models for c1bhd and c1sus2 for testing purposes. Each one has a simple structure where M ADC inputs are routed through IIR filters to an output matrix, which forms linear signal combinations that are routed to N DAC outputs. This is shown in Attachment 1 for the c1bhd case, where the signals from a single ADC are conditioned and routed to a single 18-bit DAC. The c1sus2 case is similar; however the Contec BO modules still needed to be added to this model.

The FEs are now running two models each: the IOP model and one user model. The assigned parameters of each model are documented below.

Model Host CPU DCUID Path
c1x06 c1bhd 1 23 /opt/rtcds/userapps/release/cds/c1/models/c1x06.mdl
c1x07 c1sus2 1 24 /opt/rtcds/userapps/release/cds/c1/models/c1x07.mdl
c1bhd c1bhd 2 25 /opt/rtcds/userapps/release/isc/c1/models/c1bhd.mdl
c1sus2 c1sus2 2 26 /opt/rtcds/userapps/release/sus/c1/models/c1sus2.mdl

The user models were compiled and installed following the previously documented procedure (15979). As shown in Attachment 2, all the RTS processes are now working, with the exception of the DAQ server (for which we're still awaiting hardware). Note that these models currently exist only on the cloned copy of the /opt/rtcds disk running on the test stand. The plan is to copy these models to the main 40m disk later, once the new FEs are ready to be installed.

3. AA and AI chassis installed

I installed several new AA and AI chassis in the test stand to interface with the ADC and DAC cards. This includes three 16-bit AA chassis, one 16-bit AI chassis, and one 18-bit AI chassis, as pictured in Attachment 3. All of the AA/AI chassis are powered by one of the new 15V DC power strips connected to a bench supply, which is housed underneath the computers as pictured in Attachment 4.

These chassis have not yet been tested, beyond verifying that the LEDs all illuminate to indicate that power is present.

Attachment 1: c1bhd.png
Attachment 2: gds_tp.png
Attachment 3: teststand.jpeg
Attachment 4: bench_supply.jpeg
  16185   Sun Jun 6 08:42:05 2021 JonUpdateCDSFront-End Assembly and Testing

Here is an update and status report on the new BHD front-ends (FEs).


The changes to the FE BIOS settings documented in [16167] do seem to have solved the timing issues. The RTS models ran for one week with no more timing failures. The IOP model on c1sus2 did die due to an unrelated "Channel hopping detected" error. This was traced back to a bug in the Simulink model, where two identical CDS parts were both mapped to ADC_0 instead of ADC_0/1. I made this correction and recompiled the model following the procedure in [15979].

Model naming standardization

For lack of a better name, I had originally set up the user model on c1sus2 as "c1sus2.mdl" This week I standardized the name to follow the three-letter subsystem convention, as four letters lead to some inconsistency in the naming of the auto-generated MEDM screens. I renamed the model c1sus2.mdl -> c1su2.mdl. The updated table of models is below.

Model Host CPU DCUID Path
c1x06 c1bhd 1 23 /opt/rtcds/userapps/release/cds/c1/models/c1x06.mdl
c1x07 c1sus2 1 24 /opt/rtcds/userapps/release/cds/c1/models/c1x07.mdl
c1bhd c1bhd 2 25 /opt/rtcds/userapps/release/isc/c1/models/c1bhd.mdl
c1su2 c1su2 2 26 /opt/rtcds/userapps/release/sus/c1/models/c1su2.mdl

Renaming an RTS model requires several steps to fully propagate the change, so I've documented the procedure below for future reference.

On the target FE, first stop the model to be renamed:

controls@c1sus2$ rtcds stop c1sus2

Then, navigate to the build directory and run the uninstall and cleanup scripts:

controls@c1sus2$ cd /opt/rtcds/caltech/c1/rtbuild/release
controls@c1sus2$ make uninstall-c1sus2
controls@c1sus2$ make clean-c1sus2

Unfortunately, the uninstall script does not remove every vestige of the old model, so some manual cleanup is required. First, open the file /opt/rtcds/caltech/c1/target/gds/param/testpoint.par and manually delete the three-line entry corresponding to the old model:


If this is not removed, reinstallation of the renamed model will fail because its assigned DCUID will appear to already be in use. Next, find all relics of the old model using:

controls@c1sus2$ find /opt/rtcds/caltech/c1 -iname "*sus2*"

and manually delete each file and subdirectory containing the "sus2" name. Finally, rename, recompile, reinstall, and relaunch the model:

controls@c1sus2$ cd /opt/rtcds/userapps/release/sus/c1/models
controls@c1sus2$ mv c1sus2.mdl c1su2.mdl
controls@c1sus2$ cd /opt/rtcds/caltech/c1/rtbuild/release
controls@c1sus2$ make c1su2
controls@c1sus2$ make install-c1su2
controls@c1sus2$ rtcds start c1su2

Sitemap screens

I used a tool developed by Chris, mdl2adl, to auto-generate a set of temporary sitemap/model MEDM screens. This package parses each Simulink file and generates an MEDM screen whose background is an .svg image of the Simulink model. Each object in the image is overlaid with a clickable button linked to the auto-generated RTS screens. An example of the screen for the C1BHD model is shown in Attachment 1. Having these screens will make the testing much faster and less user-error prone.

I generated these screens following the instructions in Chris' README. However, I ran this script on the c1sim machine, where all the dependencies including Matlab 2021 are already set up. I simply copied the target .mdl files to the root level of the mdl2adl repo, ran the script (./mdl2adl.sh c1x06 c1x07 c1bhd c1su2), and then copied the output to /opt/rtcds/caltech/c1/medm/medm_teststand. Then I redefined the "sitemap" environment variable on the chiara clone to point to this new location, so that they can be launched in the teststand via the usual "sitemap" command.

Current status and plans

Is it possible to convert 18-bit AO channels to 16-bit?

Currently, we are missing five 18-bit DACs needed to complete the c1sus2 system (the c1bhd system is complete). Since the first shipment, we have had no luck getting additional 18-bit DACs from the sites, and I don't know when more will become available. So, this week I took an inventory of all the 16-bit DACs available at the 40m. I located four 16-bit DACs, pictured in Attachment 2. Their operational states are unknown, but none were labeled as known not to work.

The original CDS design would call for 40 more 18-bit DAC channels. Between the four 16-bit DACs there are 64 channels, so if only 3/4 of these DACs work we would have enough AO channels. However, my search turned up zero additional 16-bit DAC adapter boards. We could check if first Rolf or Todd have any spares. If not, I think it would be relatively cheap and fast to have four new adapters fabricated.

DAQ network limitations and plan

To get deeper into the signal-integrity aspect of the testing, it is going to be critical to get the secondary DAQ network running in the teststand. Of all the CDS tools (Ndscope, Diaggui, DataViewer, StripTool), only StripTool can be used without a functioning NDS server (which, in turn, requires a functioning DAQ server). StripTool connects directly to the EPICS server run by the RTS process. As such, StripTool is useful for basic DC tests of the fast channels, but it can only access the downsampled monitor channels. Ian and Anchal are going to carry out some simple DAC-to-ADC loopback tests to the furthest extent possible using StripTool (using DC signals) and will document their findings separately.

We don't yet have a working DAQ network because we are still missing one piece of critical hardware: a 10G switch compatible with the older Myricom network cards. In the older RCG version 3.x used by the 40m, the DAQ code is hardwired to interface with a Myricom 10G PCIe card. I was able to locate a spare Myricom card, pictured in Attachment 3, in the old fb machine. Since it looks like it is going to take some time to get an old 10G switch from the sites, I went ahead and ordered one this week. I have not been able to find documentation on our particular Myricom card, so it might be compatible with the latest 10G switches but I just don't know. So instead I bought exactly the same older (discontinued) model as is used in the 40m DAQ network, the Netgear GSM7352S. This way we'll also have a spare. The unit I bought is in "like-new" condition and will unfortunately take about a week to arrive.

Attachment 1: c1bhd.png
Attachment 2: 16bit_dacs.png
Attachment 3: myricom.png
  16186   Sun Jun 6 12:15:16 2021 JonUpdateCDSOpto-isolator for c1auxey

Since this Ocean Controls optoisolator has been shown to be compatible, I've gone ahead and ordered 10 more:

  • (1) to complete c1auxey
  • (2) for the upgrade of c1auxex
  • (7) for the upgrade of c1susaux

They are expected to arrive by Wednesday.

  16188   Sun Jun 6 16:33:47 2021 JonUpdateCDSBI channels on c1auxey

There is still an open issue with the BI channels not read by EPICS. They can still be read by the Windows machine though.

I looked into the issue that Yehonathan reported with the BI channels. I found the problem was with the .cmd file which sets up the Modbus interfacing of the Acromags to EPICS (/cvs/cds/caltech/target/c1auxey1/ETMYaux.cmd).

The problem is that all the channels on the XT1111 unit are being configured in Modbus as output channels. While it is possible to break up the address space of a single unit, so that some subset of channels are configured as inputs and another as outputs, I think this is likely to lead to mass confusion if the setup ever has to be modified. A simpler solution (and the convention we adopted for previous systems) is just to use separate Acromag units for BI and BO signals.

Accordingly, I updated the wiring plan to include the following changes:

  • The five EnableMon BI channels are moved to a new Acromag XT1111 unit (BIO01), whose channels are configured in Modbus as inputs.
  • One new DB37M connector is added for the 11 spare BI channels on BIO01.
  • The five channels freed up on the existing XT1111 (BIO00) are wired to the existing connector for spare BO channels.

So, one more Acromag XT1111 needs to be added to the c1auxey chassis, with the wiring changes as noted above. I have already updated the .cmd and EPICS database files in /cvs/cds/caltech/target/c1auxey1 to reflect these changes.

  16225   Fri Jun 25 14:06:10 2021 JonUpdateCDSFront-End Assembly and Testing


Here is the final summary (from me) of where things stand with the new front-end systems. With Anchal and Ian's recent scripted loopback testing [16224], all the testing that can be performed in isolation with the hardware on hand has been completed. We currently have no indication of any problem with the new hardware. However, the high-frequency signal integrity and noise testing remains to be done.

I detail those tests and link some DTT templates for performing them below. We have not yet received the Myricom 10G network card being sent from LHO, which is required to complete the standalone DAQ network. Thus we do not have a working NDS server in the test stand, so cannot yet run any of the usual CDS tools such as Diaggui. Another option would be to just connect the new front-ends to the 40m Martian/DAQ networks and test them there.

Final Hardware Configuration

Due to the unavailablity of the 18-bit DACs that were expected from the sites, we elected to convert all the new 18-bit AO channels to 16-bit. I was able to locate four unused 16-bit DACs around the 40m [16185], with three of the four found to be working. I was also able to obtain three spare 16-bit DAC adapter boards from Todd Etzel. With the addition of the three working DACs, we ended up with just enough hardware to complete both systems.

The final configuration of each I/O chassis is as follows. The full setup is pictured in Attachment 1.

Component Qty Installed Qty Installed
16-bit ADC 1 2
16-bit ADC adapter 1 2
16-bit DAC 1 3
16-bit DAC adapter 1 3
16-channel BIO 1 1
32-channel BO 0 6

This hardware provides the following breakdown of channels available to user models:

Channel Type Channel Count Channel Count
16-bit AI* 31 63
16-bit AO 16 48
BO 0 192

*The last channel of the first ADC is reserved for timing diagnostics.

The chassis have been closed up and their permanent signal cabling installed. They do not need to be reopened, unless future testing finds a problem.

RCG Model Configuration

An IOP model has been created for each system reflecting its final hardware configuration. The IOP models are permanent and system-specific. When ready to install the new systems, the IOP models should be copied to the 40m network drive and installed following the RCG-compilation procedure in [15979]. Each system also has one temporary user model which was set up for testing purposes. These user models will be replaced with the actual SUS, OMC, and BHD models when the new systems are installed.

The current RCG models and the action to take with each one are listed below:

Model Name Host CPU DCUID Path (all paths local to chiara clone machine) Action
c1x06 c1bhd 1 23 /opt/rtcds/userapps/release/cds/c1/models/c1x06.mdl Copy to same location on 40m network drive; compile and install
c1x07 c1sus2 1 24 /opt/rtcds/userapps/release/cds/c1/models/c1x07.mdl Copy to same location on 40m network drive; compile and install
c1bhd c1bhd 2 25 /opt/rtcds/userapps/release/isc/c1/models/c1bhd.mdl Do not copy; replace with permanent OMC/BHD model(s)
c1su2 c1su2 2 26 /opt/rtcds/userapps/release/sus/c1/models/c1su2.mdl Do not copy; replace with permanent SUS model(s)

Each front-end can support up to four user models.

Future Signal-Integrity Testing

Recently, the CDS group has released a well-documented procedure for testing General Standards ADC and DACs: T2000188. They've also automated the tests using a related set of shell scripts (T2000203). Unfortnately I don't believe these scripts will work at the 40m, as they require the latest v4.x RCG.

However, there is an accompanying set of DTT templates that could be very useful for accelerating the testing. They are available from the LIGO SVN (log in with username: "first.last@LIGO.ORG"). I believe these can be used almost directly, with only minor updates to channel names, etc. There are two classes of DTT-templated tests:

  1. DAC -> ADC loopback transfer functions
  2. Voltage noise floor PSD measurements of individual cards

The T2000188 document contains images of normal/passing DTT measurements, as well as known abnormalities and failure modes. More sophisticated tests could also be configured, using these templates as a guiding example.

Hardware Reordering

Due to the unexpected change from 18- to 16-bit AO, we are now short on several pieces of hardware:

  • 16-bit AI chassis. We originally ordered five of these chassis, and all are obligated as replacements within the existing system. Four of them are now (temporarily) in use in the front-end test stand. Thus four of the new 18-bit AI chassis will need to be retrofitted with 16-bit hardware.
  • 16-bit DACs. We currently have exactly enough DACs. I have requested a quote from General Standards for two additional units to have as spares.
  • 16-bit DAC adapters. I have asked Todd Etzel for two additional adapter boards to also have as spares. If no more are available, a few more should be fabricated.
Attachment 1: test_stand.JPG
  16226   Fri Jun 25 19:14:45 2021 JonUpdateEquipment loanZurich Instruments analyzer

I returned the Zurich Instruments analyzer I borrowed some time ago to test out at home. It is sitting on first table across from Steve's old desk.

Attachment 1: ZI.JPG
  602   Mon Jun 30 13:48:47 2008 John, RobConfigurationPSLDon't put the bin in front of the air conditioning unit
We spotted that the laser power was dropping.

The air conditioning unit was blocked by the blue bin/trash can/cestino causing the laser head temp to increase by 2 degrees.

Let's be careful about this in the future.
Attachment 1: binremoval.png
  711   Tue Jul 22 03:03:22 2008 John, RobUpdatePSLFSS open loop transfer function
With the common gain slider maxed out the unity gain frequency is 58kHz.

The reference cavity refl diode appears to be okay. RF OUT/ TEST IN transfer function was normal.
There is a ~220mV offset in the RF out. We removed this using a coupler - no change. We also checked the
diode->FSS cable.

Tomorrow I'll take a closer look at the board.
  715   Tue Jul 22 13:16:09 2008 John, RobUpdatePSLFSS open loop transfer function

With the common gain slider maxed out the unity gain frequency is 58kHz.

The reference cavity refl diode appears to be okay. RF OUT/ TEST IN transfer function was normal.
There is a ~220mV offset in the RF out. We removed this using a coupler - no change. We also checked the
diode->FSS cable.

Tomorrow I'll take a closer look at the board.

Should note that the UGF of 58kHz was measured with the test cable (from RFPD to board), so the demod phase was presumably sub-optimal.
  612   Tue Jul 1 12:08:38 2008 John, JoeConfigurationPSLPMC input PD
Joe and I switched cables so that the PMCR screen actually shows reflection not transmission.

The trans camera had a BNC connected to "video out" labelled PMC input PD. The video signal
going to the monitors does not come from "video out", it comes out the "DC in/sync" cable.
As far as we can see this diode doesn't exist. Where should the PMC input PD BNC cable be
  8757   Wed Jun 26 15:11:08 2013 John ZweizigUpdateSUSNDS2 Status


I've restarted the NDS2 process on Megatron so that we can use it for getting past data and eventually from outside the 40m.

1) from /home/controls/nds2 (which is not a good place for programs to run) I ran nds2-megatron/start-nds2

2) this is just a script that runs the binary from /usr/bin/ and then leaves a log file in ~/nds2/log/

3) I tested with DTT that I could access megatron:31200 and get data that way.

There is a script in usr/bin called nds2_nightly which seems to be the thing we should run by cron to get the channel list to get updated, but I' m not sure. Let's see if we can get an ELOG entry about how this works.

Then we want Jamie to allow some kind of tunneling so that the 40m data can be accessed from outside, etc.

 I have done the following:

  * installed the nds2-client in /ligo/apps/nds2-client

  * moved the nds2 configuration directories to /ligo/apps/nds2/nds2-megatron

  * set up a cron job to update the channel list every morning at 5 am. The cron line is:

     15 5 * * * /usr/bin/nds2_nightly /ligo/apps/nds2/channel-tracker /ligo/apps/nds2/nds2-megatron

    cron will send an email each time the channel list changes, at which point you will have to restart the server with:

     cd /ligo/apps/nds2/nds2-megatron
     pkill nds2

  * restarted nds2 with updated channel lists.

  8787   Fri Jun 28 17:33:33 2013 John ZweizigUpdateSUSNDS2 Status



I've restarted the NDS2 process on Megatron so that we can use it for getting past data and eventually from outside the 40m.

1) from /home/controls/nds2 (which is not a good place for programs to run) I ran nds2-megatron/start-nds2

2) this is just a script that runs the binary from /usr/bin/ and then leaves a log file in ~/nds2/log/

3) I tested with DTT that I could access megatron:31200 and get data that way.

There is a script in usr/bin called nds2_nightly which seems to be the thing we should run by cron to get the channel list to get updated, but I' m not sure. Let's see if we can get an ELOG entry about how this works.

Then we want Jamie to allow some kind of tunneling so that the 40m data can be accessed from outside, etc.

 I have done the following:

  * installed the nds2-client in /ligo/apps/nds2-client

  * moved the nds2 configuration directories to /ligo/apps/nds2/nds2-megatron

  * set up a cron job to update the channel list every morning at 5 am. The cron line is:

     15 5 * * * /usr/bin/nds2_nightly /ligo/apps/nds2/channel-tracker /ligo/apps/nds2/nds2-megatron

    cron will send an email each time the channel list changes, at which point you will have to restart the server with:

     cd /ligo/apps/nds2/nds2-megatron
     pkill nds2

  * restarted nds2 with updated channel lists.

 I have set the cron job up to restart the nds2 server automatically if the channel list changes. The only change is that the cron command was changes to /ligo/apps/nds2/nds2-megatron/test-restart.


  9216   Mon Oct 7 18:32:01 2013 John ZweizigSummaryComputer Scripts / Programsnds2 installed, restarted

The upgrade of megatron broke the nds2 service. I have fixed things by

  1) installing the latest version of framecpp (1.19.32) from the lsc debian repository (this was necessary because I couldn't link to the existing version)

  2) built nds2-server-0.5.11 and installed it in the system directories (/usr/bin)

  3) there were a few scripts/links/etc that didn't seem to be set up correctly and I fixed them to correspond with my preious message.

 nds2 is now running and the channel list should be updated regularly and the service restarted as appropriate.


  14111   Sat Jul 28 22:16:49 2018 John MartynUpdate Characterization of Transimpedance Amplifier

Kevin and I meaured the transfer function of the photodiode circuit using the Jenne laser and agilent in the 40m lab. The attached figures depict our measured transfer function over the modulation frequency ranges of 30kHz-30MHz and 1kHz-30MHz when the power of the laser was set to 69 and 95 μW. These plots indicate a clear roll off frequency around 300 kHz. In addition, the plots beginning at 1kHz display unstable behavior at frequencies below 30kHz. I am not sure why there is such a sharp change in the transfer function around 30kHz, but I suspect this to be due to an issue with the agilent or photodiode. 

Attachment 1: PD_TF1.pdf
Attachment 2: PD_TF2.pdf
Attachment 3: PD_and_TIA_Transfer_Function_Measurements.zip
  97   Mon Nov 12 23:44:19 2007 JohnUpdatePSLISS


After John soldered a 3.7 MHz notch filter onto the ISS board, I took a quick TF and RIN measurement. The out-of-loop RIN is attached, including a dark noise trace, and with the gain slider at 10dB. The UGF is 35kHz with a phase margin of 30deg. John is currently doing a more thorough inspection, and will detail his findings in a subentry.

No progress on the ISS tonight. I tried to implement a new filter (attached)to try and gain some phase before the notch. If anything this made things worse. More work is needed.

The ISS loop is off and the power is off at the chassis.
Attachment 1: ISSfilter.jpg
  98   Tue Nov 13 14:33:40 2007 JohnUpdatePSLISS filter
The transfer function from 'In Loop Error Point Monitor' to TP3 the filter out test point on the ISS board.

-33dB at 3.715MHz.
Attachment 1: PB130035.JPG
Attachment 2: DSC_0165.JPG
  104   Thu Nov 15 04:18:11 2007 JohnSummaryPSLPMC cavity pole measurements
In connection with our work on the ISS I attempted to measure the PMC cavity pole.

I swept the PMC PZT and looked at the transmission through the cavity on the ISS Monitor diode (which is now back on the table, feel free to remove it again tomorrow).

To avoid thermal effects I reduced the laser power using the half wave plate at the laser ouput (rotated from 6 deg to 340deg).

I swept the PZT using the triangle wave command "trianglewave C1: PSL-PMC_RAMP -3.5 3.3 20 200". I noticed that the functional form of the resonances deteriorated over the duration of the excitation. Each sweep was able to capture just over one FSR. The resonances were a little close to the 'points' of the triangle wave for my liking although I don't think PZT hysteresis was a big factor.

Looking at the data the peaks are not of uniform width across a sweep or between consecutive sweeps. Hence any results from this mesurement are not particularly useful. I can't be sure if this was due to misalignments, thermal effects, higher order mode content or some other affect.

Rob suggests sweeping the laser frequency using the NPRO PZT instead.
Attachment 1: Peaks.jpg
  107   Thu Nov 15 18:23:55 2007 JohnHowToComputersSwap CAPS and CTRL on a Windows 2000/XP machine
I've swapped ctrl and caps on the four control room Windows machines. Right ctrl is unchanged.

Start menu->Run "regedit"

HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\Keyboard Layout

Click on the KeyboardLayout entry.

Edit->New Binary Value name it Scancode Map.

Then select the new Scancode Map entry.

Edit menu->Modify Binary Data.

In the dialog box enter the following data:

0000: 00 00 00 00 00 00 00 00
0008: 03 00 00 00 3A 00 1D 00
0010: 1D 00 3A 00 00 00 00 00

Exit the Registry Editor. You need to log off and then on in XP (and restart in Windows 2000) for the changes to be made.
  108   Thu Nov 15 18:36:48 2007 JohnSummary PSL table work
I've rotated the lambda/2 plate to 340deg (from 6 deg) and blocked one arm of the Mach-Zender. Undo both if you need to.
  116   Tue Nov 20 10:11:33 2007 JohnSummaryPSLPMC pole measurements
We measured the PMC pole in the following way.

1. Reduced laser power by rotating lambda/2 plate at laser output. Thermal effects in the PZT distort resonance peaks. Reducing power too much leads to problems with digitisation error.

2. Sweep NPRO PZT (C1: PSL-FSS_INOFFSET) using trianglewave. Record ramp, PMC transmission and reference cavity transmission ('C1: PSL-FSS_FAST','C1: PSL-ISS_INMONPD_F','C1: PSL-FSS_RCTRANSPD_F).

3. Since the PZT cannot sweep a full FSR in the PMC we looked at the sideband resonances within the reference cavity to calibrate the actuator.
Result: 7.35 +/- 0.22 MHz/V

4. Use #3 to calibrate the x axis of the PMC transmission.

5. Fit PMC resoances to an Airy function to get finesse. Take an average, weighted according to the resnorm. Calculate cavity pole frequency.
Result: 380kHz +/- 59kHz. This corresponds to a finesse of ~936. According to this plot the nominal pole is at 488kHz and the finesse is 732.

This is by no means a definitive measurement due to the misshapen resonance peaks recorded.
Attachment 1: FittedPMCPeak.jpg
  119   Tue Nov 20 18:02:54 2007 JohnSummaryComputersPSL_Main screen
I've updated the PSL_MAIN screen. The old version may be found in cvs/cds/caltech/medm/old/medm/psl.
Attachment 1: PSL_Screen.tif
  120   Tue Nov 20 18:35:20 2007 JohnHowToComputersMatLab in Emacs
If you can't get MatLab to run in emacs try adding the following to the .emacs file

(setq matlab-shell-command-switches '("-nojvm"))

This stops the gui opening.

To start MatLab type M-x matlab-shell.
To enter MatLab mode M-x matlab-mode.

I've done this on LINUX3.

To run MatLab in emacs under windows one can use MatLabShell http://www.cs.umb.edu/~ram/matlabShell/index.html
  259   Thu Jan 24 12:50:50 2008 JohnSummaryTreasureSugar Napoleons
Some pictures from the group meeting yesterday.
Attachment 1: Sweeties.pdf
  271   Sat Jan 26 02:02:43 2008 JohnSummaryGeneralNew Channels
I added the following channels.



The old .ini file is /cvs/cds/caltech/chans/daq/C0EDCU_26_1_2008.ini
  272   Sat Jan 26 02:08:53 2008 JohnOmnistructureLSCFibres
There is now a fibre running from the SP table to the ISCT at the Y-end. In the coming days I will try to mode match the beam from this fibre into the arm through ETMY. To achieve this I will be altering the optical layout of this table.
  275   Sat Jan 26 18:48:43 2008 JohnSummaryComputersRestart iscepics
iscepics died this afternoon. We restarted it and restored settings from yesterday. I've written up instructions in the wiki.
  276   Sat Jan 26 22:00:03 2008 JohnUpdateGeneralLSC-TRY_OUT and ETMY-QPD
In the path from the ETM to the trans PD and QPD at the Y end I have replaced a BS1-1064-10-2037-45P with a polariser. The power falling on these diodes has been reduced. When the arm is locked in its nominal state the transmitted power is now less than 1.

This polariser should serve as an injection point for the auxiliary arm locking. I am attempting to use crossed polarisations to separate this loop from the main arm light.
  288   Thu Jan 31 12:39:14 2008 JohnConfigurationGeneralY arm test mass cameras
I've adjusted the test mass cameras on the y arm to make the beam injected through ETMY more visible.
  290   Fri Feb 1 10:43:05 2008 JohnUpdateEnvironmentConstruction work
The boys next door have some bigger noisier toys.
Attachment 1: DSC_0433.JPG
  293   Fri Feb 1 17:17:05 2008 JohnSummaryPSLMach-Zender tweaking
I helped Rob adjust the alignment of the Mach-Zender to try and reduce any AM on the laser light. Our goal was to reduce the large offsets in the DD signals.

We reduced the MZ refl from 0.54 to 0.39. We were able to re-lock the mode cleaner without problems. We then centred the WFS heads.

No change in the DD signal offsets.
  294   Sat Feb 2 14:11:27 2008 JohnSummaryComputersOPTLEVmaster screen
I changed the layout of the optlev master screen. The old version is /cvs/cds/caltech/medm/old/C1ASC_OPTLEVmaster080202.adl
  296   Mon Feb 4 22:01:57 2008 JohnSummaryLSCFibres auxiliary locking - Fibers
I managed to couple ~75% of the light transmitted from the y arm, through the fibre, back to the SP table. I hoped that this would be a good way to match the beam from the fibre into the arm. Still no flashes. It looks like the cameras just aren't sensitive enough.
  304   Sat Feb 9 13:05:48 2008 JohnSummaryIOOPMC camera/ HEPA
I replaced the Gig-E camera on the PMC trans beam. The PZT was close to railing and I wanted to adjust it. I just did a quick job, there is a little scattered light on the image. If Joe is finished with the Gig-E I'll take another look at it.

The HEPA in the PSL table was turned off for some reason. I turned it back on.
  305   Sat Feb 9 13:32:07 2008 JohnSummarySUSAll watchdogs tripped
When I arrived this afternoon the watchdogs had tripped on all optics. I reset them and enabled the coil currents.

I had to adjust the alignment of the mode cleaner to get it to lock.
  315   Wed Feb 13 20:37:11 2008 JohnUpdateLSCFibre locking - Fiber
Sam and I observed fringes in the light reflected from the Y arm. These fringes are due to the sidebands and not the carrier. To improve matters we plan to reduce the RF AM and increase our modulation index.
  324   Tue Feb 19 18:28:41 2008 JohnUpdatePEMMore seismic in Baja California
Steve spotted more activity from the same quake.

Reset watchdog on ETMY.
  328   Thu Feb 21 18:29:28 2008 JohnSummaryGeneralHP Network Analyser Analyzer
The HP 4195A network analyser may be broken, measurements below 150MHz are not reliable. Above 150MHz everything looks normal. This may be caused by a problem with its output (the one you'd use as an excitation) which is varying in amplitude in a strange way.

  342   Wed Feb 27 22:05:03 2008 JohnUpdateLSCAuxiliary locking
A summary of the status of the auxiliary arm locking effort.

To help with lock acquisition we are attempting to independently lock the Y arm using light injected through ETMY. At present this secondary light source is an NPRO laser situated on the SP table. The laser light is transported to the ETM using a single mode optical fibre. In the future we might pick off some PSL light and apply a frequency shift.

We have been able to successfully mode match the fibre beam into the cavity and have been attempting lock the cavity using standard PDH signals (phase modulation sidebands are added to the light before it enters the fibre).

As yet no acceptable error signals have been produced. The demodulated RF signal is showing a time varying, bipolar dc offset.

We have minimised the residual amplitude modulation of the EOM but we expect small signals due to the undercoupled nature of the system, it could be that whatever RFAM still present is varying with time and causing this behaviour. We are also able to produce similar offsets by stressing (i.e. bending, shaking) the fibre. Could it be that the fibre is somehow converting PM into AM? Are we seeing etalon effects in the fibre or elsewhere?

If we cannot make any further progress with the existing setup we shall move the NPRO to the ETM table and try again. We are also looking into purchasing some other types of fibre.

Other things to consider are injecting through POY or using some other wavelength - neither seems obviously better.

Fiber, behavior
  348   Fri Feb 29 13:51:17 2008 JohnSummaryLSCPD6 response
I checked the response of PD6 using the AM laser. It looks happy enough.

16 averages
-10dBm source power
77.3mV dc on the diode
  359   Wed Mar 5 12:35:09 2008 JohnSummaryComputer Scripts / ProgramsPlot photodiode responses in MatLab
A matlab function to plot the responses of photodiodes. There's still plenty of room for improvement but it should work for all our diodes without any changes. You may want to adjust which points are used in the fit to remove time delay.

% Plot data from diode response measurements
function out = diodeplot(f_Hz,mag_dB,phase_deg,f_beat_MHz)

% $$$ clear all
% $$$ close all
% $$$ clc
% $$$
% $$$
% $$$ mag = dlmread('D:\40m\PD6\M7.txt','\t', 15, 0);
% $$$ phase = dlmread('D:\40m\PD6\P7.txt','\t', 15, 0);
% $$$
% $$$ % Frequency i.e. x-axis
% $$$ f = mag(:,1);
% $$$
% $$$ % Magnitude in dB
% $$$ mag_dB = mag(:,2);
% $$$
% $$$ % Phase in degrees
% $$$ phase_deg = phase(:,2);
% $$$
% $$$ % Frequencies of interest
% $$$ f_beat_MHz = [33 133 166 199]*1e6;
% $$$
% $$$ diodeplot(f, mag_dB, phase_deg, f_beat_MHz)

% x axis limits
xmin = 10e6;
xmax = 500e6;

% Unwrap phase
phase_deg = (180/pi)*unwrap((pi/180)*phase_deg);

%Find values at our freqeuncies of interest
Mag_f_beat = interp1(f_Hz,mag_dB,f_beat_MHz);

% Remove the time delay from the phase data
% (May want to adjust which points are selected here)

straight = @(a, x) a(1) * x + a(2);

xdata = f_Hz;
ydata = phase_deg;

aguess = [10 0.1];
a = lsqcurvefit(straight,aguess,xdata,ydata);
fit = straight(a,xdata);

phase_deg = phase_deg-fit;

ha = axes('units','normalized','position',[0 0 1 1]);
hi = imagesc(I);
colormap gray
set(ha,'handlevisibility','off', ...
hold on
hold off
ylabel('Phase/ degrees', 'FontSize',12)
xlabel('Frequency/ Hz', 'FontSize',12)
title('Removing the time delay','FontSize',16)
box off

set(gcf,'Color', [1 1 1])
subplot(4,1,[1 3])

title('Response of PD6','FontSize',16)
ylabel('Magnitude/ dB', 'FontSize',12)
xlim([xmin xmax])

MagLayout = get(gca, 'Position');
YLimits = get(gca, 'YLim') ;
LabelExt = [];

for ivar = 1:length(f_beat_MHz);

a = text(f_beat_MHz(ivar),1.05 * min(Mag_f_beat),...
sprintf('%2.1fdB @ %dMHz', Mag_f_beat(ivar),f_beat_MHz(ivar)/1e6),...
'VerticalAlignment','top','BackgroundColor',[.7 .9 .7],...
'Margin',0.5, 'Rotation',90);
LabelExt = [LabelExt; get(a,'Extent')];
LabelPos = get(a,'Position');


% Change YLim so that it is around the bottom of the labels
% There must be a better way
set(gca, 'YLim', [min(LabelExt(:,2)) YLimits(2)])

% Remove the last tick mark so that it doesn't overlap with the
% +180 of the phase plot
YTickLabelNew = str2num(get(gca, 'YTickLabel'));
YTickNew =[[] YTickLabelNew(2:end) ];
set(gca,'XTickLabel', [], 'YTick', YTickNew)

% Add lines now we know what the YLims are
for ivar = 1:length(f_beat_MHz);
line([f_beat_MHz(ivar) f_beat_MHz(ivar)], get(gca, 'YLim'))

xlim([xmin xmax])
ylabel('Phase/ degrees', 'FontSize',12)
xlabel('Frequency/ Hz', 'FontSize',16)
PhaseLayout = get(gca, 'Position');
PhaseLayout(4) = MagLayout(2)-PhaseLayout(2);

% Make the top of the phase plot align to the bottom of the
% magnitude plot
set(gca, 'Color', 'None', 'Position',PhaseLayout, 'YTick',[-180:45: ...
set(gcf,'units','normalized','outerposition',[0 0 1 1]);
Attachment 3: PDbw.jpg
  360   Wed Mar 5 12:51:48 2008 JohnSummaryLSCInitial Ligo Arm finesse versus lambda
I've taken the coating recipes for the initial ligo arm cavity from Rana's web page (ligo.caltech/edu/~rana/mat/)
and plotted the finesse as a function of wavelength. There is some uncertainty over the indices of refraction but
the main conclusion remains unchanged - i.e. it appears that using other wavelengths will be difficult.
Stefan is looking at how to tune the layers of any new mirrors to make dichroic optics.
Attachment 1: FofLambdaLIGOI.jpg
  367   Mon Mar 10 20:46:41 2008 JohnConfigurationLSCETMY Trans PD & QPD
I've placed a 10% reflector in the path from ETMY to the trans and quadrant photodiodes.
  377   Thu Mar 13 18:20:29 2008 JohnUpdateGeneralNew Focus 4003 EOM 29.489MHz
I measured the modulation index as a function of drive power using an OSA. Agrees well with spec of 0.2 rad/V.
ELOG V3.1.3-