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ID Date Author Type Category Subject
13963   Thu Jun 14 15:21:58 2018 gautamUpdateComputer Scripts / Programs/cvs/cds Backup in danger

I think this is because /cvs/cds is getting too big. lsblk reveals:

controls@chiara|~> lsblk NAME   MAJ:MIN RM   SIZE RO TYPE MOUNTPOINT sda      8:0    0 465.8G  0 disk  ├─sda1   8:1    0 446.9G  0 part / ├─sda2   8:2    0     1K  0 part  └─sda5   8:5    0  18.9G  0 part [SWAP] sdb      8:16   0   2.7T  0 disk  └─sdb1   8:17   0     2T  0 part /home/cds sr0     11:0    1  1024M  0 rom   sdc      8:32   0   1.8T  0 disk  └─sdc1   8:33   0   1.8T  0 part /media/40mBackup sdd      8:48   0   1.8T  0 disk  └─sdd1   8:49   0   1.8T  0 part 

I believe one of sdc or sdd is connected via SATA while the other is an external USB drive. Maybe we have to get bigger backup disks, but this may be a huge pain to setup as it will involve taking chiara down. Actually, now that I check the backup log, seems like backup is executing successfully - not sure if this is due to my unelogged mounting of sdc (using sudo mount /dev/sdc1 /media/40mBackup) last week, or if this is some LDAS backup. But in any case, seems undesirable that sdb1 is larger than sdc1 or sdd1.

2018-06-06 07:00:01,086 INFO       Updating backup image of /cvs/cds 2018-06-06 07:00:01,086 ERROR      External drive not mounted!!! 2018-06-07 07:00:01,147 INFO       Updating backup image of /cvs/cds 2018-06-07 07:00:01,147 ERROR      External drive not mounted!!! 2018-06-08 07:00:01,244 INFO       Updating backup image of /cvs/cds 2018-06-08 08:23:32,939 INFO       Backup rsync job ran successfully, transferred 316870 files. 2018-06-09 07:00:01,465 INFO       Updating backup image of /cvs/cds 2018-06-09 07:12:11,865 INFO       Backup rsync job ran successfully, transferred 1926 files. 2018-06-10 07:00:01,842 INFO       Updating backup image of /cvs/cds 2018-06-10 07:12:28,931 INFO       Backup rsync job ran successfully, transferred 1656 files. 2018-06-11 07:00:01,294 INFO       Updating backup image of /cvs/cds 2018-06-11 07:06:14,748 INFO       Backup rsync job ran successfully, transferred 1664 files. 2018-06-12 07:00:02,081 INFO       Updating backup image of /cvs/cds 2018-06-12 07:07:36,775 INFO       Backup rsync job ran successfully, transferred 1870 files. 2018-06-13 07:00:02,194 INFO       Updating backup image of /cvs/cds 2018-06-13 07:08:37,356 INFO       Backup rsync job ran successfully, transferred 1818 files. 2018-06-14 07:00:01,753 INFO       Updating backup image of /cvs/cds 2018-06-14 07:01:43,270 INFO       Backup rsync job ran successfully, transferred 1744 files.
 Quote: Local backup on chiara seems not working since Nov 19, 2017. /opt/rtcds/caltech/c1/scripts/backup/localbackup.log 2017-11-18 07:00:01,504 INFO       Updating backup image of /cvs/cds 2017-11-18 07:03:00,113 INFO       Backup rsync job ran successfully, transferred 1954 files. 2017-11-19 07:00:02,564 INFO       Updating backup image of /cvs/cds 2017-11-19 07:00:02,592 ERROR      External drive not mounted!!!

13966   Thu Jun 14 18:09:24 2018 gautamUpdateLSCReliable and repeatable 1f DRMI locking

I finally analyzed the sensing measurement I ran on Tuesday evening. Sensing responses for the DRMI DOFs seems consistent with what I measured in October 2017, although the relative phasing of the DoFs in the sensing PDs has changed significantly. For what it's worth, my Finesse simulation is here

Attachment 1: DRMI1f_June14.pdf
13967   Thu Jun 14 19:30:12 2018 gautamUpdateGeneralIFO alignment restored

All optics have been re-aligned. Jon/Johannes will elog about the work today.

13969   Fri Jun 15 00:53:21 2018 gautamUpdateLSCCalibrated MICH spectrum

Using the numbers from the sensing measurement, I calibrated the measured in-loop MICH spectrum from Tuesday night into free-running displacement noise. For convenience, I used the noise-budgeting utilities to make this plot, but I omitted all the technical noise curves as the coupling has probably changed and I did not measure these. The overall noise seems ~x3  higher everywhere from the best I had last year, but this is hardly surprising as I haven't optimized anything for low noise recently. To summarize:

• DRMI was locked using 1f error signals.
• MICH was controlled using AS55_Q.
• Main difference is that we have a little less (supposedly 10%) light on the AS55 PD now because of the AUX laser injection setup. But the AUX laser was shuttered.
• 1f LSC PDs (REFL11, REFL55 and AS55) had ADC whitening filters engaged in while this data was taken.
• ITM and BS coils were not de-whitened.

I will do a more thorough careful characterization and add in the technical noises in the coming days. The dominant uncertainty in the sensing matrix measurement, and hence this free-running noise spectrum, is that I haven't calibrated the actuators in a while.

 Quote: I finally analyzed the sensing measurement I ran on Tuesday evening. Sensing responses for the DRMI DOFs seems consistent with what I measured in October 2017, although the relative phasing of the DoFs in the sensing PDs has changed significantly. For what it's worth, my Finesse simulation is here.
Attachment 1: C1NB_disp_40m_MICH_NB_2018-06-14.pdf
13973   Fri Jun 15 14:22:05 2018 gautamUpdateALSBeatMouth PDFR measurement

I did the measurement with the BeatMouth open today. Main changes:

• Directly pipe the RF output of the Menlo PDs to the Agilent, bypassing the 20dB coupler inside the BeatMouth.
• Directly pipe the unused port of the Fiber Beamsplitter used to send light to the Menlo PD to an in-air collimator, which then sends the beam to the NF1611 reference detector.

So neglecting asymmetry in the branching ratio of the fiber beamsplitter, the asymmetry between the test PD optical path and the reference PD optical path is a single fiber mating sleeve in the former vs a collimator in the latter. In order to recover the expected number of 409 V/W for the Menlo PDs, we have to argue that the optical loss in the test PD path (fiber mating sleeve) are ~3x higher than in the NF1611 path (free space coupler). But at least the X and Y PDs show identical responses now. The error I made in the previously attached plot was that I was using the 20dB coupled output for the X PD measurement .

Revised conclusion: The measured optoelectronic response of the Menlo PDs at 10s of MHz, of ~130 V/W, is completely consistent with the numbers I reported in this elog. So rogue polarization is no longer the culprit for the discrepancy between expected and measured RF beatnote power, it was just that the expectation, based on Menlo PD specs, were not accurate.#2 of the linked elog seems to be the most likely, although "broken" should actually be "not matching spec".

While killing time b/w measurements, I looked on the ITMY optical table and found that the NF1611 I mentioned in this elog still exists. It is fiber coupled. Could be a better substitute as a Reference PD for this particular measurement.

 Quote: I will repeat the measurement tomorrow by eliminating some un-necessary patch fiber cables, and also calibrating out the cable delays. The setup shown in Attachment #1 was used because I didn't want to open up the BeatMouth. But I can pipe the port of the BS not going to the FPD310 directly to the collimator, and that should reduce the systematic uncertainty w.r.t. power distribution between FPD310 and NF1611.
Attachment 1: BeatMouthPDFR.pdf
Attachment 2: BeatMouth_PDFRdata.tgz
13974   Sat Jun 16 00:26:48 2018 gautamUpdateGeneralPRC modescan attempt

[Jon, Gautam, Johannes]

We did the following today:

1. Dither align arms such that ITMs were reliable arm references.
2. Configure the IFO such that ITMX single bounce was the only visible beam reaching the AS port from the symmetric side - ITMY, both ETMs, PRM and SRM were misaligned.
3. Do coarse alignment on the AS table using the usual near field / far field overlap technique, with "near" and "far" dictated by arm reach on the AS table. In this way, the ingoing AUX beam and the PSL single bounce from ITMX were collimated on the AS table.
4. Lock the AUX / PSL PLL. We expected a beatnote on AS110 at eithe (80-50)=30 MHz or (80+50)=130 MHz. 80 MHz is the AOM driver frequency, while 50 MHz is the PLL offset. (Marconi was actually set to 60 MHz, prolly Keerthana forgot to reset it after some remote experimentation).
5. Beat was found at 30 MHz.
6. Input steering of AUX beam into the IFO was tweaked to maximize the beat. Johannes claims he saw -35 dBm on AS110 last week. But Jon reported a best effort of ~-60 dBm today. Not sure how to square that circle.
7. Once we were confident that the input of the AUX and PSL beams were well aligned, we decided to do a scan. PRC was chosen as PRMI can be locked but I don't yet know the correct settings for SRMI locking, and DRMI seemed too ambitious for daytime.
• PRMI was locked on carrier.
• Jon can comment more here, but the measurement with AM sidebands does not rely on any beatnote on the AS110 PD, it is just looking for coupling of the AM sideband into the IFO from the AS port at resonant frequencies of the PRC.
• For a coarse sweep, we swept from 1-60 MHz, 801 points, and the IF bandwidth was set at 30 kHz on the AG4395.
• Transfer function being measured was the ratio of AM signal detected at AS110 PD, to RF drive applied to the AOM driver.
• We were expecting to see dips separated by the PRC FSR (~25 MHz, since the PRC RT length is ~12.5m), when the AM sideband becomes resonant in the PRC.
• But we saw nothing. Need to think about if this is an SNR problem, or if we are overlooking something more fundamental in the measurement setup.

This measurement seems like a fine candidate to trial the idea of looking for the FSRs (and in general, cavity resonances) of the PRC in the phase of the measured TFs, rather than the amplitude.

13981   Mon Jun 18 14:32:42 2018 gautamUpdatePSLOptics on AS table

Yesterday, I moved the following optics:

1. Lens in front of AS110 PD.
2. BS splitting light between AS110 and AS55.

After moving these components around a bit, I locked them down once I was happy that the beam was pretty well centered on both of them, and also on AS110 and AS55 (measured using O'scope with single bounce from one ITM, other optics misaligned).

The beam was close to clipping on the lens mentioned in #1, probably because this wasn't checked when the 90-10 BS was installed for the AUX laser. Furthermore, I believe we are losing more than 10% of the light due to this BS. The ASDC (which is derived from AS55 PD) level is down at ~110cts as the Michelson is fringing, while it used to be ~200 cts. I will update with a power measurement shortly. But I think we should move ahead with the plan to combine the beam into the IFO's AS mode as discussed at the meeting last week.

Unrelated to this work, but c1psl and c1iscaux were keyed.

ASDC has something weird going on with it - my main goal yesterday was to calibrate the actuators of ITMX, ITMY and BS using the Michelson. But with the Michelson locked on a dark fringe, the ASDC level changed by up to 50 counts seemingly randomly (bright fringe was ~1000 cts, I had upped the whitening gain to +21dB), even though the CCD remained clearly dark throughout. Not sure if the problem is in the readout electronics or in the PD itself.

13984   Mon Jun 18 19:47:02 2018 gautamUpdateGeneralMICH actuator calibration

Summary:

The actuator (pendulum) gains for the Beam Splitter and the two ITMs were measured to be:

BS: 9.54 +/- 0.05 nm/ct [100 ohm series resistor in coil driver board]

ITMX: 2.44 +/- 0.01 nm/ct [400 ohm series resistor in coil driver board]

ITMY: 2.44 +/- 0.02 nm/ct [400 ohm series resistor in coil driver board]

Counts here refers to DAC counts at the output of the coil filter banks (as opposed to counts at the LSC servo output). The dominant (systematic) uncertainty (which isn't quoted here) in this measurement is the determination of the peak-to-peak swing of the dark port sensor, AS55_Q. I estimate this error to be ~1ct/33cts = 3%. These values are surprisingly consistent with one another once we take into account the series resistance.

Details:

The last time this was done, we used ASDC to do the measurement. But I don't know what signal conditioning ASDC undergoes (in PD or in readout electronics). In any case, in my early trials yesterday, ASDC was behaving unpredictably. So I decided to do redo the measurement.

[Attachment #1]- Flowchart describing the calibration procedure.

[Attachment #2] - AS55_Q output while the Michelson was freeswinging. I had first aligned the ITMs using ASS. The peak-to-peak value of this corresponds to $\lambda/4$. So we know AS55_Q in terms of cts/m of MICH displacement.

[Attachment #3] - Magnitudes of transfer function from moving one of the MICH optics, to the now calibrated AS55_Q. Fits are to a shape $a/f^2$, with $a$ being the fitted parameter. Coherence during the measurement is also plotted.

• Note that the excitation is applied to the channels C1:SUS-<optic>_LSC_EXC, for <optic> in [BS, ITMX, ITMY]. But since my de-whitening board re-work to remove the analog x3 gain, there is a digital x3 gain in the coil driver filter banks. So while the calibration numbers given above are accurate, be aware that when using them for sensing matrix measurements etc, you have to multiply these by x3.
• Furthermore, moving the BS by $x$ results in a Michelson length change of $\sqrt{2}x$, and this has been factored into the above number.

Next Steps:

1. Now that I have a calibration I trust more, re-analyze my DRMI sensing matrix data. Actually the sensing response numbers aren't significantly different from what I have been assuming. It's just that in terms of counts applied at the LSC input of a suspension, there is a digital x3 gain that has to be explicitly factored in.
2. Calibrate POX and POY by locking the arms and driving the now calibrated ITMs by a known number of counts.
3. Calibrate the ETMs, and MC1/MC2/MC3 by looking at calibrated POX/POY.
4. Lock DRMI, and calibrate SRM and PRM.

Reference:

Attachment 1: AS55cal_process.pdf
Attachment 2: AS55cal.pdf
Attachment 3: MICH_act_calib.pdf
13985   Tue Jun 19 00:19:00 2018 gautamUpdateASCPOP status check

Motivation:

1. I want to use the QPD at POP, calibrate it into physical units, and quantify the amount of angular jitter in the PRC (which I claim is what limits DRMI stability atm).
2. I want to revive the PRC angular feedforward to try and mitigate this a bit. But is feedforward even the best approach? Can we use feedback using the POP QPD?

POP QPD checkout:

• The POP QPD sits on the ITMX optical table.
• It is interfaced to the CDS system via an OT301 and then a Pentek whitening stage (z:p = 15:150).
• The OT301 claims to have a switchable offset nulling capability - but despite my best efforts tonight, I couldn't use the knobs on the front to null the offset (even with the PRC locked on carrier and a strong POP beam on the QPD).
•
• So I moved the QPD with the PRC locked, to center the CDS readback of the spot position at (0,0).
• Next step is to calibrate the POP QPD readback into physical units.
• I'm thinking of using the EricG diode laser for this purpose.
• I can calibrate counts to mm of displacement on the QPD active area.
• After which I can use the estimated position to PR2 (from which POP is extracted) to convert this to angular motion.
• I guess I should check for coherence between the POP QPD signal and all angular sensors of PRM/BS/MC1/MC2/MC3 to try and confirm the hypothesis that the folding mirrors are dominating the angular noise of the cavity. Unfortunately we don't have readbacks of the angular positions of TT1 and TT2.
• I moved the POP camera a bit in YAW so that the POP spot is now better centered on the CCD monitor.
• I also wanted to check the centering on the other POP QPD (POP22/POP110/POPDC?) but I think the POPDC signal, used for triggering the PRCL LSC servo, is derived from that PD, so everytime I blocked it, the lock was lost. Need to think of another strategy.
• MC3 has been rather glitchy tonight.
• So I will wait for a quieter time when I can collect some data to train the WF for angular FF.
13988   Tue Jun 19 23:27:27 2018 gautamUpdateSUSETMX coil driver work in AM tomorrow

Per discussion today eve, barring objections, I will do the following tomorrow morning:

1. Remove ETMX coil driver board from 1X9
• Change series resistances on the fast path to 2x4k in parallel. One will be snipped off once we are happy we can still lock.
• Thick film-->thin film for important components.
2. Remove ETMX de-whitening board from 1X9
• Remove x3 analog gain.
• Thick film-->thin film for important components.
13992   Thu Jun 21 00:14:01 2018 gautamUpdateSUSETMX coil driver out

I finished the re-soldering work today, and have measured the coil driver noise pre-Mods and post-Mods. Analysis tomorrow. I am holding off on re-installing the board tonight as it is likely we will have to tune all the loops to make them work with the reduced range. So ETMX will remain de-commissioned until tomorrow.

13993   Thu Jun 21 03:13:37 2018 gautamUpdateSUSETMX coil driver noise

I decided to take a quick look at the data. Changes made to the ETMX coil driver board:

1. Fast path series resistances: 400 ohm ---> 2.25 kOhm (= 2x 4.5 kohm in parallel). Measured (with DMM) resistance in all 5 paths varied by less than 3 ohms (~0.2%).
2. All thick film resistors in signal (fast and bias) paths changed to thin film.
3. AD797 ---> Op27 for monitor output.
4. Above-mentioned mon output (30Hz HPF-ed) routed to FP LEMO mon via 100ohm for diagnostic purposes.
5. 4x Trim-pots in analog path removed.

I also took the chance to check the integrity of the LM6321 ICs. In the past, a large DC offset on the output pin of these has been indicative of a faulty IC. But I checked all the ICs with a DMM, and saw no anomalies.

Measurement condition was that (i) the Fast input was terminated to ground via 50ohm, (ii) the Bias input was shorted to ground. SR785 was used with G=100 Busby preamp (in which Steve installed new batteries today, for someone had left it on for who knows how long) for making the measurement. The voltage measurement was made at the D-Sub connector on the front panel which would be connected to the Sat. Box, with the coil driver not connected to anything downstream.

Summary of results:

[Attachment #1] - Noise measurement out to 800 Hz. The noise only seems to agree with the LISO model above 300 Hz. Not sure if the low-frequency excess is real or a measurement artefact. Tomorrow, I plan to make an LPF pomona box to filter out the HF pickup and see if the low-frequency characteristics change at all. Need to think about what this corner freq. needs to be. In any case, such a device is probably required to do measurements inside the VEA.

[Attachment #2] - Noise measurement for full SR785 span. The 19.5 kHz harmonics are visible. I have a theory about the origin of these, need to do a couple of more tests to confirm and will make a separate log.

[Attachment #3] - zip of LISO file used for modeling coil driver. I don't have the ASCII art in this, so need to double check to make sure I haven't connected some wrong nodes, but I think it's correct.

Measurements seem to be consistent with LISO model predictions.

*Note: Curves labelled "LISO model ..." are really quad sum of liso pred + busby box noise.

My main finding tonight is: With the increased series resistance (400 ohm ---> 2.25 kohm), LISO modeling tells me that even though the series resistance (Johnson noise) used to dominate the voltage noise at the output to the OSEM, the voltage noise of the LT1125 in the bias path now dominates. Since we are planning to re-design the entire bias path anyways, I am not too worried about this for the moment.

I will upload more details + photos + data + schematic + LISO model breakdown tomorrow to a DCC page

gautam noon 21 June 2018: I was looking at the wrong LISO breakdown curves. So the input stage Op27 voltage noise used to dominate. Now the Bias path LT1125 voltage noise dominates. None of the conclusions are affected... I've uploaded the corrected plots and LISO file here now.

Attachment 1: ETMXsticthced.pdf
Attachment 2: ETMXFullSpan.pdf
Attachment 3: ETMXCoilDriver.fil.zip
13998   Thu Jun 21 15:32:05 2018 gautamUpdateElectronicsEX AA filter range change

[steve, gautam]

I took this opportunity of EX downtime to change the supply voltage for the AA unit (4-pin LEMO front panel) in 1X9 from +/-5V to +/-15V. Inside the AA board are INA134 and DRV135 ICs, which are rated to work at +/-18V. In the previous state, the inputs would saturate if driven with a 2.5Vpp sine wave from a DS345 func. gen. After the change, I was able to drive the full range of the DS345 (10Vpp), and there was no saturation seen. This AA chassis is only used for the OSEM signals and also some ALS signals. Shadow sensor levels and spectra are consistent before and after the change. The main motivation was to not saturate the Green PDH Reflection signal in the digital readout. The steps we took were:

1. Confirm (by disconnecting the power cable at the back of the AA box) that the power supplied was indeed +/- 5 V.
2. Remove DIN fuse blocks from DIN rail for the relevant blocks.
3. Identify a +15 V, -15 V and GND spot to plug the wires in.
4. Effect the swap.
5. Re-insert fuses, checked supply voltage at connector end of the cable was now +/- 15 V as expected.
6. Re-connect power cable to AA box.
13999   Thu Jun 21 18:25:57 2018 gautamUpdateSUSETMX coil driver re-installed

Initial tests look promising. Local damping works and I even locked the X arm using POX, although I did it in a fake way by simply inserting a x5.625 (=2.25 kohm / 400 ohm) gain in the coil driver filter banks. I will now tune the individual loop gains to account for the reduced actuation range.

Now I have changed the loop gains for local damping loops, Oplev loops, and POX locking loop to account for the reduced actuation range. The dither alignment servo (X arm ASS) has not been re-commissioned yet...

14000   Thu Jun 21 22:13:12 2018 gautamUpdateCDSpianosa upgrade

pianosa has been upgraded to SL7. I've made a controls user account, added it to sudoers, did the network config, and mounted /cvs/cds using /etc/fstab. Other capabilities are being slowly added, but it may be a while before this workstation has all the kinks ironed out. For now, I'm going to follow the instructions on this wiki to try and get the usual LSC stuff working.

14003   Fri Jun 22 00:59:43 2018 gautamUpdateCDSpianosa functional, but NO DTT

MEDM, EPICS and dataviewer seem to work, but diaggui still doesn't work (it doesn't work on Rossa either, same problem as reported here, does a fix exist?). So looks like only donatella can run diaggui for now. I had to disable the systemd firewall per the instructions page in order to get EPICS to work. Also, there is no MATLAB installed on this machine yet. sshd has been enabled.

14007   Fri Jun 22 15:13:47 2018 gautamUpdateCDSDTT working

Seems like DTT also works now. The trick seems to be to run sudo /usr/bin/diaggui instead of just diaggui. So this is indicative of some conflict between the yum installed gds and the relic gds from our shared drive. I also have to manually change the NDS settings each time, probably there's a way to set all of this up in a more smooth way but I don't know what it is. awggui still doesn't get the correct channels, not sure where I can change the settings to fix that.

Attachment 1: Screenshot_from_2018-06-22_15-12-37.png
14009   Fri Jun 22 18:30:21 2018 gautamUpdateSUSITMY_UL sensor

I think if the magnet fell off, we would see high DC signal, and not 0 as we do now. I suspect satellite box or PD readout board/cabling. I am looking into this, tester box is connected to ITMY sat. box for now. I will restore the suspension later in the evening.

Suspension has now been restored. With combination of multimeter, octopus cable and tester box, the problem is consistent with being in the readout board in 1X5/1X6 or the cable routing the signals there from the sat. box.

• Tester box hooked up to sat box ---> UL coil still shows 0 in CDS.
• Tester box hooked up to sat box ---> Mon D-sub on sat box shows expected voltages on DMM. So tester box LEDs are being powered and seem to work.
• Sat box re-connected to test mass ---> Mon D-sub on sat box shows expected voltages on DMM. So OSEM LEDs are being powered and seem to work.
• Sat box remains connected to TM ---> Front panel LEMO monitor points on readout board shows 0 for UL channel, other channels are okay.
 Quote: We may lost the UL magnet or LED

14012   Sun Jun 24 20:02:07 2018 gautamUpdateSUSSome notes about coil driver noise

Summary:

For a series resistance of 4.5 kohm, we are suffering from the noise-gain amplified voltage noise of the Op27 (2*3.2nV/rtHz), and the Johnson noise of the two 1 kohm input and feedback resistances. As a result, the current noise is ~2.7 pA/rtHz, instead of the 1.9 pA/rtHz we expect from just the Johnson noise of the series resistance. For the present EX coil driver configuration of 2.25 kohm, the Op27 voltage noise is actually the dominant noise source. Since we are modeling small amounts (<1dB) of measurable squeezing, such factors are important I think.

Details:

[Attachment #1] --- Sketch of the fast signal path in the coil driver board, with resistors labelled as in the following LISO model plots. Note that as long as the resistance of the coil itself << the series resistance of the coil driver fast and slow paths, we can just add their individual current noise contributions, hence why I have chosen to model only this section of the overall network.

[Attachment #2] --- Noise breakdown per LISO model with top 5 noises for choice of Rseries = 2.25 kohm. The Johnson noise contributions of Rin and Rf exactly overlap, making the color of the resulting line a bit confusing, due to the unfortunate order of the matplotlib default color cycler. I don't want to make a custom plot, so I am leaving it like this.

[Attachment #3] --- Noise breakdown per LISO model with top 5 noises for choice of Rseries = 4.5 kohm. Same comments about color of trace representing Johnson noise of Rin and Rf.

Possible mitigation strategies:

1. Use an OpAmp with lower voltage noise. I will look up some candidates. LT1028/LT1128? LISO library warns of a 400 kHz noise peak though...
2. Use lower Rin and Rf. The values of these are set by the current driving capability of the immediately preceeding stage, which is the output OpAmp of the De-Whitening board, which I believe is a TLE2027. These can source/sink 50 mA according to the datasheet . So for +/-10V, we could go to 400 ohm Ri and Rf, source/sink a maximum of 25mA, and reduce the Johnson noise contribution by 40%.

I've chosen to ignore the noise contribution of the high current buffer IC that is inside the feedback loop. Actually, it may be interesting to compare the noise measurements (on the electronics bench) of the circuit as drawn in Attachment #1, without and with the high current buffer, to see if there is any difference.

This study also informs about what level of electronics noise is tolerable from the De-Whitening stage (aim for ~factor of 5 below the Rseries Johnson noise).

Finally, in doing this model, I understand that the observation the voltage noise of the coil driver apparently decreased after increasing the series resistance, as reported in my previous elog. This is due to the network formed by the fast and slow paths (during the measurement, the series resistance in the slow path makes a voltage divider to ground), and is consistent with LISO modeling. If we really want to measure the noise of the fast path alone, we will have to isolate it by removing the series resistance of the slow bias path.

Comment about LISO breakdown plots: for the OpAmp noises, the index "0" corresponds to the Voltage noise, "1" and "2" correspond to the current noise from the "+" and "-" inputs of the OpAmp respectively. In future plots, I'll re-parse these...

 Quote: I will upload more details + photos + data + schematic + LISO model breakdown tomorrow to a DCC page.

Attachment 1: CoilDriverSchematic.pdf
Attachment 2: D010001_2k_fastOnly_2.25k.pdf
Attachment 3: D010001_4k_fastOnly_4.5k.pdf
14019   Tue Jun 26 16:28:00 2018 gautamUpdateSUSCoil driver protoboard characterization

I wanted to investigate my coil driver noise measurement technique under more controlled circumstances, so I spent yesterday setting up various configurations on a breadboard in the control room. The overall topology was as sketched in Attachment #1 of the previous elog, except for #4 below. Summary of configurations tried (series resistance was 4.5k ohm in all cases):

1. Op 27 with 1kohm input and feedback resistors.
2. LT1128 with 1kohm input and feedback resistors.
3. LT1128 with 400 ohm input and feedback resistors.
4. LT1128 with 400 ohm input and feedback resistors, and also the current buffer IC LM6321 implemented.

Attachments:

Attachment #1: Picture of the breadboard setup.

Attachment #2: Noise measurements (input shorted to ground) with 1 Hz linewidth from DC to 4 kHz.

Attachment #3: Noise measurements for full SR785 span.

Attachment #4: Apparent coupling due to PSRR.

Attachment #5: Comparison of low frequency noise with and without the LM6321 part of the fast DAC path implemented.

All SR785 measurements were made with input range fixed at -42dBVpk, input AC coupled and "Floating", with a Hanning window.

Conclusions:

• I get much better agreement between LISO and measurement at a few hundred Hz and below with this proto setup. So it would seem like the excess noise I measure at ~200 Hz in the Eurocrate card version of the coil driver could be real and not simply a measurement artefact.
• I am puzzled about the 10 Hz comb in all these measurements:
• I have seen this a few times before - e.g. elog13655.
• It is not due to the infamous GPIB issue - the lines persist even though I disconnect both power adaptor and GPIB prologix box from the SR785.
• It does not seem to be correlated with the position of the analyzer w.r.t. the DC power supply (Tektronix PS280) used to power the circuit (I moved the SR785 around 1m away from the supply).
• It persists with either of the two LN preamp boxes available.
• It persists with either "Float" or "Ground" input setting on the SR785.
• All this pointed to some other form of coupling - perhaps conductive EMI.
• The only clue I have is the apparent difference between the level of the coupling for Op27 and LT1128 - it is significantly lower for the latter compared to the former.
• I ruled out position on the breadboard: simply interchanging the Op27 and LT1128 positions on the breadboard, I saw higher 10 Hz harmonics for the Op27 compared to the LT1128. In fact, the coupling was higher for the DIP Op27 compared to an SOIC one I attached to the breadboard via an SOIC to DIP adapter (both were Op27-Gs, with spec'ed PSRR of 120 dB typ).
• To test the hypothesis, I compared the noise for the Op27 config, on the one hand with regulated (via D1000217) DC supply, and on the other, directly powered by the Tektronix supply. The latter configuration shows much higher coupling.
• I did have 0.1uF decoupling capacitors (I guess I should've used ceramic and not tantala) near the OpAmp power pins, and in fact, removing them had no effect on the level of this coupling
• As a quick check, I measured the spectrum of the DC power used to run the breadboard - it is supplied via D1000217. I used an RC network to block out the DC, but the measurement doesn't suggest a level of noise in the supply that could explain these peaks.
• The regulators are LM2941 and LM2991. They specify something like 0.03% of the output voltage as AC RMS, though I am not sure over what range of frequencies this is integrated over.
• But perhaps the effect is more subtle, some kind of downconversion of higher frequency noise, but isn't the decoupling cap supposed to protect against this?
• The 19.5 kHz harmonics seem to originate from the CRT display of the SR785 (SVGA).
• The manual doesn't specify the refresh rate, but from a bit of googling, it seems like this is a plausible number.
• The coupling seems to be radiative. The box housing the Busby preamp provides ~60dB attentuation of this signal, and the amplitude of the peaks is directly correlated to where I position the Busby box relative to the CRT screen.
• This problem can be avoided by placing the DUT and preamp sufficiently far from the SR785.

Punchlines:

1. The actual coildriver used, D010001, doesn't have a regulated power supply, it just draws the +/- 15V directly from Sorensens. I don't think this is good for low noise.
2. The LM6321 part of the circuit doesn't add any excess noise to the circuit, consistent with it being inside the unity gain feedback loop. In any case, with 4.5 kohm series resistance with the coil driver, we would be driving <2.5 mA of current, so perhaps we don't even need this?
Attachment 1: IMG_7060.JPG
Attachment 2: ETMXstitchced.pdf
Attachment 3: ETMXfullSpan.pdf
Attachment 4: PSRR.pdf
14024   Wed Jun 27 18:12:04 2018 gautamUpdateElectronicsCoil driver dewhitening

Summary:

I've been thinking about what we need to do to the de-whitening boards for the ITMs and ETMs, in order to have low noise actuators. Noting down what I have so far, so that people can comment / point out things I've overlooked.

Attachment #1: Block diagram schematic of the de-whitened signal path on D000183 as it currently exists. I've omitted the unity gain buffer stage at the output, though this is important for noise considerations.

Some considerations, in rough order of priority:

1. Why do we need de-whitening?
• Because we want the Johnson noise of the series resistor (4.5 kohm) in the coil driver path to dominate the current noise to the coils at ~200 Hz where we want to measure the squeezing.
2. What should the shape of this de-whitening filter be?
• The DAC noise was measured to be ~1 uV/rtHz at 200 Hz.
• The Johnson noise spectral density of 4.5 kohm at 300 K is ~9 nV/rtHz
• So we need ~60dB of attenuation at 200 Hz relative to DC. Currently, they have ~80dB of attenuation at 200 Hz.
• However, we also need to consider the control signal multiplied by the inverse of this shape in the digital domain (required for overall flat shape). This should not saturate the DAC range.
• Furthermore, we'd like for the shape to be such that we don't have a large transient when transitioning between high range and low noise modes. We should use the DARM control signal estimate to inform this choice.
3. What about the electronics noise of the de-whitening filter itself?
• This shows up at the input of the coil driver stage, and gets transmitted to the coil with unity gain.
• So we should aim for < 3nV/rtHz at 200 Hz, such that we are dominated by the Johnson noise of the 4.5 kohm series resistance [the excess will be 5%].
• This can be realized by using the passive network which is the final stage in the de-whitening (there is a unity gain output buffer stage implemented with LT1128, which we also have to account for).

I will experiment with a few different shapes and investigate noise and de-whitened digital signal levels based on these considerations. At the very least, I guess we should remove the x3 gain on the ETM boards, they have already been bypassed for the ITMs.

Attachment 1: DeWhiteningSketch.pdf
14027   Wed Jun 27 21:18:00 2018 gautamUpdateCDSLab maintenance scripts from NODUS---->MEGATRON

I moved the N2 check script and the disk usage checking script from the (sudo) crontab of nodus to the controls user crontab on megatron .

14032   Thu Jun 28 16:48:27 2018 gautamUpdateSUSSOS cage towers

For the upcoming vent, we'd like to rotate the SOS towers to correct for the large YAW bias voltages used for DC alignment of the ITMs and ETMs. We could then use a larger series resistance in the DC bias path, and hence, reduce the actuation noise on the TMs.

Today, I used the calibrated Oplev error signals to estimate what angular correction is needed. I disabled the Oplev loops, and drove a ~0.1 Hz sine wave to the EPICS channel for the DC yaw bias. Then I looked at the peak-to-peak Oplev error signal, which should be in urad, and calibrated the slider counts to urad of yaw alignment, since I know the pk-to-pk counts of the sine wave I was driving. With this calibration, I know how much DC Yaw actuation (in mrad) is being supplied by the DC bias. I also know the directions the ETMs need to be rotated, I want to double check the ITMs because of the multiple steering mirrors in vacuum for the Oplev path. I will post a marked up diagram later.

Steve is going to come up with a strategy to realize this rotation - we would like to rotate the tower through an axis passing through the CoM of the suspended optic in the vertical direction. I want to test out whatever approach we come up with on the spare cage before touching the actual towers.

Here are the numbers. I've not posted any error analysis, but the way I'm thinking about it, we'd do some in air locking so that we have the cavity axis as a reference and we'd use some fine alignment adjust (with the DC bias voltages at 0) until we are happy with the DC alignment. Then hopefully things change by so little during the pumpdown that we only need small corrections with the bias voltages.

SoS tower DC bias correction
Optic

EPICS excitation

[V pk-pk]

ETMX 0.06 110 1.83 -5.5305 -10.14
ITMX 0.02 180 9 -1.4500 -13.05
ITMY 0.02 120 6 -0.3546 -2.13
ETMY 0.06 118 1.97 0.5532 1.09

Some remarks:

1. Why the apparent difference between ITMs and ETMs? I think it's because the bias path resistors are 400 ohms on the ETMs, but 100 ohms on the ITMs
2. If we want the series resistance for the bias path to be 10 kohm, we'd only have ~800 urad actuation (for +10V DC), so this would be an ambitious level of accuracy.
14038   Thu Jul 5 10:15:30 2018 gautamUpdateSUSPRM watchdog tripped

PRM watchdog was tripped around 7:15am PT today morning. I restored it.

Attachment 1: PRM_watchdogTrip.png
14055   Thu Jul 12 11:13:39 2018 gautamUpdateGeneralOMC revival

Aaron and I are going to do the checkout of the OMC electronics outside vacuum today. At some point, we will also want to run a c1omc model to integrate with rtcds. Barring objections, I will set up this model on one of the spare cores on the physical machine c1ioo tomorrow.

14061   Thu Jul 12 23:59:14 2018 gautamUpdateGeneralVent objectives and prep

Vent objectives:

1. Install radiative heater setup in EY chamber.
2. Re-direct 50% of AS beam to OMC
• First, we need to check if the OMC trans PDs work. Else, we have to consider using some in-air PDs for the transmon.
• Check that OMC length PZT works.
• Check that OMC steering PZTs work (Koji and I have used this in 2016 to check AS beam clipping so they should work).

We only anticipate opening up the IOO chamber and the EY chamber.

Vent preparation: see here.

14063   Fri Jul 13 02:52:11 2018 gautamUpdateGeneralVent objectives and prep

[KA, GV]

1. Arm scan setup moved from West side of PSL table to North side of AP table
• Marconi is now providing the LO for the loop. A ~5m 50ohm BNC cable needs to be laid out from the PLL area to the NW corner of the AP table where the Agilent is for the TF measurement scheme which allows phase discrimination.
• We took this opportunity to characterize/improve the setup a bit, and also clean up the 10s of cables around the PSL table. There were some Video cables (75ohm instead of 50ohm ) that were part of the scanning setup which we excised.
• Mode matching onto beat PD on PSL table was improved - beat signal Vpp increased by factor of 2. PLL gain was adjusted accordingly.
• AUX power @AP table ~37mW (before recombination BS), ~3.7mW onto SRM, ~200uW onto ITMY.
• We got a beatnote in transmission of ~120uV (rms?) after optimizing alignment into Y arm cavity with the AUX frequency on an arm FSR.
• From Sandrine's calculations, I expected ~20mV of beat signal. We leave it to Annalisa and Terra to square that circle. Probably the MM into the arm isn't stellar either, and we didn't check the polarization of the aux beam (that it is matched to the IFO's p-pol).
• The entire AUX injection chain needs careful characterization before
2. Vent prep
• Both arms were locked to IR, TRY maximized using ASS, TRX maximized by hand.
• GTRY and GTRX were also maximized.
• All test mass/PRM/SRM oplevs were centered with this "good" alignment.
• PSL power into the IMC was cut from 1.07 W (measured after G&H mirror) to 97 mW, by rotating the waveplate immediately after the PSL (original angle 180deg, new angle 216 degrees).
• PMC was locked. I did not need to change any of the gain settings.
• 2" R=10% BS in the IMC REFL path was replaced with a Y2, so there is no MCREFL till we turn the power back up.
• IMC was locked. I touched up my IMC low power autolocker, but this probably needs a bit more touching up tomorrow. MC has remained locked at low power for ~25mins, but as I typed this, I jinxed it and it lost the lock. anyway we have good alignment references.
• PSL shutter will remain closed.

@SV, we are ready to vent tomorrow. Aaron is supposed to show up ~830am to assist.

Attachment 1: preVentStatus.png
14068   Fri Jul 13 18:01:13 2018 gautamUpdateGeneralLow power MC

After getting the go ahead from Steve, I removed the physical beam block on the PSL table, sent the beam into the IFO, and re-aligned the MC to lock at low power. I've also revived my low power autolocker (running on megatron), seems to work okay though the gains may not be optimal, but it seems to do the job for now. Nominal transmission when well aligned at low power is ~1200cts. I briefly checked Y arm alignment with the green, seems okay, but didn't try locking the Y arm yet. All doors are still on, and I'm closing the PSL shutter again while Keerthana and Sandrine are working near the AS table.

14075   Tue Jul 17 01:07:40 2018 gautamUpdateSUSETMY EQ stops

For the heater setup on EY table, I EQ-stopped ETMY. Only the face EQ stops (3 on HR face, 2 on AR face) were engaged. The EY Oplev HeNe was also shutdown during this procedure.

14085   Thu Jul 19 01:56:25 2018 gautamSummaryVACAUX pump shutdown

[koji, gautam]

Per Steve's instructions, we did the following:

• TP3fl pressure reading was 65 torr.
• TP3 controller reported pumping current of ~0.18A, temperature of 24C.
• We throttled the manual valve which was connecting the "AUX" pump to the TP3fl.
• The TP3fl pressure went up to 330 torr.
• TP3fl controller reported current of 0.22A, temperature of 24C.
• After ~5mins, we shut the AUX pump off.
• We have monitored it over the last 1hour, no red flags.
• (Before stopping AUX RP)
0:56AM TP3 I=0.18A, P=6W, 23degC, TP3FL: 66
• 0:59AM TP3 I=0.22A, P=7W, 23degC, TP3FL: 336
• 1:15AM TP3 I=0.21A, P=7W, 23degC, TP3FL: 320
• 1:31AM TP3 I=0.21A, P=7W, 23degC, TP3FL: 310
• 2:06AM TP3 I=0.21A, P=7W, 23degC, TP3FL: 301
• 5:06AM TP3 I=0.21A, P=7W, 23degC, TP3FL: 275
14094   Sat Jul 21 01:06:49 2018 gautamSummaryThermal CompensationY arm locking

I implemented this today. For now, the LSC output matrix is set to actuate on MC2 for Y arm locking. As expected, the transmission was much more stable, and the PLL control signal RMS was also reduced by factor of ~3. MC2 control signal does pick up a large (~2000 cts) DC component over a few hours, so we need to relieve this periodically.

Now that we have a workable ASS for the Y arm as well, we should be able to have more confidence in returning to the same beam spot position on the ETM and staying there during a scan using this technique.

The main improvement to be trialled next in the scanning is to improve the speed of scanning. As things stand, my script takes ~2.5 seconds per datapoint. If we can cut this in half, that'd be huge. On Wednesday night, we were extraordinarily lucky to avoid MC3 glitching, EPICS/slow machine failures, and GPIB freezes. Today, the latter reared its head. Fortunately, since I'm dumping data to file for each datapoint, this means we at least have data till the GPIB freeze.

 Quote: For future measurements, we should consider locking the IMC length to the arm cavity - this would eliminate such alignment drifts, and maybe also make the PLL control signal RMS smaller.

Not related to this work: Terra, Sandrine, Keerthana and I cleaned up the lab a bit today, and made better cable labels. Aaron and I have to clean up the OMC area a bit. Huge thanks to Steve for taking care of our mess elsewhere in the lab!

14095   Sat Jul 21 01:14:02 2018 gautamUpdateOMCPZT Jena driver board check

[Aaron, gautam]

We did a quick check of this board today. Main takeaways:

• There are two voltages (HV pos and HV neg) that are output from this unit.
• Presumably, these goto different piezoelectric elements, referenced to ground. Are there any spec sheets for these describing the geometry/threshold voltages?
• The outputs are:
• $\mathrm{HV_{+}} = 10(V_{\mathrm{DAC}}+V_{\mathrm{offset}}), \mathrm{HV_{-}} = 10(-V_{\mathrm{DAC}}+V_{\mathrm{offset}})$
• So with $V_{\mathrm{offset}} = 7.5 \mathrm{V}$, we expect to be able to use +/- 7.5 V of DAC range.
• The trim pot had to be adjusted to realize $V_{\mathrm{offset}} = 7.5 \mathrm{V}$​.
• I assume 150V is some kind of damage threshold of the PZT, so there is no benefit to using 10V offset voltage (as this would result in 200 V at full range DAC voltages).

With the correct $V_{\mathrm{offset}} = 7.5 \mathrm{V}$, we expect 0V from the DAC to result in 0 actuation on the mirror, assuming that an equal 75V goes to 2 PZTs mounted diametrically opposite on the optic. Hopefully, this means we have sufficient range to scan the input pointing into the OMC and get some sort of signal in the REFL signal (while length PZT is being scanned) which indicates a resonance.

We plan to carve out some IFO time for this work next week.

14101   Tue Jul 24 09:47:51 2018 gautamUpdateCamerasDeveloping neural networks on simulated video

I was thinking a little more about the way we are training the network for the current topology - because the network has no recurrent layers, I guess it has no memory of past samples, and so it doesn't have any sense of the temporal axis. In fact, Keras by default shuffles the training data you give it randomly so the time ordering is lost. So the training amounts to requiring the network to identify the center of the Gaussian beam and output that. So in the training dataset, all we need is good (spatial) coverage of the area in which the spot is most likely to move? Or is the idea to develop some tools to generate video with spot motion close to that on the ETM in lock, so that we can use it with a network topology that has memory?

 Quote: This looks like good progress. Instead of fixed sines or random noise, you should generate now a time series for the motion which is random noise but with a power spectrum similar to what we see for the ETM pitch motion in lock. You can use inverse FFT to get the time series from the open loop OL spectra (being careful about edge effects)
14104   Wed Jul 25 22:46:15 2018 gautamConfigurationComputersNDS access from outside

After this work, I've been having some trouble getting data with Python NDS. Eventually, I figured out that the nds connection request has to be pointed at '131.215.115.200' (the address of the NAT router which faces the outside world), port 31200 (it used to work with 'nds40.ligo.caltech.edu' or '131.215.115.189'). So the following snippet in python allows a connection to be opened. Offline access of frame data via NDS2 now seems possible.

import nds2
conn = nds2.connection('131.215.115.200',31200)
 Quote: So far, ssh (22), web services (30889), and elog (8081, 8080) were tested. We also need to test megatron NDS port forwarding and rsync for nodus, too.Finally I turned off the firewall rules of shorewall on nodus as it is no longer necessary.
14107   Fri Jul 27 02:30:51 2018 gautamUpdateGeneralGlitchy MC

Kevin and I saw some weird IMC / PEM BLRMS behaviour today - see Attached screenshot. Not sure what was happening with the IMC, but MCtrans was oscillating at ~3Hz for a good 20 minutes or so. I just killed the lock, and restarted MCautolocker on megatron. There was a strange feature in the 3-10Hz BLRMS around that time as well. All seems back to normal now...

Attachment 1: 38.png
14115   Mon Jul 30 11:05:44 2018 gautamUpdateSUSIFO SUS wonky

When I came in this morning:

• PMC was unlocked.
• Seis BLRMS were off scale.
• ITMX OSEM LEDs were dark on the CRT monitor even though Sat Box was plugged in.

Checking status of slow machines, it looked like c1sus, c1aux, and c1iscaux needed reboots, which I did. Still PMC would not lock. So I did a burtrestore, and then PMC was locked. But there seemed to be waaaaay to much motion of MCREFL, so I checked the suspension. The shadow sensor EPICS channels are reporting ~10,000 cts, while they used to be ~1000cts. No unusual red flags on the CDS side. Everything looked nominal when I briefly came in at 6:30pm PT yesterday, not sure if anything was done with the IFO last night.

Pending further investigation, I'm leaving all watchdogs shutdown and the PSL shutter closed.

A quick look at the Sorensens in 1X6 revealed that the +/- 20V DC power supplies were current overloaded (see Attachment #1). So I set those two units to zero until we figure out what's going on. Possibly something is shorted inside the ITMX satellite box and a fuse is blown somewhere. I'll look into it more once Steve is back.

Attachment 1: IMG_7102.JPG
14117   Mon Jul 30 16:11:54 2018 gautamUpdateSUSTrillium interface box is broken

[koji, steve, gautam]

We debugged this in the following way:

1. Disconnect all fuses in the terminal blocks coming from the +/- 20 VDC Sorensens.
2. Check that they are indeed isolated using DMM.
3. Test blocks of fuses in order to identify where the problem is happening (i.e. plug fuses in, turn up Sorensen voltage knobs, look for current overload). We did things in the following order:
• MC suspensions
• BS, PRM and SRM
• ITMY
• ITMX
• Trillium interface box.
4. Turns out that the Trillium box is the culprit.
5. Confirmed that the problem is in the trillium interface box and not in the seismometer itself by unplugging all cables leading out of the interface box, and checking that the problem persists when the box is powered on.

So for now, the power cable to the box is disconnected on the back end. We have to pull it out and debug it at some point.

Apart from this, megatron was un-sshable so I had to hard reboot it, and restart the MCautolocker, FSSslowPy and nds2 processes on it. I also restarted the modbusIOC processes for the PSL channels on c1auxex (for which the physical Acromag units sit in 1X5 and hence were affected by our work), mainly so that the FSS_RMTEMP channel worked again. Now, IMC autolocker is working fine, arms are locked (we can recover TRX and TRY~1.0), and everything seems to be back to a nominal state. Phew.

14122   Wed Aug 1 19:41:15 2018 gautamSummaryComputersRTCDS recovery, c1ioo changes

[Gautam Koji]

After this work, we recovered the nominal RTCDS state. The main points were:

1. We needed to restart the bind9 service on chiara such that the FEs knew their IP addresses upon reboot and hence, could get their root filesystems over NFS.
2. We recovered suspension local damping, IMC locking and POX/POY locking with nominal arm transmission.

Some stuff that is not working as usual:

1. The EX QPD is reporting strange transmission values - even with the PRM completely misaligned, it reports transmission of ~30. But we were able to lock the Xarm with the Thorlabs PD and revover transmission of ~1.15.
2. The X arm green does not stay locked to the cavity - the alignment looks fine, and the green flashes are strong, but the lock does not hold. This shouldn't be directly connected to anything we did today since the Green PDH servo is entirely analog.

I made a model change in c1x03 (the IOP model on c1ioo) to add a DAC part. The model compiled, installed and started correctly, and looking at dmesg on c1ioo, it recognises the DAC card as what it is. Next step is to use a core on c1ioo for a c1omc model, and actually try driving some signals.

Note that the only change made to the c1ioo expansion chassis was that a DAC card was installed into the PCIe bus. The adaptor card which allows interfacing the DAC card to an AI board was already in the expansion chassis, presumably from whenever the DAC was removed from this machine.

*I think I forgot to restart optimus after this work...

Attachment 1: CDS_overview.png
14123   Wed Aug 1 20:44:57 2018 gautamSummaryComputersc1omc model (re?)created

The main motivation behind adding a DAC card in c1ioo was to setup an RTCDS model for the OMC. Attachment #1 shows the new look CDS overview screen. Here is what I did.

Mostly, I followed instructions from when I setup the model for the EX green PZTs.

The model is just a toy for now (CDS parameters, ADC block and 2 CDS filter modules). I leave it to Aaron to actually populate it, check functionality etc. The path to the model is /opt/rtcds/caltech/c1/userapps/release/isc/c1/models/c1omc.mdl. I am listing the parameters set on the CDS_PARAMETERS block:

• host = c1ioo
• site = c1
• rate = 16k
• dcuid = 27 (which I chose after making sure that this dcuid was not used on this list which I also updated by adding c1omc and moving c1imc to "old")
• specific_cpu = 6 (again chosen after checking the available CPUs in the above list and confirming using the cset utility).
• shmem_daq = 1
• no_rfm_dma = 1

Building and installing model:

Once the model was installed, I logged into c1ioo, and built and installed the models using the usual rtcds make and rtcds install instructions. Before starting the model, I edited /diskless/root.jessie/etc/rtsystab to allow c1omc to be run on c1ioo. Using sudo cset set, I verified that CPU #6 is no longer listed (if I understand correctly, the RTCDS system takes over the core).

MEDM:

To reflect all this on the MEDM CDS OVERVIEW screen, I just edited the screen.

• Moved the orange explanation of bits over to the c1iscey panel to make space in the c1ioo panel.
• Edited the macros to reflect the c1omc parameters.

DAQD:

Finally, I followed the instructions here to get the channels into frames and make all the indicators green. Went into fb and restarted the daqd processes. All looks good . I'm going to leave the model running overnight to investigate stability. I forgot to svn commit the model tonight, will do it tomorrow.

The testing plan (at least initially) is to install the AA and AI boards from the OMC rack in 1X1/1X2. Then we will have short SCSI cables running from the ADC/DAC to these. The actual HV driving stages will remain in the OMC rack (NE corner of AS table).

@Steve, can we get 10 Male-Female D9 cables so that we can run them from 1X1/1X2 to the OMC rack?

Unrelated to this work: There were 2 crashes of the models on c1lsc, one ~6pm and one right now ~1030pm. The restart script brought everything back gracefully  ...

Attachment 1: CDS_OVERVIEW_withOMC.png
14125   Thu Aug 2 20:47:29 2018 gautamSummaryElectronicsX Green "Mystery" solved

I walked down to the X end and found that the entire AUX laser electronics rack isn't getting any power. There was no elog about this.

I couldn't find any free points in the power strip where I think all this stuff was plugged in so I'm going to hold off on resurrecting this until tomorrow when I'll work with Steve.

 Quote: The X arm green does not stay locked to the cavity - the alignment looks fine, and the green flashes are strong, but the lock does not hold. This shouldn't be directly connected to anything we did today since the Green PDH servo is entirely analog.
14126   Thu Aug 2 20:54:18 2018 gautamSummaryComputersc1omc model looks stable

Actually, c1lsc had crashed again sometime last night so I had to reboot everything this morning. I used the reboot script again, but I increased the sleep time between trying to start up the models again so that I could walk into the VEA and power cycle the c1lsc expansion chassis, as this kind of frequent model crash has been fixed by doing so in the past. Sure enough, there have been no issues since I rebooted everything at ~1030 in the morning.

The c1omc model itself has been stable as well, though of course, there is nothing in there at the moment. I may do a check of the newly installed DAC tomorrow just to see that we can put out a sine wave.

Steve has ordered the D-sub cabling that will allow us to route signals between AA/AI boards in 1X1/1X2 to the HV PZT electronics in the OMC rack. Things look setup for a measurement next week. Aaron will post a block diagram + photoz of what box goes where in the electronics racks.

14128   Fri Aug 3 14:35:56 2018 gautamSummaryElectronicsEX AUX electronics power restored

Steve and I restored the power to the EX AUX electronics rack. The power strip on the lowest shelf of the AUX rack now goes to another power strip laid out vertically along the NW corner of 1X9. The EX green locks to the arm just fine now.

14129   Fri Aug 3 15:53:25 2018 gautamUpdateSUSLow noise bias path idea

Summary:

The idea we are going with to push the coil driver noise contribution down is to simply increase the series resistance between the coil driver board output and the OSEM coil. But there are two paths, one for fast actuation and one that provides a DC current for global alignment. I think the simplest way to reduce the noise contribution of the latter, while preserving reasonable actuation range, is to implement a precision DC high-voltage source. A candidate that I pulled off an LT application note is shown in Attachment #1.

Requirements:

• The series resistance in the bias path should be $10 k\Omega$, such that the noise from this stage is dominated by the Johnson noise of said resistor, and hence, the current noise contribution is negligible compared to the series resistance in the fast actuation path ($4.5 k\Omega$).
• Since we only really need this for the test masses, what actuation range do we want?
• Currently, ETMY has a series resistance of $400\Omega$ and has a pitch DC bias voltage of -4 V.
• This corresponds to 10 mA of DC current.
• To drive this current through $10 k\Omega$, we need 100 V.
• I'm assuming we can manually correct for yaw misalignments such that 10mA of DC current will be sufficient for any sort of corrective alignment.
• So +/- 120 V DC should be sufficient.
• The current noise of this stage should be negligible at 100 Hz.
• The noise of the transistors and the HV supply should be suppressed by the feedback loop and so shouldn't be a significant contribution (I'll model to confirm).
• The input noise of the LT1055 is ~20nV/rtHz at 100 Hz, while the Johnson noise of $10 k\Omega$ is ~13nV/rtHz so maybe the low-passing needs to be tuned, but I think if it comes to it, we can implement a passive RC network at the output to achieve additional filtering.
• To implement this circuit, we need +/- 125V DC.
• At EX and EY, we have a KEPCO HV supply meant to be used for the Green Steering PZTs.
• I'm not sure if these can do bipolar outputs, if not, for temporary testing, we can transport the unit at EY to EX.

If all this seems reasonable, I'd like to prototype this circuit and test it with ETMX, which already has the high series resistance for the fast path. So I will ask Steve to order the OpAmp and transistors.

Attachment 1: LT1055_precOpAmp.pdf
14131   Fri Aug 3 18:54:58 2018 gautamUpdateSUSGlitchy MC1

The wall StripTool indicated that the IMC wasn't too happy when I came in today. Specifically:

• MC1 watchdog was tripped.
• Even in the tripped state, MC REFL spot on the camera showed spot motion that was too large to be explained as normal seismic driven motion (i.e. with local damping supposedly disabled).
• Strange excursions were observed in the MC1 shadow sensor signal levels as well, see Attachment #1 - negative values don't make any sense for this readout.

The last time this happened, it was due to the Sorensens not spitting out the correct voltages. This time, there were no indications on the Sorensens that anything was funky. So I just disabled the MCautolocker and figured I'd debug later in the evening.

However, around 5pm, the shadow sensor values looked nominal again, and when I re-enabled the local damping, the MC REFL spot suggested that the local damping was working just fine. I re-enabled the MCautolocker, MC re-locked almost immediately. To re-iterate, I did nothing to the electronics inside the VEA. Anyways, this enabled us to work on the X arm ASS (next elog).

Attachment 1: MC1_sensorAnomaly.png
14132   Fri Aug 3 19:02:11 2018 gautamUpdateASSX arm ASS recovery

[koji, gautam]

After I effected the series resistance change for ETMX, the X arm ASS didn't work (i.e. IR transmission would degrade if the servo was run). Today, we succeeded in recovering a functional ASS servo .

So both arms have working dither alignment servos now. But remember that the Y arm ASS gains have been set for locking the Y arm with MC2 as the actuator, not ETMY.

Details:

• Koji pointed out that the demodulated signals from the ETM dither are only used to center the spot on the ETM, and that we should first run the servo with existing settings with the ETM pitch and yaw spot centering loops disabled.
• This improved TRX level from ~0.8 to 1.1
• Next, we tried increasing the LO amplitudes by x5 to account for the reduced actuation of the dither on ETMX
• We then re-enabled the two loops that were earlier disabled.
• This resulted in TRX degrading very quickly.
• So we decided to try going back to the nominal LO gains, and reducing the gain of the two ETM spot centering loops.
• This did the trick, TRX went from 1.1 --> ~1.23, which is the nominal maximum pre-vent value.
• The snap file used to recover the correct settings to run the dither alignment servos have been updated, the old one has been backed up with today's datestamp.

We then tried to maximize GTRX using the PZT mirrors, but were only successful in reaching a maximum of 0.41. The value I remember from before the vent was 0.5, and indeed, with the IR alignment not quite optimized before we began this work, I saw GTRX of 0.48. But the IR dither servo signals indicate that the cavity axis may have shifted (spot position on the ITM, which is uncontrolled, seems to have drifred significantly, the Pitch signal doesn't stay on the StripTool scale anymore). So we may have to double check that the transmitted beam isn't falling off the GTRX DC PD.

14133   Sun Aug 5 13:28:43 2018 gautamUpdateCDSc1lsc flaky

Since the lab-wide computer shutdown last Wednesday, all the realtime models running on c1lsc have been flaky. The error is always the same:

[58477.149254] c1cal: ADC TIMEOUT 0 10963 19 11027 [58477.149254] c1daf: ADC TIMEOUT 0 10963 19 11027 [58477.149254] c1ass: ADC TIMEOUT 0 10963 19 11027 [58477.149254] c1oaf: ADC TIMEOUT 0 10963 19 11027 [58477.149254] c1lsc: ADC TIMEOUT 0 10963 19 11027 [58478.148001] c1x04: timeout 0 1000000  [58479.148017] c1x04: timeout 1 1000000  [58479.148017] c1x04: exiting from fe_code()

This has happened at least 4 times since Wednesday. The reboot script makes recovery easier, but doing it once in 2 days is getting annoying, especially since we are running many things (e.g. ASS) in custom configurations which have to be reloaded each time. I wonder why the problem persists even though I've power-cycled the expansion chassis? I want to try and do some IFO characterization today so I'm going to run the reboot script again but I'll get in touch with J Hanks to see if he has any insight (I don't think there are any logfiles on the FEs anyways that I'll wipe out by doing a reboot). I wonder if this problem is connected to DuoTone? But if so, why is c1lsc the only FE with this problem? c1sus also does not have the DuoTone system set up correctly...

The last time this happened, the problem apparently fixed itself so I still don't have any insight as to what is causing the problem in the first place . Maybe I'll try disabling c1oaf since that's the configuration we've been running in for a few weeks.

14134   Sun Aug 5 13:45:00 2018 gautamUpdateSUSETMX tripped

Independent from the problems the vertex machine has been having (I think, unless it's something happening over the shared memory network), I noticed on Friday that the ETMX watchdog was tripped. Today, once again, the ETMX watchdog was tripped. There is no evidence of any abnormal seismic activity around that time, and anyways, none of the other watchdogs tripped. Attachment #1 shows that this happened ~838am PT today morning. Attachment #2 shows the 2k sensor data around the time of the trip. If the latter is to be believed, there was a big impulse in the UL shadow sensor signal which may have triggered the trip. I'll squish cables and see if that helps - Steve and I did work at the EX electronics rack (1X9) on Friday but this problem precedes our working there...

Attachment 1: ETMX_tripped.png
Attachment 2: ETMX_tripped_zoom.png
14135   Sun Aug 5 15:43:50 2018 gautamUpdateSUSAnother low noise bias path idea

• Attachment #1 shows the proposed schematic.
• It consists of a second order section with Gain x10 to map the +/-10V DC range of the DAC to +/- 100V DC such that we preserve roughly the same amount of DC actuation range.
• Corner frequency of the SOS is set to ~0.7 Hz. In hindsight, maybe this is more aggressive than necessary, we can tune this.
• DC gain is 20 dB (typo in the text where I say the DC gain is x15, though we could go with this option as well I think if we want a larger series resistance).
• A first order passive low-pass stage is added to filter out the voltage noise of the PA91, which dominates the output voltage noise (next bullet).
• Attachment #2 shows the transfer function from input to output
• The two traces compare having just a single SOS filtering stage vs the current topology of having two SOS stages.
• The passive output RC network is necessary in either case to filter the voltage noise of the PA91 OpAmp.
• For the DAC noise, I just assumed a flat noise level of $5 \mu V / \sqrt{\mathrm{Hz}}$, I don't actually know what this is for the Acromag DACs.
• Attachments #3 shows a breakdown of the top 5 noise contributions.
• The PA91 datasheet doesn't give current noise information so I just assumed $1 fA / \sqrt{\mathrm{Hz}}$, which was what was used for the PA85 in the existing opamp.lib file.
• The voltage noise is modelled as $4.5 \sqrt{1+\frac{80}{f}} nV / \sqrt{\mathrm{Hz}}$, which seems to line up okay with the plot on Pg4 of the datasheet.
• So the model suggests we will be dominated by the voltage noise of the PA91.
• Attachment #4 translates the noise into current noise seen by the actuator.
• I add the Johnson noise contribution of the series resistance for this path, which is assumed to be $10 k \Omega$.
• For comparison, I add the filtered DAC noise contribution, and Johnson noise of the proposed series resistance in the fast path.
• For the bias path, we are dominated by the Johnson noise of the series resistor from ~60 Hz upwards.
• It's not quite fair to say that the Johnson noise of the resistance in the fast path dominates, the quadrature sum of fast and bais paths will be ~1.2 times of the former alone.
• Bottom line: we will be in the regime of total current noise of ~2.2 pA/rtHz, where I think Kevin's modeling suggests we can see some squeezing.

The question still remains of how to combine the fast and bias paths in this proposed scheme. I think the following approach works for prototyping at least:

• Remove the series resistance on the existing coil driver boards' bias path, hence isolating this from the coil.
• Route the DB15 output connector from the coil driver board (which is now just the fast actuation signals) into a sub-sattelite box housing the bias path electronics.
• Sum the two signals as it is done now, by simply having a conductor (PCB trace) merge the two paths after their respective series resistances.

In the longer term, perhaps the Satellite Box revamp can accommodate a bias voltage summation connector.

 Quote: Bah! Too complex.

I have neglected many practical concerns. Some things that come to mind:

1. Is it necessary to protect the upstream DAC from some potential failure of the PA91 in which the high voltage appears at the input?
2. What is the correct OpAmp for this purpose? This chart on Apex's page suggests that PA15, PA85, PA91 and PA98 are all comparable in terms of drive capability, and the spec sheets don't suggest any dramatic differences. Some LIGO circuits use PA85, some use PA90, but I can't find any that use PA91. Perhaps Rana/Koji can comment about this.
3. What kind of protection is necessary for the PA91 power?
4. What is the correct way to do heat management? Presumably we need heatsinks, and in fact, there is a variant of the packaging style that has "formed" legs, which from what I can figure out, allow the heat sink plane on the PA91 to be parallel to the PCB surface. But I think the heat-sink wisdom suggests vertical fins are the most efficient (not sure if this holds if the PCB is inside a box though). What about the PCB itself? Are some kind of special traces needed?
5. Can we use the current-limiting resistor feature on the PA91? The datasheet seems to advice against it for G>10 configurations, which is what we need, although our requirement is only at DC so I don't know if that table is applicable to this circuit.
6. Are 3W resistors sufficient? I think we require only 10mA maximum current to preserve the current actuation range, so 100 V * 10mA = 1W, so 3W leaves some safety margin.
7. All capacitors should be rated for 500 V per the datasheet.
Attachment 1: HV_Bias_schematic.pdf
Attachment 2: TF.pdf
Attachment 3: bias.pdf
Attachment 4: HVbias_currentNoise.pdf
14136   Mon Aug 6 00:26:21 2018 gautamUpdateCDSMore CDS woes

I spent most of today fighting various CDS errors.

• I rebooted c1lsc around 3pm, my goal was to try and do some vertex locking and figure out what the implications were of having only ~30% power we used to have at the AS port.
• Shortly afterwards (~4pm), c1lsc crashed.
• Using the reboot script, I was able to bring everything back up. But the DC lights on c1sus models were all red, and a 0x4000 error was being reported.
• This error is indicative of some timing issue, but all the usual tricks (reboot vertex FEs in various order, restart the mx_streams etc) didn't clear this error.
• I checked the Tempus GPS unit, that didn't report any obvious problems (i.e. front display was showing the correct UTC time).
• Finally, I decided to shut down all watchdogs, soft reboot all the FEs, soft reboot FB, power cycle all expansion chassis.
• This seems to have done the trick - I'm leaving c1oaf disabled for now.
• The remaining red indicators are due to c1dnn and c1oaf being disabled.

Let's see how stable this configuration is. Onto some locking now...

Attachment 1: CDSoverview.png
14139   Mon Aug 6 14:38:38 2018 gautamUpdateCDSMore CDS woes

Stability was short-lived it seems. When I came in this morning, all models on c1lsc were dead already, and now c1sus is also dead (Attachment #1). Moreover, MC1 shadow sensors failed for a brief period again this afternoon (Attachment #2). I'm going to wait for some CDS experts to take a look at this since any fix I effect seems to be short-lived. For the MC1 shadow sensors, I wonder if the Trillium box (and associated Sorensen) failure somehow damaged the MC1 shadow sensor/coil driver electronics.

 Quote: Let's see how stable this configuration is. Onto some locking now...
Attachment 1: CDScrash.png
Attachment 2: MC1failures.png
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