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ID Date Author Type Categoryup Subject
  12968   Wed May 3 17:16:30 2017 PrafulUpdateElectronicsNew Altium Schematic Design for Microphone Amp

I made an Altium schematic for the microphone amplifier circuit for fabrication.

mic_schematicv2.pdf

Attachment 1: mic_schematicv2.pdf
mic_schematicv2.pdf
  13082   Tue Jun 27 16:11:28 2017 gautamUpdateElectronicsCoil whitening

I got back to trying to engage the coil driver whitening today, the idea being to try and lock the DRMI in a lower noise configuration - from the last time we had the DRMI locked, it was determined that A2L coupling from the OL loops and coil driver noise were dominant from ~10-200Hz. All of this work was done on the Y-arm, while the X-arm CDS situation is being resolved.

To re-cap, every time I tried to do this in the last month or so, the optic would get kicked around. I suspected that the main cause was the insufficient low-pass filtering on the Oplev loops, which was causing the DAC rms to rail when the whitening was turned on. 

I had tried some loop-tweaking by hand of the OL loops without much success last week - today I had a little more success. The existing OL loops are comprised of the following:

  • Differentiator at low frequencies (zero at DC, 2 poles at 300Hz)
  • Resonant gain peaked around 0.6 Hz with a Q of ______ (to be filled in)
  • BR notches 
  • A 2nd order elliptic low pass with 2dB passband ripple and 20dB stopband attenutation

THe elliptic low pass was too shallow. For a first pass at loop shaping today, I checked if the resonant gain filter had any effect on the transmitted power RMS profile - turns out it had negligible effect. So I disabled this filter, replaced the elliptic low pass with a 5th order ELP with 2dB passband ripple and 80dB stopband attenuation. I also adjusted the overall loop gain to have an upper UGF for the OL loops around 2Hz. Looking at the spectrum of one coil output in this configuration (ITMY UL), I determined that the DAC rms was no longer in danger of railing.

However, I was still unable to smoothly engage the de-whitening. The optic again kept getting kicked around each time I tried. So I tried engaging the de-whitening on the ITM with just the local damping loop on, but with the arm locked. This transition was successful, but not smooth. Looking at the transmon spot on the camera, every time I engage the whitening, the spot gets a sizeable kick (I will post a video shortly).  In my ~10 trials this afternoon, the arm is able to stay locked when turning the whitening on, but always loses lock when turning the whitening off. 

The issue here is certainly not the DAC rms railing. I had a brief discussion with Gabriele just now about this, and he suggested checking for some electronic voltage offset between the two paths (de-whitening engaged and bypassed). I also wonder if this has something to do with some latency between the actual analog switching of paths (done by a slow machine) and the fast computation by the real time model? To be investigated.

GV 170628 11pm: I guess this isn't a viable explanation as the de-whitening switching is handled by the one of the BIO cards which is also handled by the fast FEs, so there isn't any question of latency.

With the Oplev loops disengaged, the initial kick given to the optic when engaging the whitening settles down in about a second. Once the ITM was stable again, I was able to turn on both Oplev loops without any problems. I did not investigate the new Oplev loop shape in detail, but compared to the original loop shape, there wasn't a significant difference in the TRY spectrum in this configuration (plot to follow). This remains to be done in a systematic manner. 

Plots to support all of this to follow later in the evening.

Attachment #1: Video of ETMY transmission CCD while engaging whitening. I confirmed that this "glitch" happens while engaging the whitening on the UL channel. This is reminiscent of the Satellite Box glitches seen recently. In that case, the problem was resolved by replacing the high-current buffer in the offending channel. Perhaps something similar is the problem here?

Attachment #2: Summary of the ITMY UL coil output spectra under various conditions.

 

Attachment 1: ETMYT_1182669422.mp4
Attachment 2: ITMY_whitening_studies.pdf
ITMY_whitening_studies.pdf
  13158   Wed Aug 2 09:40:55 2017 SteveUpdateElectronicsspare ILIGO electronics

Spare ILIGO electronics temporarly stored in the east arm. We need cabinet space.

Attachment 1: iLIGOspares.jpg
iLIGOspares.jpg
Attachment 2: spareIligo.jpg
spareIligo.jpg
  13174   Wed Aug 9 11:33:49 2017 gautamUpdateElectronicsMC2 de-whitening

Summary:

The analog de-whitening filters for MC2 are different from those on the other optics (i.e. ITMs and ETMs). They have one complex pole pair @7Hz, Q~sqrt(2), one complex zero pair @50Hz, Q~sqrt(2), one real pole at 2.5kHz, and one real zero @250Hz (with a DC gain of 10dB).

Details:

I took the opportunity last night to measure all 4 de-whitening channel TFs. Measurements and overlaid LISO fits are seen in Attachment #1. 

The motivation behind this investigation was that last week, I was unable to lock the IMC to one of the arms. In the past, this has been done simply by routing the control signal of the appropriate arm filter bank (e.g. C1:LSC-YARM_OUT) to MC2 instead of ETMY via the LSC output matrix (if the matrix element to ETMY is 1, the matrix element to MC2 is -1).

Looking at the coil output filter banks on the MC2 suspension MEDM screen (see Attachment #2), the positions of filters in the filter banks is different from that on the other optics. In general, the BIO outputs of the DAC are wired such that disengaging FM9 on the MEDM screen engages the analog de-whitening path. FM10 then has the inverse of the de-whitening filter, such that the overall TF from DAC to optic is unity. But on MC2, these filters occupy FM7 and FM8, and FM9 was originally a 28Hz Elliptic Low-pass filter.

So presumably, I was unable to lock the IMC to an arm because for either configuration of FM9 (ON or OFF), the signal to the optic was being aggressively low-passed. To test this hypothesis, I simply copied the 28Hz elliptic to FM6, put a gain of 1 on FM9, left it engaged (so that the analog path TF is just flat with gain x3), and tried locking the IMC to the arm again - I was successful. See Attachment #3 for comparison of the control signal spectra of the X-arm control signal, with the IMC locked to the Y-arm cavity.

In this test, I also confirmed that toggling FM9 in the coil output filter banks actually switches the analog path on the de-whitening boards.

Since I now have the measurements for individual channels, I am going to re-configure the filter arrangement on MC2 to mirror that on the other optics. 


Unrelated to this work: the de-whitening boards used for MC1 and MC3 are D000316, as opposed to D000183 used for all other SOS optics. From the D000316 schematic, it looks like the signals from the AI board are routed to this board via the backplane. I will try squishing this backplane connector in the hope it helps with the glitching MC1 suspension.


GV Aug 13 11:45pm - I've made a DCC page for the MC2 dewhitening board. For now, it has the data from this measurement, but if/when we modify the filter shape, we can keep track of it on this page (for MC2 - for the other suspensions, there are other pages). 

Attachment 1: MC2deWhites.pdf
MC2deWhites.pdf
Attachment 2: MC2Coils.png
MC2Coils.png
Attachment 3: MC2stab.pdf
MC2stab.pdf
  13176   Wed Aug 9 12:05:57 2017 ranaUpdateElectronicsdata archiving

This kind of data fitting and analysis is really useful. We should figure out a way to archive it. Perhaps the data files and fitting stuff can be put into GIT in some smart way? The fit results can be added to the 40m MC electronics DCC tree. Then the links can be added to this elog.

  13371   Wed Oct 11 10:29:43 2017 SteveUpdateElectronicsSR560 noise level

Gautam and Steve,

All 3 show the same noise level ~80 nV / rt Hz at 1 kHz as shown. Batteries ordered to be replaced in the top 2

We'll do more measurement to see how can we get to 4 nV / rt Hz  specification level.

Attachment 1: sr560.jpg
sr560.jpg
Attachment 2: sr560noise.jpg
sr560noise.jpg
  13373   Wed Oct 11 17:59:45 2017 ranaUpdateElectronicsSR560 noise level

these are not the SR785 settings that you're looking for

Quote:

Gautam and Steve,

All 3 show the same noise level ~80 nV / rt Hz at 1 kHz as shown. Batteries ordered to be replaced in the top 2

We'll do more measurement to see how can we get to 4 nV / rt Hz  specification level.

To get low noise measurements on the SR785, you have to have the input range set to -50 dB, not +20 dB. Its not within the powers of commercial electronics ADCs to give you a 10 nV noise floor with +10 V input signals. The SR560 has an input referred noise of 5 nV/rHz, so the output noise should be 5e-9 x 500 = 2.5 uV/rHz. Your picture shows it giving 1 uV RMS, so you also need to use the PSD units.

  13425   Fri Nov 10 18:57:41 2017 ranaSummaryElectronicsIthaca 1201 vs. SR560

I characterized the black Ithaca 1201 pre-amp that we had sitting in the racks. It works fine and the input referred noise is < 10 nV/rHz. I also checked that the filter selection switches on the front panel did what they claim and that the gain knob gives us the correct gain.

For comparison I have also included the G=100, 1000 input referred noise of one of the best SR560 that we have (s/n 02763) in the lab. Above a few Hz, the SR560 is better, but for low frequency measurements it seems that the 1201 is our friend.

As with the SR560, you don't actually get low noise performance for G < 100, due to some fixed output noise level.

Steve:  sn48332 of Ithaca 1201

Attachment 1: Ithaca1201.pdf
Ithaca1201.pdf
  13494   Sun Dec 31 12:43:50 2017 ranaSummaryElectronicsSR560: reworking

I have ordered some LSK389A (in both the SOIC-8 and TO-71 packages) to replace the SR560's default front end FET pair (NPD5565).

I'm going to rework s# 00619 once these new FETs come in. Also ordered 100 of the SOIC-8 to DIP-8 adapter boards from Digikey.

This plot shows the current performance compared to the Rai Low Noise box. I expect the FETs should let us get to ~1.5 nV/rHz with the SR560.

Attachment 1: Preamps.pdf
Preamps.pdf
  13516   Mon Jan 8 20:50:01 2018 ranaSummaryElectronicsSR560: reworking

I replaced the NPD5565 with a LSK389 (SOIC-8 with DIP adapter). There was a noise reduction of ~30%, but not nearly as much as I expected. I wonder if I have to change the DC bias current on these to get the low noise operation?

https://photos.app.goo.gl/hsMwsif7NLscsgpx1

  13563   Sat Jan 20 01:20:37 2018 gautamUpdateElectronicsWhitening filter D990694

We use D990694 in various places. Today, Rana alerted me to an important consideration to be kept in mind when we use this board, which I found quite interesting. I still don't understand the problem at the BJT level, but I think one can appreciate the problem without going to the transistor design of the LT1125. I'm attaching an annotated schematic of the whitening section in question. If the following assumptions are valid, then I think my picture is valid.

  1. The switch used to bypass the various whitening gain stages, namely the ADG333ABR, has infinite impedance in the "OFF" state, such that when the 24dB gain stage is bypassed, U28A (or in general one of the 4 quad op-amps) is forced to drive it's output voltage across 1.0665 kohms of resistance.
  2. The individual LT1125 Op Amps can drive a maximum of 30mA of current.

Then, as one can see in the attached schematic, when we set the gain of any input to <24dB, we must ensure that the input voltage is less than approximately 2V. Otherwise, by asking too much of the first stage op-amp in the quad IC LT1125, we may be messign around with all the 4 op amps in the quad! Even the 0dB setting is not immune to this problem, as it uses one of the 4 op amps.

I don't think the usual rules of calculating the gain of a non-inverting amplifier (G = 1 + Rf/Ri) remain valid even when the op-amp is forced to drive more output current than it can, and I don't have a way to quantify the possible interference between the 4 op amps in the quad - but does this seem like a valid conclusion? If so, we must check signal levels of various LSC signals. AS55 signals currently have the 0dB gain setting - I had turned this down from 6dB some months ago, because it seemed like the ADC was saturating at the 6dB gain setting, which suggests that the input voltage is ceratinly > 2V, and AS55_Q is what is used for MICH control in the DRMI. All of my noise budgeting work over the last few months used this setting, I wonder if they are all invalid surprise


Now that I think about this a bit more - this problem shouldn't be significant for the usual LSC degrees of freedom when in lock, as the huge DC gain of the loop should squish large DC values of the error signals, and so there shouldn't be any danger of overloading the LT1125. But I don't know if we are being hurt by this effect when flashing through resonances, when the PDH horn-to-horn voltage can be quite high (which is in principle a good thing?). I don't know if there is any "hysterisis" effect where the overloaded quad IC has some relaxation time before it returns to normal operation, and if we are being limited in our ability to catch lock because if this effect. 

The concerns remain valid for th ALS demodulated error signals though, for which the signals will remain large throughout.

Attachment 1: whiteningBoardLimitations.pdf
whiteningBoardLimitations.pdf
  13564   Sat Jan 20 15:57:11 2018 ranaUpdateElectronicsWhitening filter D990694

this is the note from Hartmut Grote on this topic from 2004

  13568   Tue Jan 23 01:33:23 2018 gautamUpdateElectronicsWhitening filter D990694

After discussing with Koji, we looked at the aLIGO incarnation of this board. Interestingly, it too has a similar topology of 4 switchable gain stages with gains of 24, 12, 6 and 3dB. The main differences are that they use single Op27 ICs instead of the quad LT1125s, and also, they use a different combination of feedback resistors to realize the various gains. 

We considered upping the feedback resistance (R15, R143) on the 24dB gain stage of our boards from (1k, 66.5ohms) to (3k, 200ohms) as on the aLIGO boards - but this doesn't really help? Because KCL demands that the same current flow in R15 and R143, and so the output Vsat of the op amp and its max current driving capabilities in combination determine if the inverting input can follow the non inverting input?

As Hartmut points out in his note, he was able to access the full range of ADC voltages when the gain was set to 3dB, despite the fact that the LT1125 was still getting internally saturated. Operating with minimum 24dB whitening gain doesn't really solve the problem either because the problem just gets shifted to the next gain stage in the chain, and we still have saturation. I also don't have a feeling for how much differential voltage these LT1125s can sustain before they are damaged - I guess the planned THD check will reveal if they are okay or not.

It seems to me like the only way to truly fix this problem of one stage saturating and screwing up the others is to use single Op27s (or equivalent) in place of the quad LT1125s. The aLIGO design also has a series resistance to the non-inverting input - this can help prevent current overdraw from the previous stage (due to a lowered input impedance of the OpAmp - but I wonder how low this can go?).

Quote:

this is the note from Hartmut Grote on this topic from 2004

 

  13569   Tue Jan 23 01:56:18 2018 gautamUpdateElectronicsTeledyne AP1053

I have acquired 5 pieces of the Teledyne AP1053 from Koji - these are now at the 40m. I will determine an appropriate location for storage of these and update. We are also looking to acquire 5 more of these. The combination of high power output (26dBm), low gain (10dB), and low noise figure (1.5dB) are quite uncommon in an amplifier and so these should be used only when such properties are required simultaneously.

*Steve informs me that these amps have been stored in the RF cabinet E6 along the east arm.

Steve's note: Teledyne rf amp product selection guide

                   Teledyne rf low noise amp guide

 

Attachment 1: DSC00022.JPG
DSC00022.JPG
  13572   Wed Jan 24 00:48:47 2018 gautamUpdateElectronicsWhitening filter D990694

I plan to do some characterization of this problem. The plan is to use THD as a metric for whether we are having hidden saturations. Pg 9 of the LT1125 datasheet tells us what fraction of THD to expect. I will use one of the several unused DAC channels available at the LSC rack to drive a 100Hz sine wave into one of the inputs of the whitening chassis, and measure the THD up to a reasonable harmonic number (will probably be set by the ADC noise) for (i) various whitening gain settings and (ii) various input signal amplitudes.

The motivation is to attempt to quantify the problem better:

  1. How bad is it to have one or more of the OpAmps in the quad IC either saturated to its voltage rails, or max output current?
  2. Can we reproduce Hartmut's observations?
  3. Are the OpAmps already irreversibly damaged because of extended abuse?

Then we can decide what, if anything, to do about this issue.

  13632   Tue Feb 13 22:35:21 2018 gautamUpdateElectronicsPSL table power supply cleanup

The main motivation for this work is that I want +15VDC power available on the PSL table to hookup the Teledyne box that Koji made a week ago and do some noise measurements on my revised IR ALS signal chain. But I think this is a good opportunity to effect a number of changes I've been wanting to do for a while.

Tomorrow, Steve and I will do the following:

  1. Fix the AOM driver power cabling that I broke.
  2. Make the AOM +24VDC power supply independent - right now it is shared between the AOM driver and the two ZHL-3-A amplifiers.
  3. Tap an independent +24VDC power supply from 1X1 for the ZHL-3A amplifiers (I guess one power supply and fuse is sufficient for both amplifiers since they are in the same box).
  4. Tap an independent +15VDC power supply for the Teledyne box.
  5. Tap an independent +15VDC power supply for the little fan on the back of the PSL controller, that is currently powered by a bench supply (+12VDC, but it's just a fan, so +15VDC or +10VDC will do just fine, and these are the Sorensen levels we have).
  6. Tap an independent +/-24VDC power supply for the FSS summing box. Right now it is being powered by a bench supply under the PSL table. The indicated supply voltage on the box is +/-18V. But according to the schematic, this +/-18V get regulated down to +/- 15V, so we may as well use +/-24V which is available from the Sorensens in 1X1 (there is no +/-18VDC Sorensen there). The datasheets for the 7815 and 7915 ICs suggest that this will be just fine.
  7. Where possible, make at least 1 spare outlet for each supply voltage available at 1X1, such that in future, tapping extra supply points won't be such a huge pain.

So in summary, we will need, at 1X1, (at least, including 1 spare for future work):

  • New +24VDC connections ------ 3x
  • New -24VDC connections ------- 2x
  • New +15VDC connections ------ 3x
  13633   Wed Feb 14 17:49:22 2018 gautamUpdateElectronicsPSL table power supply cleanup

[steve, gautam]

We completed this work today. Need to clean up a little (i.e. coil excess cable lengths, remove unused cables etc), which we will do tomorrow. All connections have been made at the DIN rail end, but the fuses have not been inserted yet, so there is no voltage reaching the PSL table on any of the newly laid out cables. We also need to establish two +15VDC connections at the DIN rail side. I may establish this later in the evening, as the main point of this work was to get the Teledyne signal path operational. Setting up these DIN connectors is actually a huge pain, we tried to setup a few extra ports for the voltages we used today so that in future, life is easier for whoever wants to pipe DC power to the PSL table. The rule is, however, to re-establish the same number of open ports for each voltage as was available when you started.

For the ZHL-3A, Teledyne, and AOM driver cables, we used 18AWG, 2 conductor, twisted wire, while for the PSL fan we used 20AWG. For the FSS box, we decided to use the 3 conductor 24AWG twisted wire. I believe that these wire gauge choices are appropriate given the expected current in each of these paths.

Pictures + further details tomorrow.

gautam @ 1030pm: there was some mistake with the +15V wiring we did in the evening (the PSL fan and Teledyne cables were plugged into the wrong DIN terminal blocks). I fixed this, and also routed +15VDC to the newly installed set of terminal blocks for this purpose (since we had run out of +15VDC ports at 1X1). After checking voltages at both 1X1 and on the PSL table, I hooked up

  1. FSS Summing box
  2. Teledyne amplifier
  3. ZHL-3A amplifiers

to their newly laid out power supplies. IMC locks so looks like the FSS box is doing fine yes. So we can recover one bench power supply from under the PSL table on the east side. I didn't hook up the AOM driver just now because of some accessibility issues, and I'd also like to do an ALS beat spectrum measurement if possible.

Attachment 1: IMG_5135.JPG
IMG_5135.JPG
Attachment 2: Sorensens_1X1_before.JPG
Sorensens_1X1_before.JPG
Attachment 3: Sorensens_1X1_after.JPG
Sorensens_1X1_after.JPG
  13645   Wed Feb 21 00:04:27 2018 gautamUpdateElectronicsTemporary RF power monitor setup

I made a voltage divider using a 20.47kohm and 1.07kohm (both values measured with a DMM). The whole thing is packaged inside a Pomona box I found lying around on the Electronics bench. I have hooked it up to the ALSY_I channel and will leave it so overnight. The INMON of this channel isn't DQed, but for this test, the 16Hz EPICS data will suffice. I've locked the EX laser to the arm, enabled slow temperature servo to allow overnight lock (hopefully) and disabled LSC mode (as locking the arm to the MC tends to break the green lock)

To convert the INMON counts to RF power, I will use (based on my earlier calibration of this monitor channel, see DCC document for the demod chassis).

\mathrm{P_{RF}} (\mathrm{dBm}) = \frac{19.13 \times \frac{cts}{1638.4} - 10.23}{0.12}


1AM update: Attachment #1 shows that the RF amplitude has been relatively stable (less than 10% of nominal value variation) over the course of the last hour or so. Even though there is some low frequency drift over timescales of ~20mins, no evidence of the wild ~20dB amplitude changes I saw last week. The signs are encouraging...

overnight update: See Attachment #2 - looking at the past 11 hours of second trend data during which the arm stayed locked, there actually seems to have been more significant variation in the beatnote amplitude. Swings of up to 6dBm are seen on a ~20min timescale, while there is also some longer term drift over 12 hours by a couple of dBm. There is probably a systematic error in the Y-axis, as I measured the RF power at the input of the power splitter at the LSC rack to be ~3dBm, so I expect something closer to 0dBm to be the LO input power which is what I am monitoring. So further debugging is required - I think I'll start by aligning the X fiber coupled beam to one of the fiber's special axes.

Attachment 1: RFbeatAmp.png
RFbeatAmp.png
Attachment 2: BeatMouthX_RFAM_20180221.pdf
BeatMouthX_RFAM_20180221.pdf
  13649   Thu Feb 22 10:49:11 2018 SteveUpdateElectronicsrack power supplies checked

All rack power supplies labeled if their load changed.

 

Attachment 1: 1X1_DC.jpg
1X1_DC.jpg
Attachment 2: 1X5_DC.jpg
1X5_DC.jpg
Attachment 3: 1X9_DC.jpg
1X9_DC.jpg
Attachment 4: 1X8_DC.jpg
1X8_DC.jpg
Attachment 5: 1Y2_DC.jpg
1Y2_DC.jpg
Attachment 6: 1Y1_DC.jpg
1Y1_DC.jpg
Attachment 7: AUX_1Y2_DC.jpg
AUX_1Y2_DC.jpg
Attachment 8: AUX_OMC_DC.jpg
AUX_OMC_DC.jpg
  13665   Mon Mar 5 11:58:24 2018 gautamUpdateElectronicsThree opamps walked onto an AA board

For testing the new IR ALS noise, we had decided that we would like to use the differential output of the demodulated ALS beat signal, as opposed to a single-ended output, as measurements suggested the former to be a lower noise configuration than the latter. For this purpose, Koji and I acquired a couple of old AA boards from the WB electronics shop. These are however, rev2 of the board, whereas the latest version is v6. The main difference between v2 and v6 is that (i) the THS4131 instrumentation amplifier has the Vocm pin grounded in v6 but is floating in v2 and (ii) the buffer opamps are AD8622 in v6 but are AD8672 in v2. But in fact, the boards we have are stuffed with AD8682

I talked to Rich on Friday, and he seemed to think the AD8672 didn't have any issues noise-wise, the main reason they changed it was because its power consumption was high, and was causing overheating when several of these 1U chassis were packed closely together in an electronics rack. But the AD8682, which is what we have, has comparable power consumption to the AD8622. It is however a JFET opamp, and the voltage noise is a bit higher than the AD8622. 

I am sure there is a way to LISO model a differential output opamp like the THS4131, but I thought I'd simulate the noise in LTSPICE instead. But I couldn't get that to work. So instead, I just measured the transfer function and noise of a single channel, for which Koji had expertly hacked together a custom shorting of the THS4131 Vocm pin to ground. Attachments #1 and #2 show the measurement. All looks good. Note that the phase is 180 at DC because I had hooked up the input signal opposite to what it should have been. The voltage noise of the differential outputs (each measured w.r.t. ground, with both inputs shorted to ground by a short patch cable) at 10 Hz is <100nV/rtHz, and the ADC noise is expected to be ~1uV/rtHz, so I think this is fine.

Conclusion: I think for the ALS test, we can just use the AA board in this config without worrying too much about replacing the buffer stage opamps, even though we've ordered 100pcs of AD8622.


Addendum 7 Mar 2018 11am: As per this document, the output noise of the AA board should be <75nV/rtHz from 10 Hz-50 kHz. So maybe the AD8682 noise is a little high after all. I've gotten the LTSpice model working now, will post the comparison of modelled output noise for various combinations here shortly.

Attachment 1: AA_TF.pdf
AA_TF.pdf
Attachment 2: AA_noise.pdf
AA_noise.pdf
  13667   Wed Mar 7 12:04:14 2018 gautamUpdateElectronicsThree opamps walked onto an AA board

Here are the plots. Comments:

  1. Measurement and model agree quite well yes.
  2. Of the 3 OpAmps, the ones installed seem to be the noisiest (per model)
  3. Despite #2, I don't think it is critical to replace the buffer opamps as we only win by ~10nV/rtHz in the 300-10kHz range.
  4. I don't understand the spec given in T070146. It says the noise everywhere between 10Hz-50kHz should be <75nV/rtHz. But even the model suggests that at 10Hz, the noise is ~250nV/rtHz for any choice of buffer opamp, so that's a factor of 3 difference which seems large. Maybe I made a mistake in the model but the agreement between measurement and model for the AD8682 choice gives me confidence in the simulation. LTSpice files used are in Attachment #3. Could also be an artefact of the way I made the measurement - between an output and ground instead of differentially...

I like LTspice for such modeling - the GUI is nice to have (though I personally think that typing out a nodal file a la LISO is faster), and compared to LISO, I think that the LTspice infrastructure is a bit more versatile in terms of effects that can be modeled. We can also easily download SPICE models for OpAmps from manufacturers and simply add them to the library, rather than manually type out parameters in opamp.lib for LISO. But the version available for Mac is somewhat pared down in terms of the UI, so I had to struggle a bit to find the correct syntax for the various simulation commands. The format of the exported data is also not as amenable to python plotting as LISO output files, but i'm nitpicking...

Quote:

I've gotten the LTSpice model working now, will post the comparison of modelled output noise for various combinations here shortly.

 

Attachment 1: AA_TF.pdf
AA_TF.pdf
Attachment 2: AA_noise.pdf
AA_noise.pdf
Attachment 3: D070081_LTspiceFiles.zip
  13671   Thu Mar 8 15:23:16 2018 gautamUpdateElectronicsNew DC power ports at c1lsc

[Koji, Gautam]

Yesterday, we installed some new DIN rail connectors at the LSC rack to provide 3 new outputs each for +24V DC and -24V DC. The main motivation was to facilitate the installation and powering of the differential receiving AA board. The regulators used inside the 1U chassis actually claims a dropout voltage of 0.5V and outputs 14V nominally, so a +/-15V DC supply would've perhaps been sufficient, but we decided to leave a bit more margin, and unfortunately, there are no +/-18V DC KEPCO linear power supplies to the LSC rack. Procedure:

  1. Prepared a bunch of DIN rail connectors with tinned, daisy-chained wires in the office area. Checked continuity and isolation with DMM.
  2. Checked that the two Sorensens at the bottom of the LSC rack were powering the RF distribution box and nothing else at the LSC rack.
  3. Walked over to the little rack housing all the KEPCO DC power supplies that supply DC voltages to the LSC rack. After checking that the labelled voltage and current values were correct, we turned them off, first +/-5V, then +/-15V (2 sets), and finally +/-24V.
  4. Installed the pre-assembled DIN connectors on the side rail at the LSC rack (we had to remove the side panel for the rack to do this work).
    • We used the ports supplying power to the ALS 1U demod chassis (+/-24V DC) to tap these voltages to our newly installed connectors.
    • The interconnecting wires are rather thick gauge, and especially for the ground wire, we found it impossible to push in our tap-off wire into the "correct/hot" side of the DIN blocks. So we had to use the other side instead. I'll upload a picture shortly which will make this more clear.
    • Checked continuity and isolation with DMM.
    • Turned the KEPCOs back on in reverse order to how they were turned off.
    • Measured voltages on the hot side of the DIN blocks, confirmed that they were as expected.
  5. Prepared a 12AWG aLIGO style power cable to connect to the 1U chassis. A reel of this cabling, with yellow shielding, is located ~halfway along under the EW arm. Koji prepared the actual connector and housed it in a DSUB shell as per aLIGO wiring color scheme.
  6. Installed the power cabling to one set of our 3 newly installed +/-24V DC power supplies.
  7. Inserted fuses into the hot DIN blocks, measured voltage at connector end of our newly installed power cable. At first, I forgot to check if the fuse blocks had fuses inside, but after this was rectified, voltages were as expected yes.

The c1lsc frontend models crashed for some reason during this procedure. Now the c1sus frontend model is also behaving weirdly. It is unclear to me if/how this work would have led to these problems, but the temporal correlation (but not causation?) is undeniable.

  13802   Tue May 1 08:04:13 2018 Jon RichardsonConfigurationElectronicsPSL-Aux. Laser Phase-Locked Loop

[Jon, Gautam, Johannes]

Summary: In support of making a proof-of-concept RF measurement of the SRC Gouy phase, we've implemented a PLL of the aux. 700mW NPRO laser frequency to the PSL. The lock was demonstrated to hold for minutes time scales, at which point the slow (currently uncontrolled) thermal drift of the aux. laser appears to exceed the PZT dynamic range. New (temporary) hardware is set up on an analyzer cart beside the PSL launch table.

Next steps:

- Characterize PLL stability and noise performance (transfer functions).

- Align and mode-match aux. beam from the AS table into the interferometer.

- With the IFO locked in a signal-recycled Michelson configuration, inject broadband (swept) AM sidebands via the aux. laser AOM. Coherently measure the reflection of the driven AM from the SRC.

- Experiment with methods of creating higher-order modes (partially occluding the beam vs. misaligning into, e.g., the output Faraday isolator). The goal is identify a viable techinque that is also possible at the sites, where the squeezer laser serves as the aux. laser.

The full measurement idea is sketched in the attached PDF.

IMG_2551.jpg
PSL-Aux. beat note sensor on the PSL launch table.
IMG_2552.jpg
Feedback signal to aux. laser PZT.
IMG_2553.jpg
PLL electronics cart.

 

Attachment 1: IMG_2553.jpg
IMG_2553.jpg
Attachment 4: src_gouy_phase_v3.pdf
src_gouy_phase_v3.pdf src_gouy_phase_v3.pdf src_gouy_phase_v3.pdf src_gouy_phase_v3.pdf
  13813   Thu May 3 20:29:39 2018 gautamConfigurationElectronicsPSL-Aux. Laser Phase-Locked Loop

Some notes about the setup and work at the PSL table today, Jon can add to / correct me.

  • All equipment for the phase locking now sit on a cart that is on the west side of the MC beam tube, near ITMX chamber.
  • Cables have been routed through the space between the PSL enclosure and the optical table.
  • HEPA was turned up for this work, now it has been turned down to the nominal level of 30%.
  • Alignment into the PMC had degraded a bit - I tweaked it and now MC transmission is up at ~15600 which is a number I am used to. We still don't have a PMC transmission monitor since the slow ADC failure.
  13814   Fri May 4 13:24:56 2018 Jon RichardsonConfigurationElectronicsAUX-PSL PLL Implementation & Characterization

Attached are final details of the phase-locked loop (PLL) implementation we'll use for slaving the AUX 700 mW NPRO laser to the PSL.

The first image is a schematic of the electronics used to create the analog loop. They are curently housed on an analyzer cart beside the PSL table. If this setup is made permanent, we will move them to a location inside the PSL table enclosure.

The second image is the measured transfer function of the closed loop. It achieves approximately 20 dB of noise suppression at low frequencies, with a UGF of 50 kHz. In this configuration, locks were observed to hold for 10s of minutes.

Attachment 1: PLL_Schematic.pdf
PLL_Schematic.pdf
Attachment 2: PLL_AUX-PSL_40m.pdf
PLL_AUX-PSL_40m.pdf
  13816   Fri May 4 19:06:28 2018 ranaConfigurationElectronicsAUX-PSL PLL Implementation & Characterization

this doesn't make much sense to me; the phase to frequency conversion (mixer-demod to PZT ) should give us a 1/f loop as Johannes mentioned in the meeting. That doesn't agree with your loop shape.

How about give us some more details of the setup including photos and signal/power levels? And maybe measure the LB1005 TF by itself to find out what's wrong with the loop.

  13845   Tue May 15 20:51:27 2018 gautamConfigurationElectronicsMaking PLL setup more permanent

[jon, steve, gautam]

Some points which Jon will elaborate upon (and put photos of) in his detailed elog about this setup:

  • PLL electronics (mixer, coupler, ZFL500HLN amplifier and DC power supply for the beatnote, SR560 servo) all reside on the newly installed lower level PSL shelf.
  • Cross connect channel C1:PSL-126MOPA_126CURADJ hijacked for remote temperature control of the AUX NPRO. Note that shield of front panel BNC is ground and so even though the manual says the controller accepts +/-10V, this is not a differential input. BNC cable was routed from cross connect to PSL enclosure, MEDM slider will be setup.
  • There was an SMA cable running from the VEA to the control room which we decided to use for monitoring of the beatnote amplitude on the control room analyzer. Yesterday, Steve and I routed the end of this inside the VEA, near 1X2 originally, to inside the PSL table where it is hooked up to the (20dB) coupled amplifier output. This required some work on the cable tray, we were careful but in case there is some wonkiness in some signals, perhaps this work is to blame.

We are now in a state where the PLL can be locked remotely from the control room by tweaking the AUX laser temperature laugh. Tomorrow, Keerthana will work on getting Craig's/Johannes' Digital Frequency Counter script working here, I think we can easily implement a PLL autolocker if we have some diagostic that tells us if the PLL us locked or not.


Steve informed me that there is an acoustic hum inside the PSL enclosure which wasn't there before. Indeed, it is at ~295Hz, and is from the Bench power supply used to power the ZFL500HLN amplifier. This will have to go...

  13848   Wed May 16 18:52:50 2018 gautamConfigurationElectronicsPLL mysteries solved

[Koji, Gautam]

Summary:

As I suspected, when the SR560 is operated in 1 Hz, first order LPF mode, the (electronic) transfer function has a zero at ~5kHz (!!!).

Details:

This is what allowed the PLL to be locked with this setting with UGF of ~30kHz. On the evidence of Attachment #3, there is also some flattening of the electrical TF at low frequencies when the SR560 is driving the NPRO PZT. I'm pretty sure the flattening is not a data download error but since this issue needs further investigation anyway, I'm not reading too much into it. I fit the model with LISO but since we don't have low frequency (~1Hz) data, the fit isn't great, so I'm excluding it from the plots.

We also did some PLL loop characterization. We decided that the higher output range (10Vp bs 10Vpp for the SR560) of the LB1005 controller means it is a better option for the PLL. The lock state can also be triggered remotely. It was locked with UGF ~ 60kHz, PM ~45deg.

We also measured the actuation coefficient of the NPRO laser PZT to be 4.89 +/- 0.02 MHz/V. Quoted error is (1-sigma) from the fit of the linear part of the measured transfer function to a single pole at DC with unknown gain. I used the "clean" part of the measurement that extends to lower frequencies for the fit, as can be seen from the residuals plot. Good to know that even though the LDs are dying, the PZT is still going strong :D.

Remaining loop characterization (i.e. verification of correct scaling of in loop suppression with loop gain etc.) is left to Jon.

Measurement schemes:

  1. OLG (Attachment #1) was measured using the usual IN1/IN2 technique.
  2. PZT calibration (Attachment #2) was measured by injecting an excitation at the PLL control point.
    • The ratio of the PLL error point (Volts) to Excitation (Volts) was measured using the SR785.
    • The error point was calibrated by looking at the PLL open loop Vpp (corresponds to pi radians of phase shift).
    • Dividing the fitted gain of the phase->Frequency conversion by the error point calibration, we get the PZT actuation coefficient. 

Some other remarks:

  1. In the swept-sine mode, the SR785 measures transfer functions by taking the ratio of complex FFT values of its inputs at the drive frequency. So the phase in particular is a good indicator of whether the measurement is coherent or not.
  2. In all these measurements, the PLL gain is huge at low frequencies, and hence, the excitation is completely squished on propagating through the loop. E.g. a 10mV excitation is suppressed by a factor of ~60dB = 1000 to 10uV, and if the analyzer autoRange is set to UpOnly, it is easy to see how this is drowned at the IN1 input. This is why the measurements lose coherence below ~1 kHz.
  3. It is easy to imagine implementing an EPICS servo that offloads the DC part of the LB box control signal to the SLOW frequency input on the Lightwave controller. This would presumably allow us to extend the lock timescales. We can also easily implement a PLL autolocker.
  4. Preliminary investigation of the SR560 situation suggests that individual filter stages can only achieve a maximum stopband attenuation of 60dB relative to the passband. When we cascade two stages together, 120dB seems possible...
Attachment 1: PLLanalysis.pdf
PLLanalysis.pdf
Attachment 2: PZTcal.pdf
PZTcal.pdf
Attachment 3: SR560_funkiness.pdf
SR560_funkiness.pdf
  13858   Thu May 17 13:51:35 2018 Jon RichardsonConfigurationElectronicsDocumentation & Schematics for AUX-PSL PLL

[Jon, Gautam]

Attached is supporting documentation for the AUX-PSL PLL electronics installed in the lower PSL shelf, as referenced in #13845.

Some initial loop measurements by Gautam and Koji (#13848) compare the performance of the LB1005 vs. an SR560 as the controller, and find the LB1005 to be advantageous (a higher UGF and phase margin). I have some additional measurements which I'll post separately.

Loop Design

Pickoffs of the AUX and PSL beams are routed onto a broadband-sensitive New Focus 1811 PD. The AUX laser temperature is tuned to place the optical beat note of the two fields near 50 MHz. The RF beat note is sensed by the AC-coupled PD channel, amplified, and mixed-down with a 50 MHz RF source to obtain a DC error signal. The down-converted term is isolated via a 1.9-MHz low-pass filter in parallel with a 50 Ohm resistor and fed into a Newport LB1005 proportional-integral (PI) servo controller. Controller settings are documented in the below schematic. The resulting control signal is fed back into the fast PZT actuator input of the AUX laser.

Schematic diagram of the PLL.

 

 

 

 

 

 

 

 

 

 

Hardware Photos

Optical layout on the PSL table.

 

PLL electronics installed in the lower PSL shelf.

 

Close-up view of the phase detector electronics.

 

Slow temp. (left) and fast PZT signals into the AUX controller.

 

AUX-PSL beat note locked at 50 MHz offset, from the control room.

 

  13863   Fri May 18 14:18:03 2018 gautamConfigurationElectronicsBasic MEDM Control Screen setup

I setup a basic MEDM screen for remote control of the PLL.

The Slow control voltage slider allows the frequency of the laser to be moved around via the front panel slow control BNC.

The TTL signal slider provides 0/5V to allow triggering of the servo. Eventually this functionality will be transferred to the buttons (which do not work for now).

The screen can be accessed from the PSL dropdown menu in sitemap. We can make this better eventually, but this should suffice for initial setup.

Attachment 1: AUX_PLL_CTRL.png
AUX_PLL_CTRL.png
  13867   Fri May 18 19:59:55 2018 Jon RichardsonConfigurationElectronicsAUX-PSL PLL Characterization Measurements

Below is analysis of measurements I had taken of the AUX-PSL PLL using an SR560 as the servo controller (1 Hz single-pole low-pass, gain varied 100-500). The resulting transfer function is in good agreement with that found by Gautam and Koji (#13848). The optimal gain is found to be 200, which places the UGF at 15 kHz with a 45 deg phase margin.

For now I have reverted the PLL to use the SR560 instead of the LB1005. The issue with the LB1005 is that the TTL input for remote control only "freezes" the integrator, but does not actually reset it. This is fine if the lock is disabled in a controlled way (i.e., via the medm interface). However, if the lock is lost uncontrollably, the integrator is stuck in a garbage state that prevents re-locking. The only way to reset this integrator is to manually flip a switch on the controller box (no remote reset). Rana suggests we might be able to find a workaround using a remote-controlled relay before the controller.

Attachment 1: SR560_OL.pdf
SR560_OL.pdf
Attachment 2: SR560_CL.pdf
SR560_CL.pdf
  13869   Sun May 20 17:43:01 2018 ranaUpdateElectronicsHow to choose resistors

Article from EE Times, describing why metal foil (NOT metal film) resistors are really better than wirewound when it comes to everything except high power dissipation.

Need to do some diggin to see if we can find ~1k metal foil resistors which can handle ~1W of heat.

Steve: here it is

  13873   Mon May 21 15:34:19 2018 gautamConfigurationElectronicsChannel hijacking history

Since we've been hijacking channels like there is no tomorrow for the AUX-PLL setup, I'm documenting the channel names here. The next time c1psl requires a reboot, I'll rename these channels to something more sensible. To find the channel mapping, Koji suggested I use this. Has worked well for us so far... We've labelled all pairs of wires pulled out of the cross connects and insulation taped the stripped ends, in case we ever need to go back to the original config.

Previously unused C1PSL Channels now used for AUX PLL

Channel name AI/AO Function
C1:PSL-126MOPA_126CURADJ AO Slow temperature control
C1:PSL-FSS_RFADJ AO Servo trigger TTL
C1:PSL-126MOPA_126PWR AI PLL error signal monitor
C1:PSL-126MOPA_DMON AI PLL control signal monitor
C1:PSL-FSS_PHCON AO

To mitigate integrator railing

  13876   Tue May 22 10:14:39 2018 Jon RichardsonConfigurationElectronicsDocumentation & Schematics for AUX-PSL PLL

 

Quote:

[Jon, Gautam]

Attached is supporting documentation for the AUX-PSL PLL electronics installed in the lower PSL shelf, as referenced in #13845.

Some initial loop measurements by Gautam and Koji (#13848) compare the performance of the LB1005 vs. an SR560 as the controller, and find the LB1005 to be advantageous (a higher UGF and phase margin). I have some additional measurements which I'll post separately.

Loop Design

Pickoffs of the AUX and PSL beams are routed onto a broadband-sensitive New Focus 1811 PD. The AUX laser temperature is tuned to place the optical beat note of the two fields near 50 MHz. The RF beat note is sensed by the AC-coupled PD channel, amplified, and mixed-down with a 50 MHz RF source to obtain a DC error signal. The down-converted term is isolated via a 1.9-MHz low-pass filter in parallel with a 50 Ohm resistor and fed into a Newport LB1005 proportional-integral (PI) servo controller. Controller settings are documented in the below schematic. The resulting control signal is fed back into the fast PZT actuator input of the AUX laser.

Schematic diagram of the PLL.

 

 

 

 

 

 

 

 

 

 

Hardware Photos

Optical layout on the PSL table.

 

PLL electronics installed in the lower PSL shelf.

 

Close-up view of the phase detector electronics.

 

Slow temp. (left) and fast PZT signals into the AUX controller.

 

AUX-PSL beat note locked at 50 MHz offset, from the control room.

 

 

Attachment 1: Schematic_PLL.pdf
Schematic_PLL.pdf
  13891   Fri May 25 13:06:33 2018 Jon RichardsonConfigurationElectronicsImproved Measurements of AUX-PSL PLL

Attached are gain-variation measurements of the final, in situ AUX-to-PSL phase-locked loop (PLL).

Attachment 1: Figure of open-loop transfer function

Attachment 2: Raw network analyzer data

The figure shows the open-loop transfer function measured at several gain settings of the LB1005 PI servo controller. The shaded regions denote the 1-sigma sample variance inferred from 10 sweeps per gain setting. This analysis supercedes previous posts as it reflects the final loop architecture, which was slightly modified (now has a 90 dB low-frequency gain limit) as a workaround to make the LB1005 remotely operable. The measurements are also extended from 100 kHz to 1 MHz to resolve the PZT resonances of the AUX laser.

Conclusions:

  • Gain variation confirms response linearity.
  • At least two PZT resonances above the UGF are not far below unity (150 kHz and 500 kHz).
  • Recommend to lower the proportional gain by 3 dB. This will place the UGF at 30 kHz with 55 degrees of phase.
Attachment 1: LB1005_OL_transfer.pdf
LB1005_OL_transfer.pdf
Attachment 2: data.tar.gz
  13998   Thu Jun 21 15:32:05 2018 gautamUpdateElectronicsEX AA filter range change

[steve, gautam]

I took this opportunity of EX downtime to change the supply voltage for the AA unit (4-pin LEMO front panel) in 1X9 from +/-5V to +/-15V. Inside the AA board are INA134 and DRV135 ICs, which are rated to work at +/-18V. In the previous state, the inputs would saturate if driven with a 2.5Vpp sine wave from a DS345 func. gen. After the change, I was able to drive the full range of the DS345 (10Vpp), and there was no saturation seen. This AA chassis is only used for the OSEM signals and also some ALS signals. Shadow sensor levels and spectra are consistent before and after the change. The main motivation was to not saturate the Green PDH Reflection signal in the digital readout. The steps we took were:

  1. Confirm (by disconnecting the power cable at the back of the AA box) that the power supplied was indeed +/- 5 V.
  2. Remove DIN fuse blocks from DIN rail for the relevant blocks.
  3. Identify a +15 V, -15 V and GND spot to plug the wires in. 
  4. Effect the swap.
  5. Re-insert fuses, checked supply voltage at connector end of the cable was now +/- 15 V as expected.
  6. Re-connect power cable to AA box.
  14024   Wed Jun 27 18:12:04 2018 gautamUpdateElectronicsCoil driver dewhitening

Summary:

I've been thinking about what we need to do to the de-whitening boards for the ITMs and ETMs, in order to have low noise actuators. Noting down what I have so far, so that people can comment / point out things I've overlooked. 

Attachment #1: Block diagram schematic of the de-whitened signal path on D000183 as it currently exists. I've omitted the unity gain buffer stage at the output, though this is important for noise considerations. 

Some considerations, in rough order of priority:

  1. Why do we need de-whitening?
    • Because we want the Johnson noise of the series resistor (4.5 kohm) in the coil driver path to dominate the current noise to the coils at ~200 Hz where we want to measure the squeezing.
  2. What should the shape of this de-whitening filter be?
    • The DAC noise was measured to be ~1 uV/rtHz at 200 Hz. 
    • The Johnson noise spectral density of 4.5 kohm at 300 K is ~9 nV/rtHz
    • So we need ~60dB of attenuation at 200 Hz relative to DC. Currently, they have ~80dB of attenuation at 200 Hz.
    • However, we also need to consider the control signal multiplied by the inverse of this shape in the digital domain (required for overall flat shape). This should not saturate the DAC range.
    • Furthermore, we'd like for the shape to be such that we don't have a large transient when transitioning between high range and low noise modes. We should use the DARM control signal estimate to inform this choice.
  3. What about the electronics noise of the de-whitening filter itself?
    • This shows up at the input of the coil driver stage, and gets transmitted to the coil with unity gain. 
    • So we should aim for < 3nV/rtHz at 200 Hz, such that we are dominated by the Johnson noise of the 4.5 kohm series resistance [the excess will be 5%]. 
    • This can be realized by using the passive network which is the final stage in the de-whitening (there is a unity gain output buffer stage implemented with LT1128, which we also have to account for).   

I will experiment with a few different shapes and investigate noise and de-whitened digital signal levels based on these considerations. At the very least, I guess we should remove the x3 gain on the ETM boards, they have already been bypassed for the ITMs. 

Attachment 1: DeWhiteningSketch.pdf
DeWhiteningSketch.pdf
  14112   Sun Jul 29 00:59:54 2018 KojiUpdateElectronicsCharacterization of Transimpedance Amplifier

You have this measurement problem when the IF bandwidth is larger than the measurement frequency. I suspect the IF bandwidth is 30kHz.

  14125   Thu Aug 2 20:47:29 2018 gautamSummaryElectronicsX Green "Mystery" solved

I walked down to the X end and found that the entire AUX laser electronics rack isn't getting any power. There was no elog about this.

I couldn't find any free points in the power strip where I think all this stuff was plugged in so I'm going to hold off on resurrecting this until tomorrow when I'll work with Steve.

Quote:

The X arm green does not stay locked to the cavity - the alignment looks fine, and the green flashes are strong, but the lock does not hold. This shouldn't be directly connected to anything we did today since the Green PDH servo is entirely analog.

  14128   Fri Aug 3 14:35:56 2018 gautamSummaryElectronicsEX AUX electronics power restored

Steve and I restored the power to the EX AUX electronics rack. The power strip on the lowest shelf of the AUX rack now goes to another power strip laid out vertically along the NW corner of 1X9. The EX green locks to the arm just fine now.

  14175   Wed Aug 22 00:22:05 2018 KojiSummaryElectronicsInspection of the possible dual backplane interfaces for Acromag DAQ

[Johannes, Koji]

We went around the LSC, PSL, IOO, and SUS racks to check how many dual backplane interfaces will be required.

Euro card modules are connected to the backplane with two DIN 41612 connectors (as you know). The backplane connectors provide DC supplies and GND connections.
In addition, they are also used for the input and output connections with the fast and slow machines.

According to the past inspection by Johannes, most of the modules just use the upper DIN41612 connector (called P1). But there are some modules exhibited the possibility of the additional use of the other connector (P2).

Tuesday afternoon Johannes and I made the list of the modules with the possible dual use. And I took a time to check the modules with DCC, Jay's schematics, and the visual inspection of the actual modules.

LSC Rack

  • Common mode servo (D040180 Rev B)
    • Schematic source D040180 Rev B D1500308
    • Assesment: Both P1 and P2 are to be connected to Acromag, but there are only a few channels on P2
    • P1: 1A-32A Digital In
    • P2: 1A-3A Analog Out (D32/33/34, SLOW MON and spare?)
            9A Digital Out for D35 (Limitter)
            10A-15A Spare
            16A Digital In (Latch Enable/Disable)
            25A, 25C  Differential Analog in (Differential offset input, indicated as "BIAS") 
  • PD Interface (D990543 Rev B)
    • Schematic source D990543 RevB
    • Assesment: No connection necessary. We don't monitor/control anything of any LSC PDs from Acromag.

PSL Rack

  • Generic DAQ Interface (D990155) - This is a DAC interface.
    • Schematic source: Jay's page D990155 Rev.B All the lines between P2 and P3 are connected.
    • Assesment: Only P2 is to be connected to Acromag.
    • P1 DAC mon -> not necessary
    • P2 A1-A16, Connected to DAC in P2-P3
  • PMC Servo
    • Schematic source: LIGO DCC D980352
    • Assesment: Only P1 (1A-9A) is to be connected to Acromag. (Just one DSub is sufficient)
    • P1 1A-9A
  • Crystal Ref (D980353)
    • Schematic source: LIGO DCC D980353
    • Assesment: Only P1 (1A-4A) is to be connected to Acromag. (Just one DSub is sufficient)
    • P1 1A-4A
  • TTFSS REV A
    • Schematic source: PNot found
    • Assesment: Probably Only P1 is sufficient. We need to analyze the board to figure out the channel assignment.

IOO Rack

  • PD Interface (D990543 Rev B)
    • Schematic source D990543 RevB
    • Assesment: Only P1 connection is sufficient.
  • Generic DAQ Interface (D990155)
    • Assesment: Remove the module. We already have the same module in PSL Rack. This is redundant.
  • Common mode servo (D040180 Rev B)
    • See above
  • Pentek Generic Input Board D020432
    • Schematic source Jay's page D020432-A
    • Assesment: No connection. There is no signal on the backplane.

SUS Rack

  • SUS Dewhitening
    • Schematic source: Jay's page D000316-A
    • Assesment: No connection.
    • We can omit Mon CHs.
    • Bypass/Inputs are already connected to the fast channels.

 

  14177   Wed Aug 22 12:22:27 2018 ranaSummaryElectronicsInspection of the possible dual backplane interfaces for Acromag DAQ

I think we don't need to keep Crystal Ref: we can change this into a regular Wenzel box with no outside control or monitoring.

Quote:

 

  • Crystal Ref (D980353)
    • Schematic source: LIGO DCC D980353
    • Assesment: Only P1 (1A-4A) is to be connected to Acromag. (Just one DSub is sufficient)
    • P1 1A-4A

 

  14273   Tue Nov 6 10:03:02 2018 SteveUpdateElectronicsContec board found

The Contec test board with Dsub37Fs was on the top shelf of E7

Attachment 1: DSC01836.JPG
DSC01836.JPG
  14414   Wed Jan 23 18:11:56 2019 gautamUpdateElectronicsEthernet Power Strip IP conflict

For the last week, I noticed that I was unable to turn the EY chamber illuminator on using the remote python scripts. This was turning out to be really annoying, having to turn the light on/off manually. Today, I looked into the problem and found that there is a conflict in the IP addresses of the EY Ethernet Strip (which Chas assigned a static IP but did not include detailed procedures forno) and the vertex area laptop, paola. The failure of the python control of the power strip coincided exactly with when Chub and I turned on paola for working at the IY chamber - but how was I supposed to know these events are correlated? I tried shutting down paola , power cycling the Ethernet power strip, and restarting the bind9 services on chiara, but remote control of the ethernet power strip remains elusive. I suspect reconfiguring the static IP for the Ethernet switch will require some serial port enabled device...

  14417   Thu Jan 24 22:55:50 2019 gautamUpdateElectronicsSatellite box S/N 102 investigation

I had taken Satellite box S/N 102, from the SRM suspension, down to the Y-end as part of debugging. However, at some point, I stopped getting readbacks from the shadow sensor PDs, even with the Sat. Box tester hooked up (so as to rule out anything funky with the actual OSEMs). Today evening, I did a more systematic investigation. Schematic with component references is here.

  1. Used mini-grabbers and a bench power supply to connect +/-24V to C57 and C58.
  2. Checked that all ICs were getting +/- 15 V to the supply pins.
  3. Debugged individual channels, checking voltages at various nodes
    • Found that the "PD K" bias voltage was anomalosly low.
    • Found that the inverting input of U3C wasn't ground.
    • The above findings are summarized in Attachment #2.
    • This suggested something was wrong with the Quad OpAmp LT1125 IC, so I elected to switch it out.
    • During the desoldering process, the pads for the "NC" pins came off (Attachment #1) - this has happened to me before on these old boards. I don't think I applied excess heat during the desoldering (I used 650F).
    • Replaced the IC, and measured the expected 10V at the "PD K" node.
  4. I then connected the tester box and verified all the shadow sensor channels (LED + PD) work as expected, using the front panel J3 and the "octopus cable".
  5. It remains to verify that the coil driver signals get correctly routed through the Satellite box before giving this box a pass certification.

The question remains as to what caused this failure mode - I can't think of why that particular IC was damaged during the Satellite box swapping process - is this indicative of some problem elsewhere in the ETMY OSEM/coil driver electronics chain?

Attachment 1: IMG_7294.JPG
IMG_7294.JPG
Attachment 2: D961289-B2.pdf
D961289-B2.pdf
  14418   Fri Jan 25 12:49:53 2019 gautamUpdateElectronicsEthernet Power Strip IP conflict resolved

To avoid the annoying excercise of having to manually toggle the illuminators, I solved the IP conflict. Made a wiki page for the ethernet power strips since the documentation was woeful (the way the power strips are mounted in the racks, you can't even see the manufacturer/model/make). All chamber illuminators can now be turned on/off by the MEDM scripts yes. Note that there is a web interface available too, which can be useful in case of some python socket issues. The main lesson is: avoid using the "reset" button on the power strips, it destroys the static IP config.


Unrelated to this work: The EY laptop, asia, won't boot up anymore, with a "Fan Error" message being the red flag. I've temporarily recommissioned the vacuum rack laptop, belladonna, to be the EY machine for this vent. Can we get 3 netbooks that actually work and don't need to be tethered to a power strip for the VEA?

  14421   Tue Jan 29 17:19:16 2019 gautamUpdateElectronicsSatellite box S/N 105 repaired

[chub, koji, gautam]

Attachment #1 shows the signal routing near the Satellite box. Somehow, the female 64 pin IDC connector that brings the signals from the coil driver board wasn't mating well with the mail connector on the Satellite box front panel. This is a connector specific problem - plugging the female end into one of the male connectors inside the Satellite box yielded signal continuity. The problem was resolved by re-making both connections -by driving the EPICS bias slider through its full range, we were able to see the full voltage swing at the DB connectors going to the flange

This kind of flakiness could be all around the lab, and could be responsible for many of the suspension "mysteries". To re-iterate, the problem seems to be the way the female sockets of the connector mates with the male pins - while the actual crimping points may look secure, there may not be signal continuity.

Now that this problem is resolved, tomorrow we will recover the cavity alignment and possibly start a pumpdown.


Unrelated to this work - the spare satellite box (S/N #100), which had a note on it that said "low voltages", was tested. The "low voltages" referred to the OSEM shadow sensor voltages being low when the LED was completely unobscured. The reason was that the mod to increase the drive current to 25 mA had not yet been implemented on this unit. I added the appropriate 806 ohm resistors, and verified that the voltages were correct, so now we have a working spare. It is stored in the "photodiode" cabinet along the east arm, together with the tester boxes. 

Attachment 1: IMG_7301.JPG
IMG_7301.JPG
  14555   Fri Apr 19 12:06:31 2019 awadeBureaucracyElectronicsBorrowed Busby Box May 19th 2019

I've borrowed the Busby Box for a day or so.  Location: QIL lab at Bridge West.

Edit  Sat Apr 20 21:16:46 2019 (awade): returned.

  14584   Mon Apr 29 16:34:27 2019 gautamUpdateElectronicsITMX/IMTY mis-labelling fixed at 1X4 and 1X5

After the X and Y arm naming conventions were changed, the labelling of the electronics in the eurocrates was not changed 😞 😔 😢 . This meant that when we hooked up the new Acromag crate, all the slow ITMX channels were in fact connected to the physical ITMY optic. I ♦️fixed♦️ the labelling now - Attachments #1 and #2 show the coil driver boards and SUS PD whitening boards correctly labelled. Our electronics racks are in desperate need of new photographs.

The "Y" arm runs in the EW direction, while the "X" arm runs in the NW direction as of April 29 2018.

ITMX was freed. ITMY is being worked on is also free..

Attachment 1: IMG_7400.JPG
IMG_7400.JPG
Attachment 2: IMG_7401.JPG
IMG_7401.JPG
  14669   Thu Jun 13 15:08:31 2019 MilindUpdateElectronicsVCO pickup by Rich

Rich dropped by at around 3:00 PM today and picked up the VCO in Attachment #1 and left the note in Attachment #2 on Gautam's desk with the promise of bringing it back soon.

Attachment 1: WhatsApp_Image_2019-06-13_at_15.06.57.jpeg
WhatsApp_Image_2019-06-13_at_15.06.57.jpeg
Attachment 2: WhatsApp_Image_2019-06-13_at_15.06.57(1).jpeg
WhatsApp_Image_2019-06-13_at_15.06.57(1).jpeg
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