I took the spectrum of an EM172 connected to my amplifier inside and outside a large box filled with foam layers:

I also made a diagram with my plan for the microphone amplifier boxes. This is a bottom view:

The dimensions I got from this box: http://www.digikey.com/product-detail/en/bud-industries/CU-4472/377-1476-ND/696705

This seemed like the size I was looking for and it has a mounting flange that could make suspending it easier. Let me know if you have any suggestions.

I'll be doing a Huddle test next week to get a better idea of the noise floor and well as starting construction of the circuits to go inside the boxes and the boxes themselves.
 

I set up 3 of my circuits in the interferometer near MC2 to do a huddle test. I have the signals from my microphones going into C1:PEM-MIC_1_IN1, C1:PEM-MIC_2_IN1, and C1:PEM-MIC_3_IN1. These are channels C17-C19. Here are some pictures of my setup:

I'll likely be collecting data from this for a couple of hours. Please don't touch it for now- it should be gone soon. There are some wires running along the floor near MC2 as well.

In order to help Praful do his huddle test, I have temporarily arranged for the outputs of the 3 channels he wants to monitor to be acquired as DQ channels at 2048 Hz by editing the C1PEM model. No prior DQ channels were set up for the microphones. Data collected overnight should be sufficient for Praful's analysis, so we can remove these DQ channels from C1PEM before committing the updated model to the svn. There is in fact a filter that is enabled for these microphone channels that claims to convert the amplified microphone output to Pascals, but it is just a gain of 0.0005. 

In the long term, once we install microphones around the IFO, we can update C1PEM to reflect the naming conventions for the microphones as is appropriate.

The results of my first huddle test were not so good- one of the signals did not match the other two very well- so I changed the setup so that the mics would be better oriented to receive the same signal. Pictures of the new setup are attached.

I also noticed some problems with one of my microphones so I soldered a new mic to bnc and switched it out. Just judging from Dataviewer, the signals seem to be more similar now. I'll be taking data for another few hours to confirm.

I used the Wiener filtering method described by Ignacio and Jessica (https://dcc.ligo.org/DocDB/0119/T1500195/002/SURF_Final.pdf and https://dcc.ligo.org/public/0119/T1500194/001/Final_Report.pdf) and got the following results:

mic1_wiener.pdf

mic2_wiener.pdf

mic3_wiener.pdf

The channel readout has a gain of 0.0005 and the ADC is 16-bit and operates are 20V. The channel also reads the data out in Pa. I therefore had to multiply the timeseries by 1/0.0005=2000 to get it in units of counts and then by (20 Volts)/(2^16 counts) to get back to the original signal in volts. The PSDs were generated after doing this calibration. I also squared, integrated, and square rooted the PSDs to get an RMS voltage for each microphone as a sanity check:

Mic 1: 0.00036 V

Mic 2: 0.00023 V

Mic 3: 0.00028 V

These values seem reasonable given that the timeseries look like this:

timeseries_elog.pdf

For the past week, I've been trying to make a soldered amplifier circuit to use in a prototype box, However, I've been running into this same issue. The circuit, pictured below, works fine on a solderless breadboard.

simple_amp.png

When I amplify a sine wave, I get a clean looking result at the output on the solderless breadboard:

However, on my soldered circuit, if I turn up the negative voltage supply from the power supply past about -12.5V (the target is -15V), I get a strange signal that Gautam suggested looks like some kind of discharging.

At -12.3 V (soldered breadboard):

At -15.0 V (soldered breadboard):

The signal is much noisier. Zooming in on this second signal, this pattern appears:

This pattern is also showing up even when there is no input from the function generator and the circuit is just given a voltage supply of +/- 15V:

I have tried switching out both the positive and negative voltage regulators, the opamp, and remaking and resoldering the entire circuit but I'm still getting the same signal, which is absent from the solderless circuit. This output was produced with a function generator, so I have also ruled out the microphone as a source of this extra noise. The voltage dependence of this problem made me think it was the voltage regulator, but I've switched out the voltage regulator multiple times and it's still showing up. I'm not sure why this signal appears only as the negative voltage supply is increased- there is no problem with increasing the positive input voltage. Please let me know if you have any ideas as to what component or issue could be causing this.

I remade another soldered circuit, adding extra 100uF electrolytic bypass capacitors at the input and output of the voltage regulator and ensuring that every grounded component now has its own path to ground rather than going through other elements. This circuit now seems to be working just like the solderless circuit. Attached is the transfer function of the soldered circuit, which matches with the result from the solderless circuit.

soldered_transfer_function.png

solderless_transfer_function.png

Here are both on the same figure- they are about overlapping but are slightly different if you zoom in enough.

both_transfer.png

I have also attached a new version of the circuit schematic to reflect the changes and to make the physical layout more clear.

simple_ampv2.pdf

My next step for these last few days this summer will be designing a PCB using Altium. I've emailed Varun about how to use Altium on the iMac but he hasn't responded. If anyone else knows how to use the software, please let me know.

What I suggested was:
- For most cases, power decoupling capacitors for the regulators should be ~100nF "high-K ceramic capacitors" + 47uF~100uF "electrolytic capacitors".
- For opamps, 100nF high-K ceramic should be fine, but you should consult with datasheets.
- Usually, you don't need to use tantalum capacitors for this purpose unless specified.
- Don't use film capacitors for power decoupling.

79XXs are less stable compared to 78XXs, and tend to become unstable depending on the load capacitance.
One should consult with the datasheet of each chip in order to know the proper capacitors values.
But also, you may need to tweak the capacitor value when necessary. Above recipe works most of the case.

I added an EM172 to my soldered circuit and it seems to be working so far. I have taken a spectra using the EM172 in ambient noise in the control room as well as in white noise from Audacity. My computer's speakers are not very good so the white noise results aren't great but this was mainly to confirm that the microphone is actually working.

white_v_ambient.pdf

Do these look good for the ceramic capacitors? We're running low.

http://www.mouser.com/ProductDetail/Vishay-BC-Components/K104K15X7RF53L2/?qs=sGAEpiMZZMuMW9TJLBQkXmrXPxxCV7CRo6C15yUYAos%3d

Yes

Interesting articles how they should only be used for power decoupling and not in the signal path.

http://www.edn.com/design/analog/4416466/Signal-distortion-from-high-K-ceramic-capacitors

http://www.edn.com/design/analog/4426318/More-about-understanding-the-distortion-mechanism-of-high-K-MLCCs

Gautam helped me drill holes in a metal box and I set up my circuit inside. Everything seems to be working so far. Tomorrow I'll be suspending the box near the PSL and setting up a data channel. Attached are some pictures of the box- sorry some of the angles turned out weird.

My box has been suspended in the PSL using surgical tubing, and it has been connected to C1:PEM-MIC_1 (C17) with a BNC. I made a braided power cable as well but it turned out to be slightly too short... Once this is fixed, everything should be ready and we can see if it's working correctly. I also set up a new tab on the summary pages for this channel:

https://ldas-jobs.ligo.caltech.edu/~praful.vasireddy/1154941217-1154942117/pem/acoustic/

This data is back from when I had my solderless breadboard running near MC2. I'll add this tab to the real pages once the box is working (which could be a while since I'm gone for a month). Let me know if you see any issues with either the tab or the box/cables.

1. add photo of installation
2. no more secret personal pages! put channels into the actual pages that we look at
3. make it ASD instead of PSD, same as the other channels
4. add specgram (whitened and not)

I'll add a picture of the installation when I get back to campus and finish hooking up the power cable. I haven't added this channel to the actual pages yet because there's not any data right now- the box is still unpowered because my braided power cable wasn't long enough. I just changed the format of the spectrum to ASD and added spectrograms. Here's how the tab looks now: https://ldas-jobs.ligo.caltech.edu/~praful.vasireddy/1155014117-1155015017/pem/acoustic/

Let me know if there's anything else to change.

In November of 2010, Valera Frolov (LLO), investigated our satellite amplifiers and made some recommendations about how to increase the SNR.

In light of the recent issues, we ought to fix up one of the spares into this state and swap it in for the ITMY's funky box.

The sat amp schematic is (D961289). It has several versions. Our spare is labeled as version D (not a choice on the DCC page).

1. U13-17 seem superfluous. Why would we need a high current buffer to drive the slow EPICS ADCs ?
2. The Radd resistors indicated on the B2 schematic have not been added to this board. What would be the purpose of adding them anyway?
3. The transimpedance resistors are, in fact, 29.4k as indicated on the B1 schematic.
4. The LT1125: V_n = 3 nV w/ f_corner = 5 Hz. I_n = 0.4 pA w/ f_corner = 100 Hz. So at 1 Hz the current noise is limiting at ~120 nV/rHz or 650 nV/rHz using the 161k that Valera recommends.
5. Even in that case the ADC noise is higher than the opamp noise.
6. We should be using metal film resistors instead of the thick film junk that's installed now.

Edit (Sep 6): The purpose of the Radd resistors is to lower the resistance and thus up the current through the LED. The equivalent load becomes 287 Ohms. Presumably, this in series with the LED is what gives the 25 mA stated on the schematic. This implies the LED has an effective resistance of 100 Ohms at this operating point. Why 3 resistors? To distribute the heat load. The 1206 SMD resistors are usually rated for 1/4 W. Better to replace with 287 Ohm metal film resistors rated for 1 W, if Steve can find them online.

The attached PDF shows the output noise of the satellite amp. This was calculated using 'osempd.fil' in the 40m/LISO GitLab repo.

The mean voltage output is ~1 Vdc, which corresponds to a current with a shot noise level of 100 nV/rHz on this plot. So the opamp current noise dominates below 1 Hz as long as the OSEM LED output is indeed quantum limited down to 0.1 Hz. Sounds highly implausible.

To convert into meters, we divide by the OSEM conversion factor of ~1.6 V/mm, so the shot noise equivalent would be ~1e-10 m/rHz above 1 Hz.

After adding the sat amp to the 40m DCC tree (D1600348), I notice that not only is the PD readout not built for low noise, neither is the LED drive.  The noise should be dominated by the voltage noise of the LT1031 voltage reference. This has a noise of ~500 nV/rHz at 1 Hz. That corresponds to an equivalent current noise through the LED of 25 mA * (500e-9 / 10) ~ 1 nA/rHz. Or ~45 nV/rHz at the sat amp output. This would be OK as long as everything behaves ideally. BUT, we have thick film (i.e. black surface mount) resistors on the LED drive so we'll have to measure it to make sure.

Also, why is the OSEM LED included in the feedback loop of the driver? It means disconnecting the cable from the sat amp makes the driver go unstable probably. I think one concept is that including the device in the feedback loop makes it so that any EMI picked up in the cabling, etc. gets cancelled out by the opamp. But this then requires that we test each driver to make sure it doesn't oscillate when driving the long cable.  

If we have some data with one of the optics clamped and the open light hitting the PD, or with the OSEMs removed and sitting on the table, that would be useful for evaluating the end-to-end noise of the OSEM circuit. It seems like we probably have that due to the vent work, so please post the times here if you have them.

The ETMX OSEMs have been attached to its Satellite box and plugged in for the last 10 days or so, with the PD exposed to the unobstructed LED. I pulled the spectrum of one of the sensors (mean detrended, I assume this takes care of removing the DC value?). The DQed channels claim to record um (the raw ADC counts are multiplied by a conversion factor of 0.36). For comparison, re-converted the y-axis for the measured curve to counts, and multiplied the total noise curve from the LISO simulation by a factor of 3267.8cts/V (2^16cts/20V) so the Y axis is noise in units of counts/rtHz. At 1Hz, there is more than an order of magnitude difference between the simulation and the measurement which makes me suspect my y-axis conversion, but I think I've done this correctly. Can such a large discrepancy be solely due to thick film resistors?

In order to figure out the difference betweent simulated result and measurement, I tried to measuren the electronic noise by following ways as show in attachment 1

1.measure from the satellite box by SR785 at ETMY ,calibrate to counts by divide by 3267.8. while at that conditin, the set up is in suspension.

2. measure after ADC by diagnostics test tools, with set up on table in history and on uspension currently.

3. use the caculated butterfly channel.

the results are shown in attachmemt 2. The overall nosie level are still much higher than simulation.

REF33 was removed for taking picture of the bare C30362 InGaAs photodiode per Rana's request. All other rf photodiodes have their glass cover on.

Note: it is back to it's place but this pd will need alignment!

The small steering mirror was completly lose before it was removed.

I made an Altium schematic for the microphone amplifier circuit for fabrication.

mic_schematicv2.pdf

I got back to trying to engage the coil driver whitening today, the idea being to try and lock the DRMI in a lower noise configuration - from the last time we had the DRMI locked, it was determined that A2L coupling from the OL loops and coil driver noise were dominant from ~10-200Hz. All of this work was done on the Y-arm, while the X-arm CDS situation is being resolved.

To re-cap, every time I tried to do this in the last month or so, the optic would get kicked around. I suspected that the main cause was the insufficient low-pass filtering on the Oplev loops, which was causing the DAC rms to rail when the whitening was turned on. 

I had tried some loop-tweaking by hand of the OL loops without much success last week - today I had a little more success. The existing OL loops are comprised of the following:

• Differentiator at low frequencies (zero at DC, 2 poles at 300Hz)
• Resonant gain peaked around 0.6 Hz with a Q of ______ (to be filled in)
• BR notches 
• A 2nd order elliptic low pass with 2dB passband ripple and 20dB stopband attenutation

THe elliptic low pass was too shallow. For a first pass at loop shaping today, I checked if the resonant gain filter had any effect on the transmitted power RMS profile - turns out it had negligible effect. So I disabled this filter, replaced the elliptic low pass with a 5th order ELP with 2dB passband ripple and 80dB stopband attenuation. I also adjusted the overall loop gain to have an upper UGF for the OL loops around 2Hz. Looking at the spectrum of one coil output in this configuration (ITMY UL), I determined that the DAC rms was no longer in danger of railing.

However, I was still unable to smoothly engage the de-whitening. The optic again kept getting kicked around each time I tried. So I tried engaging the de-whitening on the ITM with just the local damping loop on, but with the arm locked. This transition was successful, but not smooth. Looking at the transmon spot on the camera, every time I engage the whitening, the spot gets a sizeable kick (I will post a video shortly).  In my ~10 trials this afternoon, the arm is able to stay locked when turning the whitening on, but always loses lock when turning the whitening off. 

The issue here is certainly not the DAC rms railing. I had a brief discussion with Gabriele just now about this, and he suggested checking for some electronic voltage offset between the two paths (de-whitening engaged and bypassed). I also wonder if this has something to do with some latency between the actual analog switching of paths (done by a slow machine) and the fast computation by the real time model? To be investigated.

GV 170628 11pm: I guess this isn't a viable explanation as the de-whitening switching is handled by the one of the BIO cards which is also handled by the fast FEs, so there isn't any question of latency.

With the Oplev loops disengaged, the initial kick given to the optic when engaging the whitening settles down in about a second. Once the ITM was stable again, I was able to turn on both Oplev loops without any problems. I did not investigate the new Oplev loop shape in detail, but compared to the original loop shape, there wasn't a significant difference in the TRY spectrum in this configuration (plot to follow). This remains to be done in a systematic manner. 

Plots to support all of this to follow later in the evening.

Attachment #1: Video of ETMY transmission CCD while engaging whitening. I confirmed that this "glitch" happens while engaging the whitening on the UL channel. This is reminiscent of the Satellite Box glitches seen recently. In that case, the problem was resolved by replacing the high-current buffer in the offending channel. Perhaps something similar is the problem here?

Attachment #2: Summary of the ITMY UL coil output spectra under various conditions.

Spare ILIGO electronics temporarly stored in the east arm. We need cabinet space.

Summary:

The analog de-whitening filters for MC2 are different from those on the other optics (i.e. ITMs and ETMs). They have one complex pole pair @7Hz, Q~sqrt(2), one complex zero pair @50Hz, Q~sqrt(2), one real pole at 2.5kHz, and one real zero @250Hz (with a DC gain of 10dB).

Details:

I took the opportunity last night to measure all 4 de-whitening channel TFs. Measurements and overlaid LISO fits are seen in Attachment #1. 

The motivation behind this investigation was that last week, I was unable to lock the IMC to one of the arms. In the past, this has been done simply by routing the control signal of the appropriate arm filter bank (e.g. C1:LSC-YARM_OUT) to MC2 instead of ETMY via the LSC output matrix (if the matrix element to ETMY is 1, the matrix element to MC2 is -1).

Looking at the coil output filter banks on the MC2 suspension MEDM screen (see Attachment #2), the positions of filters in the filter banks is different from that on the other optics. In general, the BIO outputs of the DAC are wired such that disengaging FM9 on the MEDM screen engages the analog de-whitening path. FM10 then has the inverse of the de-whitening filter, such that the overall TF from DAC to optic is unity. But on MC2, these filters occupy FM7 and FM8, and FM9 was originally a 28Hz Elliptic Low-pass filter.

So presumably, I was unable to lock the IMC to an arm because for either configuration of FM9 (ON or OFF), the signal to the optic was being aggressively low-passed. To test this hypothesis, I simply copied the 28Hz elliptic to FM6, put a gain of 1 on FM9, left it engaged (so that the analog path TF is just flat with gain x3), and tried locking the IMC to the arm again - I was successful. See Attachment #3 for comparison of the control signal spectra of the X-arm control signal, with the IMC locked to the Y-arm cavity.

In this test, I also confirmed that toggling FM9 in the coil output filter banks actually switches the analog path on the de-whitening boards.

Since I now have the measurements for individual channels, I am going to re-configure the filter arrangement on MC2 to mirror that on the other optics. 

Unrelated to this work: the de-whitening boards used for MC1 and MC3 are D000316, as opposed to D000183 used for all other SOS optics. From the D000316 schematic, it looks like the signals from the AI board are routed to this board via the backplane. I will try squishing this backplane connector in the hope it helps with the glitching MC1 suspension.

GV Aug 13 11:45pm - I've made a DCC page for the MC2 dewhitening board. For now, it has the data from this measurement, but if/when we modify the filter shape, we can keep track of it on this page (for MC2 - for the other suspensions, there are other pages). 

This kind of data fitting and analysis is really useful. We should figure out a way to archive it. Perhaps the data files and fitting stuff can be put into GIT in some smart way? The fit results can be added to the 40m MC electronics DCC tree. Then the links can be added to this elog.

Gautam and Steve,

All 3 show the same noise level ~80 nV / rt Hz at 1 kHz as shown. Batteries ordered to be replaced in the top 2

We'll do more measurement to see how can we get to 4 nV / rt Hz  specification level.

these are not the SR785 settings that you're looking for

To get low noise measurements on the SR785, you have to have the input range set to -50 dB, not +20 dB. Its not within the powers of commercial electronics ADCs to give you a 10 nV noise floor with +10 V input signals. The SR560 has an input referred noise of 5 nV/rHz, so the output noise should be 5e-9 x 500 = 2.5 uV/rHz. Your picture shows it giving 1 uV RMS, so you also need to use the PSD units.

I characterized the black Ithaca 1201 pre-amp that we had sitting in the racks. It works fine and the input referred noise is < 10 nV/rHz. I also checked that the filter selection switches on the front panel did what they claim and that the gain knob gives us the correct gain.

For comparison I have also included the G=100, 1000 input referred noise of one of the best SR560 that we have (s/n 02763) in the lab. Above a few Hz, the SR560 is better, but for low frequency measurements it seems that the 1201 is our friend.

As with the SR560, you don't actually get low noise performance for G < 100, due to some fixed output noise level.

Steve:  sn48332 of Ithaca 1201

I have ordered some LSK389A (in both the SOIC-8 and TO-71 packages) to replace the SR560's default front end FET pair (NPD5565).

I'm going to rework s# 00619 once these new FETs come in. Also ordered 100 of the SOIC-8 to DIP-8 adapter boards from Digikey.

This plot shows the current performance compared to the Rai Low Noise box. I expect the FETs should let us get to ~1.5 nV/rHz with the SR560.

I replaced the NPD5565 with a LSK389 (SOIC-8 with DIP adapter). There was a noise reduction of ~30%, but not nearly as much as I expected. I wonder if I have to change the DC bias current on these to get the low noise operation?

https://photos.app.goo.gl/hsMwsif7NLscsgpx1

We use D990694 in various places. Today, Rana alerted me to an important consideration to be kept in mind when we use this board, which I found quite interesting. I still don't understand the problem at the BJT level, but I think one can appreciate the problem without going to the transistor design of the LT1125. I'm attaching an annotated schematic of the whitening section in question. If the following assumptions are valid, then I think my picture is valid.

1. The switch used to bypass the various whitening gain stages, namely the ADG333ABR, has infinite impedance in the "OFF" state, such that when the 24dB gain stage is bypassed, U28A (or in general one of the 4 quad op-amps) is forced to drive it's output voltage across 1.0665 kohms of resistance.
2. The individual LT1125 Op Amps can drive a maximum of 30mA of current.

Then, as one can see in the attached schematic, when we set the gain of any input to <24dB, we must ensure that the input voltage is less than approximately 2V. Otherwise, by asking too much of the first stage op-amp in the quad IC LT1125, we may be messign around with all the 4 op amps in the quad! Even the 0dB setting is not immune to this problem, as it uses one of the 4 op amps.

I don't think the usual rules of calculating the gain of a non-inverting amplifier (G = 1 + Rf/Ri) remain valid even when the op-amp is forced to drive more output current than it can, and I don't have a way to quantify the possible interference between the 4 op amps in the quad - but does this seem like a valid conclusion? If so, we must check signal levels of various LSC signals. AS55 signals currently have the 0dB gain setting - I had turned this down from 6dB some months ago, because it seemed like the ADC was saturating at the 6dB gain setting, which suggests that the input voltage is ceratinly > 2V, and AS55_Q is what is used for MICH control in the DRMI. All of my noise budgeting work over the last few months used this setting, I wonder if they are all invalid 

Now that I think about this a bit more - this problem shouldn't be significant for the usual LSC degrees of freedom when in lock, as the huge DC gain of the loop should squish large DC values of the error signals, and so there shouldn't be any danger of overloading the LT1125. But I don't know if we are being hurt by this effect when flashing through resonances, when the PDH horn-to-horn voltage can be quite high (which is in principle a good thing?). I don't know if there is any "hysterisis" effect where the overloaded quad IC has some relaxation time before it returns to normal operation, and if we are being limited in our ability to catch lock because if this effect. 

The concerns remain valid for th ALS demodulated error signals though, for which the signals will remain large throughout.

this is the note from Hartmut Grote on this topic from 2004

After discussing with Koji, we looked at the aLIGO incarnation of this board. Interestingly, it too has a similar topology of 4 switchable gain stages with gains of 24, 12, 6 and 3dB. The main differences are that they use single Op27 ICs instead of the quad LT1125s, and also, they use a different combination of feedback resistors to realize the various gains. 

We considered upping the feedback resistance (R15, R143) on the 24dB gain stage of our boards from (1k, 66.5ohms) to (3k, 200ohms) as on the aLIGO boards - but this doesn't really help? Because KCL demands that the same current flow in R15 and R143, and so the output Vsat of the op amp and its max current driving capabilities in combination determine if the inverting input can follow the non inverting input?

As Hartmut points out in his note, he was able to access the full range of ADC voltages when the gain was set to 3dB, despite the fact that the LT1125 was still getting internally saturated. Operating with minimum 24dB whitening gain doesn't really solve the problem either because the problem just gets shifted to the next gain stage in the chain, and we still have saturation. I also don't have a feeling for how much differential voltage these LT1125s can sustain before they are damaged - I guess the planned THD check will reveal if they are okay or not.

It seems to me like the only way to truly fix this problem of one stage saturating and screwing up the others is to use single Op27s (or equivalent) in place of the quad LT1125s. The aLIGO design also has a series resistance to the non-inverting input - this can help prevent current overdraw from the previous stage (due to a lowered input impedance of the OpAmp - but I wonder how low this can go?).

I have acquired 5 pieces of the Teledyne AP1053 from Koji - these are now at the 40m. I will determine an appropriate location for storage of these and update. We are also looking to acquire 5 more of these. The combination of high power output (26dBm), low gain (10dB), and low noise figure (1.5dB) are quite uncommon in an amplifier and so these should be used only when such properties are required simultaneously.

*Steve informs me that these amps have been stored in the RF cabinet E6 along the east arm.

Steve's note: Teledyne rf amp product selection guide

                   Teledyne rf low noise amp guide

I plan to do some characterization of this problem. The plan is to use THD as a metric for whether we are having hidden saturations. Pg 9 of the LT1125 datasheet tells us what fraction of THD to expect. I will use one of the several unused DAC channels available at the LSC rack to drive a 100Hz sine wave into one of the inputs of the whitening chassis, and measure the THD up to a reasonable harmonic number (will probably be set by the ADC noise) for (i) various whitening gain settings and (ii) various input signal amplitudes.

The motivation is to attempt to quantify the problem better:

1. How bad is it to have one or more of the OpAmps in the quad IC either saturated to its voltage rails, or max output current?
2. Can we reproduce Hartmut's observations?
3. Are the OpAmps already irreversibly damaged because of extended abuse?

Then we can decide what, if anything, to do about this issue.

The main motivation for this work is that I want +15VDC power available on the PSL table to hookup the Teledyne box that Koji made a week ago and do some noise measurements on my revised IR ALS signal chain. But I think this is a good opportunity to effect a number of changes I've been wanting to do for a while.

Tomorrow, Steve and I will do the following:

1. Fix the AOM driver power cabling that I broke.
2. Make the AOM +24VDC power supply independent - right now it is shared between the AOM driver and the two ZHL-3-A amplifiers.
3. Tap an independent +24VDC power supply from 1X1 for the ZHL-3A amplifiers (I guess one power supply and fuse is sufficient for both amplifiers since they are in the same box).
4. Tap an independent +15VDC power supply for the Teledyne box.
5. Tap an independent +15VDC power supply for the little fan on the back of the PSL controller, that is currently powered by a bench supply (+12VDC, but it's just a fan, so +15VDC or +10VDC will do just fine, and these are the Sorensen levels we have).
6. Tap an independent +/-24VDC power supply for the FSS summing box. Right now it is being powered by a bench supply under the PSL table. The indicated supply voltage on the box is +/-18V. But according to the schematic, this +/-18V get regulated down to +/- 15V, so we may as well use +/-24V which is available from the Sorensens in 1X1 (there is no +/-18VDC Sorensen there). The datasheets for the 7815 and 7915 ICs suggest that this will be just fine.
7. Where possible, make at least 1 spare outlet for each supply voltage available at 1X1, such that in future, tapping extra supply points won't be such a huge pain.

So in summary, we will need, at 1X1, (at least, including 1 spare for future work):

• New +24VDC connections ------ 3x
• New -24VDC connections ------- 2x
• New +15VDC connections ------ 3x

[steve, gautam]

We completed this work today. Need to clean up a little (i.e. coil excess cable lengths, remove unused cables etc), which we will do tomorrow. All connections have been made at the DIN rail end, but the fuses have not been inserted yet, so there is no voltage reaching the PSL table on any of the newly laid out cables. We also need to establish two +15VDC connections at the DIN rail side. I may establish this later in the evening, as the main point of this work was to get the Teledyne signal path operational. Setting up these DIN connectors is actually a huge pain, we tried to setup a few extra ports for the voltages we used today so that in future, life is easier for whoever wants to pipe DC power to the PSL table. The rule is, however, to re-establish the same number of open ports for each voltage as was available when you started.

For the ZHL-3A, Teledyne, and AOM driver cables, we used 18AWG, 2 conductor, twisted wire, while for the PSL fan we used 20AWG. For the FSS box, we decided to use the 3 conductor 24AWG twisted wire. I believe that these wire gauge choices are appropriate given the expected current in each of these paths.

Pictures + further details tomorrow.

gautam @ 1030pm: there was some mistake with the +15V wiring we did in the evening (the PSL fan and Teledyne cables were plugged into the wrong DIN terminal blocks). I fixed this, and also routed +15VDC to the newly installed set of terminal blocks for this purpose (since we had run out of +15VDC ports at 1X1). After checking voltages at both 1X1 and on the PSL table, I hooked up

1. FSS Summing box
2. Teledyne amplifier
3. ZHL-3A amplifiers

to their newly laid out power supplies. IMC locks so looks like the FSS box is doing fine . So we can recover one bench power supply from under the PSL table on the east side. I didn't hook up the AOM driver just now because of some accessibility issues, and I'd also like to do an ALS beat spectrum measurement if possible.

I made a voltage divider using a 20.47kohm and 1.07kohm (both values measured with a DMM). The whole thing is packaged inside a Pomona box I found lying around on the Electronics bench. I have hooked it up to the ALSY_I channel and will leave it so overnight. The INMON of this channel isn't DQed, but for this test, the 16Hz EPICS data will suffice. I've locked the EX laser to the arm, enabled slow temperature servo to allow overnight lock (hopefully) and disabled LSC mode (as locking the arm to the MC tends to break the green lock)

To convert the INMON counts to RF power, I will use (based on my earlier calibration of this monitor channel, see DCC document for the demod chassis).

1AM update: Attachment #1 shows that the RF amplitude has been relatively stable (less than 10% of nominal value variation) over the course of the last hour or so. Even though there is some low frequency drift over timescales of ~20mins, no evidence of the wild ~20dB amplitude changes I saw last week. The signs are encouraging...

overnight update: See Attachment #2 - looking at the past 11 hours of second trend data during which the arm stayed locked, there actually seems to have been more significant variation in the beatnote amplitude. Swings of up to 6dBm are seen on a ~20min timescale, while there is also some longer term drift over 12 hours by a couple of dBm. There is probably a systematic error in the Y-axis, as I measured the RF power at the input of the power splitter at the LSC rack to be ~3dBm, so I expect something closer to 0dBm to be the LO input power which is what I am monitoring. So further debugging is required - I think I'll start by aligning the X fiber coupled beam to one of the fiber's special axes.

All rack power supplies labeled if their load changed.

For testing the new IR ALS noise, we had decided that we would like to use the differential output of the demodulated ALS beat signal, as opposed to a single-ended output, as measurements suggested the former to be a lower noise configuration than the latter. For this purpose, Koji and I acquired a couple of old AA boards from the WB electronics shop. These are however, rev2 of the board, whereas the latest version is v6. The main difference between v2 and v6 is that (i) the THS4131 instrumentation amplifier has the Vocm pin grounded in v6 but is floating in v2 and (ii) the buffer opamps are AD8622 in v6 but are AD8672 in v2. But in fact, the boards we have are stuffed with AD8682. 

I talked to Rich on Friday, and he seemed to think the AD8672 didn't have any issues noise-wise, the main reason they changed it was because its power consumption was high, and was causing overheating when several of these 1U chassis were packed closely together in an electronics rack. But the AD8682, which is what we have, has comparable power consumption to the AD8622. It is however a JFET opamp, and the voltage noise is a bit higher than the AD8622. 

I am sure there is a way to LISO model a differential output opamp like the THS4131, but I thought I'd simulate the noise in LTSPICE instead. But I couldn't get that to work. So instead, I just measured the transfer function and noise of a single channel, for which Koji had expertly hacked together a custom shorting of the THS4131 Vocm pin to ground. Attachments #1 and #2 show the measurement. All looks good. Note that the phase is 180 at DC because I had hooked up the input signal opposite to what it should have been. The voltage noise of the differential outputs (each measured w.r.t. ground, with both inputs shorted to ground by a short patch cable) at 10 Hz is <100nV/rtHz, and the ADC noise is expected to be ~1uV/rtHz, so I think this is fine.

Conclusion: I think for the ALS test, we can just use the AA board in this config without worrying too much about replacing the buffer stage opamps, even though we've ordered 100pcs of AD8622.

Addendum 7 Mar 2018 11am: As per this document, the output noise of the AA board should be <75nV/rtHz from 10 Hz-50 kHz. So maybe the AD8682 noise is a little high after all. I've gotten the LTSpice model working now, will post the comparison of modelled output noise for various combinations here shortly.

Here are the plots. Comments:

1. Measurement and model agree quite well .
2. Of the 3 OpAmps, the ones installed seem to be the noisiest (per model). 
3. Despite #2, I don't think it is critical to replace the buffer opamps as we only win by ~10nV/rtHz in the 300-10kHz range.
4. I don't understand the spec given in T070146. It says the noise everywhere between 10Hz-50kHz should be <75nV/rtHz. But even the model suggests that at 10Hz, the noise is ~250nV/rtHz for any choice of buffer opamp, so that's a factor of 3 difference which seems large. Maybe I made a mistake in the model but the agreement between measurement and model for the AD8682 choice gives me confidence in the simulation. LTSpice files used are in Attachment #3. Could also be an artefact of the way I made the measurement - between an output and ground instead of differentially...

I like LTspice for such modeling - the GUI is nice to have (though I personally think that typing out a nodal file a la LISO is faster), and compared to LISO, I think that the LTspice infrastructure is a bit more versatile in terms of effects that can be modeled. We can also easily download SPICE models for OpAmps from manufacturers and simply add them to the library, rather than manually type out parameters in opamp.lib for LISO. But the version available for Mac is somewhat pared down in terms of the UI, so I had to struggle a bit to find the correct syntax for the various simulation commands. The format of the exported data is also not as amenable to python plotting as LISO output files, but i'm nitpicking...

[Koji, Gautam]

Yesterday, we installed some new DIN rail connectors at the LSC rack to provide 3 new outputs each for +24V DC and -24V DC. The main motivation was to facilitate the installation and powering of the differential receiving AA board. The regulators used inside the 1U chassis actually claims a dropout voltage of 0.5V and outputs 14V nominally, so a +/-15V DC supply would've perhaps been sufficient, but we decided to leave a bit more margin, and unfortunately, there are no +/-18V DC KEPCO linear power supplies to the LSC rack. Procedure:

1. Prepared a bunch of DIN rail connectors with tinned, daisy-chained wires in the office area. Checked continuity and isolation with DMM.
2. Checked that the two Sorensens at the bottom of the LSC rack were powering the RF distribution box and nothing else at the LSC rack.
3. Walked over to the little rack housing all the KEPCO DC power supplies that supply DC voltages to the LSC rack. After checking that the labelled voltage and current values were correct, we turned them off, first +/-5V, then +/-15V (2 sets), and finally +/-24V.
4. Installed the pre-assembled DIN connectors on the side rail at the LSC rack (we had to remove the side panel for the rack to do this work).
   • We used the ports supplying power to the ALS 1U demod chassis (+/-24V DC) to tap these voltages to our newly installed connectors.
   • The interconnecting wires are rather thick gauge, and especially for the ground wire, we found it impossible to push in our tap-off wire into the "correct/hot" side of the DIN blocks. So we had to use the other side instead. I'll upload a picture shortly which will make this more clear.
   • Checked continuity and isolation with DMM.
   • Turned the KEPCOs back on in reverse order to how they were turned off.
   • Measured voltages on the hot side of the DIN blocks, confirmed that they were as expected.
5. Prepared a 12AWG aLIGO style power cable to connect to the 1U chassis. A reel of this cabling, with yellow shielding, is located ~halfway along under the EW arm. Koji prepared the actual connector and housed it in a DSUB shell as per aLIGO wiring color scheme.
6. Installed the power cabling to one set of our 3 newly installed +/-24V DC power supplies.
7. Inserted fuses into the hot DIN blocks, measured voltage at connector end of our newly installed power cable. At first, I forgot to check if the fuse blocks had fuses inside, but after this was rectified, voltages were as expected .

The c1lsc frontend models crashed for some reason during this procedure. Now the c1sus frontend model is also behaving weirdly. It is unclear to me if/how this work would have led to these problems, but the temporal correlation (but not causation?) is undeniable.

[Jon, Gautam, Johannes]

Summary: In support of making a proof-of-concept RF measurement of the SRC Gouy phase, we've implemented a PLL of the aux. 700mW NPRO laser frequency to the PSL. The lock was demonstrated to hold for minutes time scales, at which point the slow (currently uncontrolled) thermal drift of the aux. laser appears to exceed the PZT dynamic range. New (temporary) hardware is set up on an analyzer cart beside the PSL launch table.

Next steps:

- Characterize PLL stability and noise performance (transfer functions).

- Align and mode-match aux. beam from the AS table into the interferometer.

- With the IFO locked in a signal-recycled Michelson configuration, inject broadband (swept) AM sidebands via the aux. laser AOM. Coherently measure the reflection of the driven AM from the SRC.

- Experiment with methods of creating higher-order modes (partially occluding the beam vs. misaligning into, e.g., the output Faraday isolator). The goal is identify a viable techinque that is also possible at the sites, where the squeezer laser serves as the aux. laser.

The full measurement idea is sketched in the attached PDF.

Some notes about the setup and work at the PSL table today, Jon can add to / correct me.

• All equipment for the phase locking now sit on a cart that is on the west side of the MC beam tube, near ITMX chamber.
• Cables have been routed through the space between the PSL enclosure and the optical table.
• HEPA was turned up for this work, now it has been turned down to the nominal level of 30%.
• Alignment into the PMC had degraded a bit - I tweaked it and now MC transmission is up at ~15600 which is a number I am used to. We still don't have a PMC transmission monitor since the slow ADC failure.

Attached are final details of the phase-locked loop (PLL) implementation we'll use for slaving the AUX 700 mW NPRO laser to the PSL.

The first image is a schematic of the electronics used to create the analog loop. They are curently housed on an analyzer cart beside the PSL table. If this setup is made permanent, we will move them to a location inside the PSL table enclosure.

The second image is the measured transfer function of the closed loop. It achieves approximately 20 dB of noise suppression at low frequencies, with a UGF of 50 kHz. In this configuration, locks were observed to hold for 10s of minutes.

this doesn't make much sense to me; the phase to frequency conversion (mixer-demod to PZT ) should give us a 1/f loop as Johannes mentioned in the meeting. That doesn't agree with your loop shape.

How about give us some more details of the setup including photos and signal/power levels? And maybe measure the LB1005 TF by itself to find out what's wrong with the loop.

[jon, steve, gautam]

Some points which Jon will elaborate upon (and put photos of) in his detailed elog about this setup:

• PLL electronics (mixer, coupler, ZFL500HLN amplifier and DC power supply for the beatnote, SR560 servo) all reside on the newly installed lower level PSL shelf.
• Cross connect channel C1:PSL-126MOPA_126CURADJ hijacked for remote temperature control of the AUX NPRO. Note that shield of front panel BNC is ground and so even though the manual says the controller accepts +/-10V, this is not a differential input. BNC cable was routed from cross connect to PSL enclosure, MEDM slider will be setup.
• There was an SMA cable running from the VEA to the control room which we decided to use for monitoring of the beatnote amplitude on the control room analyzer. Yesterday, Steve and I routed the end of this inside the VEA, near 1X2 originally, to inside the PSL table where it is hooked up to the (20dB) coupled amplifier output. This required some work on the cable tray, we were careful but in case there is some wonkiness in some signals, perhaps this work is to blame.

We are now in a state where the PLL can be locked remotely from the control room by tweaking the AUX laser temperature . Tomorrow, Keerthana will work on getting Craig's/Johannes' Digital Frequency Counter script working here, I think we can easily implement a PLL autolocker if we have some diagostic that tells us if the PLL us locked or not.

Steve informed me that there is an acoustic hum inside the PSL enclosure which wasn't there before. Indeed, it is at ~295Hz, and is from the Bench power supply used to power the ZFL500HLN amplifier. This will have to go...

[Koji, Gautam]

Summary:

As I suspected, when the SR560 is operated in 1 Hz, first order LPF mode, the (electronic) transfer function has a zero at ~5kHz (!!!).

Details:

This is what allowed the PLL to be locked with this setting with UGF of ~30kHz. On the evidence of Attachment #3, there is also some flattening of the electrical TF at low frequencies when the SR560 is driving the NPRO PZT. I'm pretty sure the flattening is not a data download error but since this issue needs further investigation anyway, I'm not reading too much into it. I fit the model with LISO but since we don't have low frequency (~1Hz) data, the fit isn't great, so I'm excluding it from the plots.

We also did some PLL loop characterization. We decided that the higher output range (10Vp bs 10Vpp for the SR560) of the LB1005 controller means it is a better option for the PLL. The lock state can also be triggered remotely. It was locked with UGF ~ 60kHz, PM ~45deg.

We also measured the actuation coefficient of the NPRO laser PZT to be 4.89 +/- 0.02 MHz/V. Quoted error is (1-sigma) from the fit of the linear part of the measured transfer function to a single pole at DC with unknown gain. I used the "clean" part of the measurement that extends to lower frequencies for the fit, as can be seen from the residuals plot. Good to know that even though the LDs are dying, the PZT is still going strong :D.

Remaining loop characterization (i.e. verification of correct scaling of in loop suppression with loop gain etc.) is left to Jon.

Measurement schemes:

1. OLG (Attachment #1) was measured using the usual IN1/IN2 technique.
2. PZT calibration (Attachment #2) was measured by injecting an excitation at the PLL control point.
   • The ratio of the PLL error point (Volts) to Excitation (Volts) was measured using the SR785.
   • The error point was calibrated by looking at the PLL open loop Vpp (corresponds to pi radians of phase shift).
   • Dividing the fitted gain of the phase->Frequency conversion by the error point calibration, we get the PZT actuation coefficient. 

Some other remarks:

1. In the swept-sine mode, the SR785 measures transfer functions by taking the ratio of complex FFT values of its inputs at the drive frequency. So the phase in particular is a good indicator of whether the measurement is coherent or not.
2. In all these measurements, the PLL gain is huge at low frequencies, and hence, the excitation is completely squished on propagating through the loop. E.g. a 10mV excitation is suppressed by a factor of ~60dB = 1000 to 10uV, and if the analyzer autoRange is set to UpOnly, it is easy to see how this is drowned at the IN1 input. This is why the measurements lose coherence below ~1 kHz.
3. It is easy to imagine implementing an EPICS servo that offloads the DC part of the LB box control signal to the SLOW frequency input on the Lightwave controller. This would presumably allow us to extend the lock timescales. We can also easily implement a PLL autolocker.
4. Preliminary investigation of the SR560 situation suggests that individual filter stages can only achieve a maximum stopband attenuation of 60dB relative to the passband. When we cascade two stages together, 120dB seems possible...

[Jon, Gautam]

Attached is supporting documentation for the AUX-PSL PLL electronics installed in the lower PSL shelf, as referenced in #13845.

Some initial loop measurements by Gautam and Koji (#13848) compare the performance of the LB1005 vs. an SR560 as the controller, and find the LB1005 to be advantageous (a higher UGF and phase margin). I have some additional measurements which I'll post separately.

Loop Design

Pickoffs of the AUX and PSL beams are routed onto a broadband-sensitive New Focus 1811 PD. The AUX laser temperature is tuned to place the optical beat note of the two fields near 50 MHz. The RF beat note is sensed by the AC-coupled PD channel, amplified, and mixed-down with a 50 MHz RF source to obtain a DC error signal. The down-converted term is isolated via a 1.9-MHz low-pass filter in parallel with a 50 Ohm resistor and fed into a Newport LB1005 proportional-integral (PI) servo controller. Controller settings are documented in the below schematic. The resulting control signal is fed back into the fast PZT actuator input of the AUX laser.

Hardware Photos

I setup a basic MEDM screen for remote control of the PLL.

The Slow control voltage slider allows the frequency of the laser to be moved around via the front panel slow control BNC.

The TTL signal slider provides 0/5V to allow triggering of the servo. Eventually this functionality will be transferred to the buttons (which do not work for now).

The screen can be accessed from the PSL dropdown menu in sitemap. We can make this better eventually, but this should suffice for initial setup.