Being suspicious of FSS PC path as the culprit of the MC unlocks, I opened the FSS box and connected a probe to the TP7,
which is a test point in the PC path (before high voltage amplifier).
The signal is routed to an unused fast DAQ channel in the IOO rack. It is named C1:IOO-MC_TMP1 and recorded by the frame
builder. You can use this channel as a generic test DAQ channel later.
By looking at the attachment, the PC path (C1:IOO-MC_TMP1) goes crazy at the same time as other channels. So probably
it is not the trigger for the MC unlock.
Then I noticed the WFS signals drift away just before the unlock as shown in the attached plot. So now the WFS is the
main suspect.
Rob tweaked MC1 pitch to center the WFS QPDs while the MC is not locked. It improved the shape of the MC reflection.
However, the sudden MC unlock still happens. We then lowered the WFS gain from 0.5 to 0.3. Did not change the situation.
It looks like the MC length loop starts oscillating after the WFS signals drift away.
We will measure the WFS and MC OPLTF to see the stability of the loops tomorrow.
|