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Entry  Tue Jun 21 21:17:16 2022, yuta, Update, BHD, RTS models for BHD added but PCIE error remaining Screenshot_2022-06-21_20-12-55_C1HPC.pngScreenshot_2022-06-21_20-14-56_C1SU2.pngScreenshot_2022-06-21_20-13-38_C1LSC.pngScreenshot_2022-06-21_20-34-44_RED.png
    Reply  Wed Jun 22 14:44:03 2022, Anchal, Update, BHD, Fixed DC error in c1su2, added new library model for suspensions 
       Reply  Tue Jun 28 14:24:23 2022, yuta, Update, BHD, BHD DC PD signals now also sent to c1lsc to circumvent IPC error C1LSC.JPGC1SUS2.JPGScreenshot_2022-06-28_16-03-16_BHDDCPDcopied.png
          Reply  Mon Nov 14 17:45:02 2022, yuta, Update, BHD, BHD DC PD unwhitening and removing cables to c1lsc Screenshot_2022-11-15_13-08-17.png
             Reply  Mon Nov 21 18:43:46 2022, yuta, Update, BHD, c1hpc and c1lsc modified to send BHD_DIFF and BHD_SUM Screenshot_2022-11-21_18-42-49_BHD.png
                Reply  Wed Nov 23 11:06:08 2022, Anchal, Update, BHD, c1hpc and c1sus modified to add BS dither and demodulation option 
                   Reply  Tue Nov 29 15:32:32 2022, Anchal, Update, BHD, c1hpc model updates to support double audio dither Screenshot_2022-11-29_15-36-05.png
Message ID: 16935     Entry time: Tue Jun 21 21:17:16 2022     Reply to this: 16938
Author: yuta 
Type: Update 
Category: BHD 
Subject: RTS models for BHD added but PCIE error remaining 

[Anchal, Yuta]

RTS models for BHD homodyne phase control (c1hpc) and angular control (c1bac) are created and added to c1sus2.
c1su2 and c1lsc models were modified accordingly.
We still have issues with IPC PCIE connection sending DCPD A and B signals to c1lsc and DC error 0x2000 in c1su2 model.

c1hpc (host: c1sus2) Attachment #1
 This model is for homodyne phase control.
 It can dither LO1, LO2, AS1, AS4 in POS and demodulate mixture of DCPD A/B signals for the phase control to feedback to those optics.
 It also sends DCPD A/B signals to c1lsc via cdsIPCx_PCIE.
 Dither and controls signals are sent to the optics via cdsIPCx_SHMEM.

c1bac (host: c1sus2)
 This model is for BHD angular control.
 It is basically the same as c1hpc, but it is for PIT and YAW dithering of LO1, LO2, AS1, AS4.

c1su2 (host: c1su2) Attachment #2
 LSC and ASCPIT/YAW feedback signals from c1hpc and c1bac via shared memory were added to send them to corresponding optics.
 Somehow Mux/Demux didn't work to send SHMEM signals inside the subsystem in the Simulink model (this works for ADC, but probably not for IPC stuff?), and we had hard time make-install-ing this model.

c1lsc (host: c1lsc) Attachment #3
 DCPD A/B signals from c1hpc via PCIE were added for our new error signals for LSC.

Starting and restarting the models
 After having some troubles make-install-ing modified models (be careful of goto and from tags!), we stopped all the models in c1sus, c1ioo, c1lsc, c1sus2 and started all of them, including new c1hpc and c1bac models.
 This somehow created RFM errors in c1scx and c1scy.
 So, we proceeded to do the same step we did in 40m/16887 and 40m/15646, now including c1sus2 for the restart.
 Initial attempt made c1lsc, c1sus, c1ioo mostly red, so scripts/cds/rebootC1LSC.sh was run again on pianosa.
 RFM issues for c1scx and c1scy were solved.
 Shared memory within c1sus2 seems to be working, but sending DCPD A/B signals from c1hpc to c1lsc is not working (see Attachement #4).

Next:
 - Fix C1:HPC-LSC_DCPC_A/B issue
 - Make/modify MEDM screens

Attachment 1: Screenshot_2022-06-21_20-12-55_C1HPC.png  198 kB  Uploaded Tue Jun 21 22:18:52 2022  | Show | Hide all | Show all
Attachment 2: Screenshot_2022-06-21_20-14-56_C1SU2.png  78 kB  Uploaded Tue Jun 21 22:19:05 2022  | Hide | Hide all | Show all
Screenshot_2022-06-21_20-14-56_C1SU2.png
Attachment 3: Screenshot_2022-06-21_20-13-38_C1LSC.png  72 kB  Uploaded Tue Jun 21 22:19:14 2022  | Show | Hide all | Show all
Attachment 4: Screenshot_2022-06-21_20-34-44_RED.png  286 kB  Uploaded Tue Jun 21 22:21:09 2022  | Hide | Hide all | Show all
Screenshot_2022-06-21_20-34-44_RED.png
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