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Entry  Wed Feb 24 22:13:47 2021, Jon, Update, CDS, Planning document for front-end testing 
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                      Reply  Tue Apr 6 07:19:11 2021, Jon, Update, CDS, New SimPlant cymac 
                         Reply  Tue Apr 6 11:13:01 2021, Jon, Update, CDS, FE testing 
                            Reply  Sat Apr 10 08:51:32 2021, Jon, Update, CDS, I/O Chassis Assembly 
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                                  Reply  Tue May 4 07:38:36 2021, Jon, Update, CDS, I/O Chassis Assembly Screen_Shot_2021-05-03_at_4.16.06_PM.png
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                                        Reply  Tue May 11 17:43:09 2021, Koji, Update, CDS, I/O Chassis Assembly 
                                           Reply  Fri May 28 11:16:21 2021, Jon, Update, CDS, Front-End Assembly and Testing c1bhd.pnggds_tp.pngteststand.jpegbench_supply.jpeg
                                              Reply  Sun Jun 6 08:42:05 2021, Jon, Update, CDS, Front-End Assembly and Testing c1bhd.png16bit_dacs.pngmyricom.png
                                                 Reply  Tue Jun 22 16:53:01 2021, Ian MacMillan, Update, CDS, Front-End Assembly and Testing 
                                                    Reply  Thu Jun 24 17:32:52 2021, Ian MacMillan, Update, CDS, Front-End Assembly and Testing C1-SU2_Channel_Responses.pdfC1-BHD_Channel_Responses.pdfCDS_Channel_Test.zip
                                                       Reply  Fri Jun 25 14:06:10 2021, Jon, Update, CDS, Front-End Assembly and Testing test_stand.JPG
Message ID: 16224     Entry time: Thu Jun 24 17:32:52 2021     In reply to: 16220     Reply to this: 16225
Author: Ian MacMillan 
Type: Update 
Category: CDS 
Subject: Front-End Assembly and Testing 

Anchal and I ran tests on the two systems (C1-SUS2 and C1-BHD). Attached are the results and the code and data to recreate them.

We connected one DAC channel to one ADC channel and thus all of the results represent a DAC/ADC pair. We then set the offset to different values from -3000 to 3000 and recorded the measured signal. I then plotted the response curve of every DAC/ADC pair so each was tested at least once.

There are two types of plots included in the attachments

1) a summary plot found on the last pages of the pdf files. This is a quick and dirty way to see if all of the channels are working. It is NOT a replacement for the other plots. It shows all the data quickly but sacrifices precision.

2) In an in-depth look at an ADC/DAC pair. Here I show the measured value for a defined DC offset. The Gain of the system should be 0.5 (put in an offset of 100 and measure 50). I included a line to show where this should be. I also plotted the difference between the 0.5 gain line and the measured data. 

As seen in the provided plots the channels get saturated after about the -2000 to 2000 mark, which is why the difference graph is only concentrated on -2000 to 2000 range. 

Summary: all the channels look to be working they all report very little deviation off of the theoretical gain. 

Note: ADC channel 31 is the timing signal so it is the only channel that is wildly off. It is not a measurement channel and we just measured it by mistake.

Attachment 1: C1-SU2_Channel_Responses.pdf  4.239 MB  Uploaded Thu Jun 24 18:46:27 2021  | Show | Hide all | Show all
Attachment 2: C1-BHD_Channel_Responses.pdf  2.228 MB  Uploaded Thu Jun 24 18:46:37 2021  | Show | Hide all | Show all
Attachment 3: CDS_Channel_Test.zip  7.684 MB  Uploaded Thu Jun 24 18:47:36 2021
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