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Entry  Tue Jul 16 16:00:01 2019, gautam, Update, CDS, c1iscaux Supermicro setup IMG_7769.JPG
    Reply  Wed Jul 17 21:22:41 2019, gautam, Update, CDS, CM board Latch Enable subtlety 
       Reply  Sun Jul 21 12:55:38 2019, gautam, Update, CDS, CM board Latch Enable test script LatchLogic.pdfLatchLogicTest.png
          Reply  Fri Aug 9 08:59:04 2019, gautam, Update, CDS, Prep for install of c1iscaux 
             Reply  Sun Aug 11 11:47:42 2019, gautam, Update, CDS, Bench test of c1iscaux 
                Reply  Mon Aug 12 17:36:04 2019, gautam, Update, CDS, More bench test of c1iscaux iscauxCheclist.pdf
                   Reply  Mon Aug 12 21:25:19 2019, Koji, Update, CDS, More bench test of c1iscaux 
                   Reply  Tue Aug 13 08:07:09 2019, gautam, Update, CDS, P1--->P2 
                      Reply  Tue Aug 13 14:36:17 2019, gautam, Update, CDS, P1--->P2 
                   Reply  Fri Aug 16 16:40:04 2019, gautam, Update, CDS, 1Y3 work newLook1Y3.JPGIMG_7803.JPGc1lsc_crashed.png
                      Reply  Sat Aug 17 16:49:23 2019, gautam, Update, CDS, More 1Y3 work Screen_Shot_2019-08-17_at_3.00.57_PM.pngScreen_Shot_2019-08-17_at_3.12.23_PM.pngIMG_7804.JPGScreenshot_from_2019-08-17_17-04-47.png
                         Reply  Mon Aug 19 14:36:21 2019, gautam, Update, CDS, c1iscaux remaining work caseForSmallerFootprint.pdf
                            Reply  Tue Aug 20 19:05:24 2019, Koji, Update, CDS, MC1 (and MC3) troubleshoot Screenshot_from_2019-08-20_17-26-01.pngScreenshot_from_2019-08-20_17-43-03.png
                               Reply  Thu Aug 22 12:54:06 2019, Koji, Update, CDS, MC1 glitch removed (for now) and IMC locking recovered 7x
                                  Reply  Thu Aug 22 20:56:51 2019, Koji, Update, CDS, MC1 glitch removed (for now) and IMC locking recovered 
                            Reply  Fri Aug 23 18:46:17 2019, Jon, Update, CDS, c1iscaux remaining work 
                               Reply  Sun Aug 25 14:18:08 2019, gautam, Update, CDS, c1iscaux remaining work Screen_Shot_2019-08-25_at_10.38.37_PM.png
    Reply  Thu Jul 18 10:46:04 2019, gautam, Update, CDS, Database files made 
       Reply  Thu Jul 18 19:58:56 2019, gautam, Update, CDS, Work on Acromag chassis IMG_7771.JPGIMG_7770.JPGIMG_7772.JPG
          Reply  Fri Jul 19 19:44:03 2019, gautam, Update, CDS, Database file test Whitening.png
Message ID: 14790     Entry time: Sun Jul 21 12:55:38 2019     In reply to: 14769     Reply to this: 14837
Author: gautam 
Type: Update 
Category: CDS 
Subject: CM board Latch Enable test script 

DATED, SEE ELOG14941 for the most up-to-date info on latch.py.

I wrote (/cvs/cds/caltech/target/c1iscaux3/latch.py) and tested the logic illustrated in Attachment #1. Results of a test are shown in Attachment #2, the various channels change as expected. Note that for negative values of the gain channel, the corresponding "BITS" channel will take on values like 65536 - this is because the mbboDirect data type is a 16 bit data type, and presumably the MSB is the sign bit. A bit mask is applied to this channel before the actual BIO unit bits are set - we should verify that the correct behavior happens, but I don't immediately see any problems.

To me, this is a robust logic, but it will benefit from more sets of eyes giving it a look over. The idea is to run this continuously on the Supermicro machine.

Apart from this, I also fixed some errors in the mbboDirect record syntax - so now I am able to start up the EPICS server without it throwing any error messages. It remains to verify that changing an EPICS gain slider results in the appropriate gain bits being flipped in the correct way (on the hardware side, I think the correct behavior is happening on the software end). For this testing, I turned off the old c1iscaux crate at ~10am, and started up the server on c1iscaux3. I am reverting to the nominal config now (~1pm).

Further testing will require the wiring inside the Acromag chassis to be completed. This should be the priority task for next week.

*Update 1130 22 July 2019: I've now installed the required dependencies on c1iscaux3 and setup the latch.py script to run as a systemctl process dependent on modbusIOC.service.

Attachment 1: LatchLogic.pdf  116 kB  Uploaded Sun Jul 21 15:26:17 2019  | Hide | Hide all
LatchLogic.pdf
Attachment 2: LatchLogicTest.png  10 kB  Uploaded Sun Jul 21 15:26:25 2019  | Hide | Hide all
LatchLogicTest.png
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