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Entry  Tue Jul 16 16:00:01 2019, gautam, Update, CDS, c1iscaux Supermicro setup IMG_7769.JPG
    Reply  Wed Jul 17 21:22:41 2019, gautam, Update, CDS, CM board Latch Enable subtlety 
       Reply  Sun Jul 21 12:55:38 2019, gautam, Update, CDS, CM board Latch Enable test script LatchLogic.pdfLatchLogicTest.png
          Reply  Fri Aug 9 08:59:04 2019, gautam, Update, CDS, Prep for install of c1iscaux 
             Reply  Sun Aug 11 11:47:42 2019, gautam, Update, CDS, Bench test of c1iscaux 
                Reply  Mon Aug 12 17:36:04 2019, gautam, Update, CDS, More bench test of c1iscaux iscauxCheclist.pdf
                   Reply  Mon Aug 12 21:25:19 2019, Koji, Update, CDS, More bench test of c1iscaux 
                   Reply  Tue Aug 13 08:07:09 2019, gautam, Update, CDS, P1--->P2 
                      Reply  Tue Aug 13 14:36:17 2019, gautam, Update, CDS, P1--->P2 
                   Reply  Fri Aug 16 16:40:04 2019, gautam, Update, CDS, 1Y3 work newLook1Y3.JPGIMG_7803.JPGc1lsc_crashed.png
                      Reply  Sat Aug 17 16:49:23 2019, gautam, Update, CDS, More 1Y3 work Screen_Shot_2019-08-17_at_3.00.57_PM.pngScreen_Shot_2019-08-17_at_3.12.23_PM.pngIMG_7804.JPGScreenshot_from_2019-08-17_17-04-47.png
                         Reply  Mon Aug 19 14:36:21 2019, gautam, Update, CDS, c1iscaux remaining work caseForSmallerFootprint.pdf
                            Reply  Tue Aug 20 19:05:24 2019, Koji, Update, CDS, MC1 (and MC3) troubleshoot Screenshot_from_2019-08-20_17-26-01.pngScreenshot_from_2019-08-20_17-43-03.png
                               Reply  Thu Aug 22 12:54:06 2019, Koji, Update, CDS, MC1 glitch removed (for now) and IMC locking recovered 7x
                                  Reply  Thu Aug 22 20:56:51 2019, Koji, Update, CDS, MC1 glitch removed (for now) and IMC locking recovered 
                            Reply  Fri Aug 23 18:46:17 2019, Jon, Update, CDS, c1iscaux remaining work 
                               Reply  Sun Aug 25 14:18:08 2019, gautam, Update, CDS, c1iscaux remaining work Screen_Shot_2019-08-25_at_10.38.37_PM.png
    Reply  Thu Jul 18 10:46:04 2019, gautam, Update, CDS, Database files made 
       Reply  Thu Jul 18 19:58:56 2019, gautam, Update, CDS, Work on Acromag chassis IMG_7771.JPGIMG_7770.JPGIMG_7772.JPG
          Reply  Fri Jul 19 19:44:03 2019, gautam, Update, CDS, Database file test Whitening.png
Message ID: 14769     Entry time: Wed Jul 17 21:22:41 2019     In reply to: 14765     Reply to this: 14790
Author: gautam 
Type: Update 
Category: CDS 
Subject: CM board Latch Enable subtlety 

[koji, gautam]

Koji pointed out an important subtlety pertaining to the "LATCH ENABLE" signal line on the CM board. The purpose of this line is to smoothly facilitate the transition of a change in the "multi-bit-binary-outputs", a.k.a. "mbbo", that are controlled by MEDM gain sliders, to the analog electronics on the CM board. Why is this necessary? Imagine changing the gain from 7dB (=0111 in mbbo representation) to 8dB (=1000 in mbbo representation). In order to realize this change, all 4 bits have to change their state. But this almost certainly doesn't happen synchronously, because our EPICS interface isn't synchronous. So at some intermediate times, the mbbo representation could be 0100 (=4dB), or 1111 (=15dB), or many other possible values, which are all significantly different from either the initial value or the desired final state. This is clearly undesirable.

In order to protect against this kind of error, a Latched output part, 74ALS573, is used to buffer the physical digital logic levels from the switches in the analog gain stages. So in the default state, the "LATCH ENABLE" signal line is held "LOW". When a change happens in the EPICS value corresponding to a gain slider, the "LATCH ENABLE" state is quickly toggled to "HIGH", so as to enable the appropriate analog gain stages to be switched, and then again to "LOW", at which point the latch holds its output state. This logic is currently implemented by a piece of code called "latch.o", which is the compiled version of "latch.st", which may be found in /cvs/cds/caltech/target/c1iool0 where it presumably was written for the IMC servo board, but not in /cvs/cds/caltech/target/c1iool0  , which is where the CM board database files reside. The only elog reference I can find pertaining to this particular piece of code is from Alan, and doesn't say anything about the actual logic.

For the new c1iscaux, we need to implement this logic somehow. After discussion between Koji and me, we feel that a piece of python code is sufficient. This would continuously run in the background on the supermicro server machine. The channel hierarchy for each gain channes is as follows (I've taken the example of C1:LSC-CM_REFL1_GAIN):

  • C1:LSC-CM_REFL1_GAIN ------ this is the channel tied to an MEDM slider, and so is a "soft" channel
  • C1:LSC-CM_REFL1_SET ------- this is a "soft" channel that gets converted to an mbbo
  • C1:LSC-CM_REFL1_BITS ------ this is a channel that actually controls (multiple) physical binary outputs on the Acromag

So the logic will be that it continuously scans the EPICS channel C1:LSC-CM_REFL1_GAIN  for a change in set value. When a change is detected, it has to update the C1:LSC-CM_REFL1_SET channel. In the next EPICS refresh cycle, this would result in the mbbo bits, C1:LSC-CM_REFL1_BITS , all changing to the appropriate values. After these changes have happened, we need to toggle the LATCH ENABLE in order to allow the changes to propagate to the analog gain stage switches. Need to think about what's the best way to do this.

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