Migration of the 10Hz pole from the output stage of the FSS to the pomona box was successful.
This also allowed me to insert my offsetting/summing point circuit.
- Remove C63 (1uF cap) of the FSS
- Short 500 Ohm in the pomona box
This removed 10Hz pole in FSS and 32 Hz zero in the pomona box.
In total we obtain the gain and range of 3.2 for the fast PZT path.
3x10^2 to 3x10^3 times more filtering of the HV amp noise between 10kHz and 100kHz.
The current maximum gains of the FSS is
Overall +19dB (prev. +13dB)
Fast +30dB (prev +21.5dB)
- Insert a summing amplifier between the FSS box and the HV amp.
- This amplifier attenuate the input by a factor of 2, and add 5V. i.e. +/-10V input => 0~10V output.
- This just worked fine.
- Now the fast gain is nominally +30dB.
- In order to provide more room to play with the fast-PC cross over, I moved the pole freq from 2.9Hz to 9.9Hz
This was done by replacing a 5kOhm in the pomona box by a 1.5kOhm.
- I just noticed that the output impedance of the FSS (15.8kOhm) and the input impedance of the summing amp (10k Ohm)
interfere and gives additional 1/2.58 attenuation in addition to the attenuation in the summing amplifier.
This yields the output range of the HV amp between 45-105V, instead of 0-150V. This is not nice.
- The output impedance of the FSS box (R46 15.8kOhm) was replaced with 100Ohm.
- Now the PMC unlocks very frequently. This might have come from the PMC locking issue or too much gain of the IMC
Trial 5 (final):
- I suspected that the PMC unlock is caused by too much actuation at the high freq. So I decided to revert the pomona box change