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Message ID: 1902     Entry time: Wed Feb 17 11:56:48 2021
Author: Paco 
Type: Lab Infrastructure 
Category: Electronics 
Subject: UPDH box zero model and SR560 "lock" 

UPDHv3 box (serial 17142) is bogus. While retrieving values of some of the components to plug into working zero model, saw the VGA stage is bypassed by a previously unnoticed hack. Verified this by taking TF and not seeing any changes with respect to the gain knob (shown below are zero's model TFs suggesting a tunable UGF from ~ 10 Hz to 1 kHz), so this box is not good for a standalone servo.

As suggested a few meetings ago, made a quick and dirty lock using a single SR560 and took measurement of something* CLTF (SR560 gain = 10) below. New goal is to find a decent replacement, for which decided to use RedPitaya's python API "pyRPL". Just using the GUI out of the box can also lock the cavity relatively quickly but neither method results in longer than 1 minute lock... so took one step back to polish the pdh error signal.

* Something = Use SR785 TF measurement with source on Ch1, and to B input in SR560. The SR560 in (A-B) mode, and demodulated signal connected to A. The loop was closed with the SR560 output driving the PZT, and Ch2 of SR785. Wouldn't call this CLTF...

Attachment 1: updhv3_VGA_gain.pdf  12 kB  | Hide | Hide all | Show all
updhv3_VGA_gain.pdf
Attachment 2: SR560_OLTFSR785_17-02-2021_164500.pdf  31 kB  Uploaded Wed Feb 17 16:51:08 2021  | Show | Hide all | Show all
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