Aaron and I previously saw that the 40 Hz cantilever mode was using up most of the PDH signal's linear range while in lock.
This means that the loop has just enough gain to stay locked. Increasing the gain seems to make it unstable, so we want to lower the UGF.
So perhaps a 3x reduction in the UGF and a 10x increase in the gain at 40 Hz? To do this we want to shape the loop with a pole:zero boost having a 30x gain at DC relative to the high frequency part.
We can do this by making a pole zero section in a Pomona box with a pole at 40 Hz and a zero at 1200 Hz. This should be stable, since I expect our UGF is > 3 kHz.
To figure out the component values, we need to now the output impedance of the LB box and the input impedance of the current driver. Any ideas?