As part of the effort to debug what was happening with the slow computers, I disabled the auto MEDM snapshots process that Yoichi/Kakeru setup some long time ago:

https://nodus.ligo.caltech.edu:30889/medm/screenshot.html

We have to re-activate it now that the MEDM screen locations have been changed. To do this, we have to modify the crontab on nodus and also the scripts that the cron is calling. I would prefer to run this cron on some linux machine since nodus starts to crawl whenever we run ImageMagick stuff.

Also, we should remember to start moving the old target/ directories into the new area. All of the slow VME controls are still not in opt/rtcds/.

(Suresh, Yuta)

Background:
  Last week, we reduced the common mode displacement of the beam through MC1 to MC3. 
  Next work is to tilt the beam and center it.

What we did:
  1. Changed the offset going into 1201 Low Noise Amplifier(1201 is for adding +5V offset so that the feedback signal will be in the range of 0-10V)
  2. Using the last steering mirror(SM@PSL) and IM1, tilted the beam
  3. As the beam height changed alot(~0.5cm higher at IM1), MC1 reflection could not reach MCREFL PD. So, we tilted the mirror just after MC1, too.

Result:


Plan:
  - continue to tilt IM1 in small increments in order to reduce PIT/YAW to length coupling
      If large increments, it takes so much time re-aligning MC to get flashing!

By the way:
    The signal we kept saying "MCL" was not the error signal itself. It was a feed back signal(output of the mode cleaner servo board). The cable labeled "MC REFL" is the error signal. Compare MEDM screen C1IOO_MC_SERVO.adl and the mode cleaner servo board at 1X2. You will be enlightened.

(Suresh, Yuta)

Summary:
  We need MC to be locked and aligned well to align other in-vac optics.
  We continued to align the incident beam so that the beam passes the actuation nodes of MC1 and MC3.
  From the previous measurement, we found that beam height at IM1 has to be increased by ~3cm.
  Today, we increased it by ~1cm and achieved about 1/3 of the required correction.
  But we cannot proceed doing this because the beam is hitting IM1 at the edge already.

What is the goal of this alignment?:
  If the beam doesn't hit MC optics in the center, we see angle to length coupling, which is not good for the whole interferometer.
 
  Also, if the beam is tilted so much, transmitted beam though MC3 cannot go into FI at right after MC3.
  Say, FI has an aparture of 3mm and MC3-FT distance is 300mm. The beam tilt should be smaller than 3/300 rad. MC1-MC3 distance is 200mm, so the displacement at each mirror should be smaller than ~1mm.
  1mm is about 7% (see Koji's elog #2863) TO_COIL gain imbalance in A2L measurement.
 
  We are currently assuming that each coils are identical. If they have 5% variance, it is meaningless to try to reduce the beam displacement less than ~5%.

  So, we set the goal to 7%.

What we did:
  1. Leveled the MC table.

  2. Measured the table height using DISTO D3 laser gauge.
    PSL table 0.83m (+-0.01m)
    OMC table 0.82m
    MC table  0.81m

  3. Using the last steering mirror(SM@PSL) and IM1, tilted the beam vertically

Result:


  At t=0 (this morning), the beam tilt was ~40%/(MC1-MC3 distance). Now, it is ~30%/(MC1-MC3 distance).
  30%/(MC1-MC3 distance) is ~5/200 rad.

Plan:
 We have to somehow come up with the next story. Too much vertical tilt. What is wrong? Table leveling seems OK.
 - measure in-vac beam height
 - maybe OSEMs are badly aligned. we have to check that.

It didn't make sense in several points.

1. Is the Faraday aperture really 3mm? The beam has the gaussian radius of ~1.5mm. How can it be possible to go through the 3mm aperture?

2. Why the MC3-FT distance is the matter? We have the steering mirror after MC3. So we can hit the center of the Faraday.
But if we have VERTICAL TILT of the beam, we can not hit the center of the Faraday entrance and exit at the same time.
That would yield the requirement.

3. If each coil has 5% variance in the response, variance of the nodal point (measured in % of the coil imbalance) by those four coils will be somewhat better than 5%, isn't it?

1. We didn't measure the aperture size last night. We have to check that.

2. We have to measure the length of FI. Or find a document on this FI.

3. Yes, 5%/sqrt(4). But I didn't think the factor of 2 is important for this kind of estimation.

1. Look at the Faraday.

2. Look at the wiki. There is the optical layout in PNG and PDF.

3. 5% (0.8mm) and 2.5%(0.4mm) sounds a big difference for the difficulty, but if you say so, it is not so different.

Actualy, if you can get to the 5% level, it is easy to get to the 1-2% level as I did last time.
The problem is we are at the 15-20% level and can not improve it.

(Koji, Jenne, Yuta)

We found one of DAC cables had a poor contact.
That probably caused our too much "tilt" of the beam into MC.

Story:
  From the previous A2L measurement and MC aligning, we found that the beam is somehow vertically "tilted" so much.
  We started to check the table leveling and the beam height and they looked reasonable.
  So, we proceeded to check coil balancings using optical levers.
  During the setup of optical levers, I noticed that VMon for MC1_ULCOIL was always showing -0.004 even if I put excitation to coils.
  It was because one of the DAC cables(labeled CAB_1Y4_88) had a poor contact.
  If I push it really hard, it is ok. But maybe we'd better replace the cable.

What caused a poor connection?:
  I don't know.
  A month ago, we checked that they are connected, but things change.

How to prevent it:
  I made a python script that automatically checks if 4 coils are connected or not using C1:IOO_LOCKIN oscillator.
  It is /cvs/cds/caltech/users/yuta/scripts/coilchecker.py.
  It turns off all 3 coils except for the one looking at, and see the difference between oscillation is on and off.
  The difference can be seen by demodulating SUSPOS signal by oscillating frequency.
  If I intentionally unplug CAB_1Y4_88, the result output for MC1 will be;

==RESULTS== (GPS:973512733)
MC1_ULCOIL      0.923853382664 [!]
MC1_URCOIL      38.9361304794
MC1_LRCOIL      55.4927575177
MC1_LLCOIL      45.3428533919

Plan:
 - Make sure the cable connection and do A2L and MC alignment again
 - Even if the cables are ok, it is better to do coil balancings. See the next elog.

(Suresh, Yuta)

Background:
  Previous A2L measurement is based on the assumption that actuator efficiencies are identical for all 4 coils.
  We thought that the unbelievable "tilt" may be caused by imbalance of the coils.

Method:
  1. Setup an optical lever.
  2. Dither the optic by one coil and demodulate oplev outputs(OL_PIT or OL_YAW) in that frequency.
  3. Compare the demodulated amplitude. Ideally, the amplitude is proportional to the coil actuation efficiency.

What we did:
[MC2]
  MC2 is the least important, but the easiest.
  1. Placed a red laser pointer at MC2 trans table. During the installation, I moved the mirror just before QPD.
  2. Made a python script that measures coil actuation efficiency using the above method. I set the driving frequency to 20Hz.
  It is /cvs/cds/caltech/users/yuta/scripts/actuatorefficiency.py.
  The measurement result is as follows. Errors are estimated from the repeated measurement. (Attachment #1)

MC2_ULCOIL 1
MC2_URCOIL 0.953 ± 0.005
MC2_LRCOIL 1.011 ± 0.001
MC2_LLCOIL 0.939 ± 0.006

[MC1]
  For MC1, we can use the main laser and WFS1 QPD as an oplev.
  But we only have slow channels for QPD DC outputs(C1:IOO_WFS1_SEG#_DC).
  So, we intentionally induce RF AM by EOM(see Kiwamu's elog #3888) and use demodulated RF outputs of the WFS1 QPD(C1:IOO_WFS1_I/Q#) to see the displacement.
  1. Replaced HR mirror in the MCREFL path at AP table to BS so that we can use WFS1.(see Koji's elog #3878)
    The one we had before was labeled 10% pick-off, but it was actually an 1% pick-off.
  2. Checked LO going into WFS1 demodulator board(D980233 at 1X2).
    power: 6.4dBm, freq: 29.485MHz
  3. Turned on the hi-voltage(+100V) power supply going into the demodulator boards.
  4. Noticed that no signal is coming into c1ioo fast channels.
    It was because they were not connected to fast ADC board. We have to make a cable and put it in.

[MC3]
  Is there any place to place an oplev?

Plan:
 - prepare c1ioo channels and connections
 - I think we'd better start A2L again than do oplev and coil balancing.

The cause is apparent! The connectors on the cables are wrong!
Currently only 50% of the pin length goes into the connector!

[Koji / Yuta]

There were the guys who used the PENTEK 40pin connectors into the IDC 40pin connectors.
Those connectors are not compatible at all.

==> We replaced the connectors on the cables from DAC to IDC adapters to the dewhitening board for the vertex SUSs.

In addition, I found one of the Binary OUT IDC50pin connector has no clamp.

==> We put the IDC50pin clamp on it.

PENTEK connectors were inserted. The latches are not working!

the vertical pitch is different between PENTEK and IDC!

Wow! Where is the clamp???

[Valera Yuta Kiwamu Koji]

Kiwamu burtrestored c1psl. We measured the power levels around the PMC.

With 2.1A current at the NPRO:

Pincident = 1.56W
Ptrans_main = 1.27W
Ptrans_green_path = .104W

==> Efficiency =88%

----

We limited  the MC incident power to ~50mW. This corresponds to the PMC trans of 0.65V.
(The PMC trans is 1.88V at the full power with the actual power of 132mW)

(Joe, Suresh, Yuta)

Currently, only 2 ADC cards work on c1sus machine.
No QPD inputs(e.g. MC2 trans), and no RFM.

Summary:
  We wanted to have PEM(physical environment montor) channels, so we moved a ADC card in c1sus machine.
  It ended up with destroying one of the 3 ADCs.

What we did:
  1. Moved ADC card at PCIe expansion board slot 0 to other empty slot.
     What we call PCI slot 0 was "DO NOT USE" in LIGO-T10005230-v1, so we moved it.

  2. Connected that ADC card to PEM channel box at 1X7 via SCSI cable.

  3. ADC card order is changed, so we checked ADC number assinging and re-labeled the cable.

  4. Found RFM is not working(c1sus and c1ioo not talking) and fb is in a weird state(Status: 0x4000 in GDS screens)

  5. Swapped the cabling so that ADC card 0 will be connected to timing interface card at slot1, but didn't help.
     More than that, we suffered ADC timeout.

  6. Tried ADC card swapping, slot position changing, taking out some of the ADC cards, etc.
     We found that ADC timeout doesn't happen with 2 ADC cards.
     But if we connect one of the ADC card to the timing interface card at slot 8, c1sus ADC timeouts with 2 ADC cards, too.
     So, I think that timing interface card is bad.

  7. Stopped rebooting c1sus again and again. We decided to investigate the problem tomorrow.
     We only need ADC card 0 and 1 for MC damping.(see this wiki page)
       ADC card 0: all UL/UR/LR/LL SENs
       ADC card 1: all SD SENs     
       ADC card 2: all QPDs

Result:
  We can damp optics and lock MC.
  We can't do A2L because RFM is not working.
  We can't see MC2 trans because we currently don't have ADC card 2.

Summary:
   I set Q-values for each ringdown of PRM, BS, ITMX, ITMY, MC1, MC2, MC3 to ~5 using QAdjuster.py.
   Here are the results;


  Red ringdowns indicate the second try after gain setting.

Note:
  - ITMX and ITMY are referred according to MEDM screens in this entry.
  - ITMX(south) OSEM positions are currently so bad(LL and SD are all the way in/out).
        I have to change IFO_ALIGN slider values to check the damping servo. For SIDE, I couldn't do that. I reverted the slider change after the damping checking.
  - ITMY(west) somehow has opposite coil gain sign.
       Usually for the other optics, UL,UR,LR,LL is 1,-1,1,-1. But for ITMY to damp, they are -1,1,-1,1.
  - PRM damps, but ringdown doesn't look nice. There must be something funny going on.
  - SRM doesn't have OSEMs put in now.

I finished the direct measurement of cable impedances.

Moreover, I wrote the cable replacement plan.

The reason I am checking the cables is for replacing the cables with impedance of 50 or 52 ohm by those with impedance of 75 ohm.

After I figures out which cable has not proper impedance, I will make new cables and substitute them in order to match the impedance, which would lead to better VIDEO signal.

Moreover, as Koji suggested, the VIDEO system will be upgraded for better interface.

I measured the cable impedance by checking the reflection ratio at the point connected to the terminator with 50 ohm or 75 ohm.

The orange colored cables are measured to be 75ohm so we do not need to replace them.

Combining the list of cable types and the list of desired length,

I need to make total 37 cables and to remove 10 cables from the current connection.

Detailed plan is attached below.

I currently ordered additional cables and BNC plugs.

From now on, I will keep making CCD cables for VIDEO upgrade.

Then, with your helps, we will replace the CCD cables.

In my opinion, I will finish VIDEO upgrade by this year.

(Koji, Joe, Yuta)

Motivation:
  We wanted to know more about CDS.

Setup:
  Same as in elog #3829.

What we did:
  1. Made test RT models c1tst and c1nio for c1iscex.
     c1tst has only 2 filter module(minimum limit of a model), 2 inputs, 2 outputs and it runs with IOP c1x01.
     c1nio is the same as c1tst except it runs(or, should run) without IOP.

  2. Measured the time delay of ADC through DAC using different machine, different sampling rate by measuring transfer functions.

  3. c1nio(without IOP) didn't seem to be running correctly and we couldn't measure the TF.
     "1 PPS" error appeared in GDS screen(C1:FEC-39_TIME_ERR).
     It looks like c1nio is receiving the signal as we could see in the MEDM screen, but the signal doesn't come out from the DAC.

TF we expected:
  All the filters and gains are set to 1.

  We have DA's TF when putting 64K signal out to analog world.
    D(f)=exp(-i*pi*f*Ts)*sin(pi*f*Ts)/(pi*f*Ts)  (Ts: sample time)

  We have AA filter and AI filter when downsampling and upsampling.
    A(f)=G*(1+b11/z+b12/z/z)/(1+a11/z+a12/z/z)*(1+b21/z+b22/z/z)/(1+a21/z+a22/z/z)       z=exp(i*2*pi*f*Ts)
  Coefficients can be found in /cvs/cds/rtcds/caltech/c1/core/advLigoRTS/src/fe/controller.c.

/* Coeffs for the 2x downsampling (32K system) filter */
static double feCoeff2x[9] =
        {0.053628649721183,
        -1.25687596603711,    0.57946661417301,    0.00000415782507,    1.00000000000000,
        -0.79382359542546,    0.88797791037820,    1.29081406322442,    1.00000000000000};
/* Coeffs for the 4x downsampling (16K system) filter */
static double feCoeff4x[9] =
    {0.014805052402446, 
    -1.71662585474518,    0.78495484219691,   -1.41346289716898,   0.99893884152400,
    -1.68385964238855,    0.93734519457266,    0.00000127375260,   0.99819981588176};

  For 64K system, we expect H=1.

  We also have a delay.
    S(f)=exp(-i*2*pi*f*dt)   (dt: delay time)

  So, total TF we expect is;
    H(f)=a*A(f)^2*D(f)*S(f)
  a is a constant depending on the range of ADC and DAC(I think). Currently, a=1/4.

  We may need to think about TF when upsampling.(D(f) is TF of upsampling 64K to analog)

Result:
  Example plot is attached.
  For other plots and the raw data, see /cvs/cds/caltech/users/yuta/scripts/CDSdelay2/ directory.
  As you can see, TFs are slightly different from what we expect.
  They show ripple we don't understand at near cut off frequency.

  If we ignore the ripple, here is the result of delay time at each condition;

data file    host    FE    IOP        rate    sample time    delay        delay/Ts
c1rms16K.dat    c1sus      c1rms    adcSlave    16K    61.0usec    110.4usec    1.8
c1scx16K.dat    c1iscex    c1scx    adcSlave    16K    61.0usec     85.5usec    1.4
c1tst16K.dat    c1iscex    c1tst    adcSlave    16K    61.0usec     84.3usec    1.4
c1tst32K.dat    c1iscex    c1tst    adcSlave    32K    30.5usec     53.7usec    1.8
c1tst64K.dat    c1iscex    c1tst    adcSlave    64K    15.3usec     38.4usec    2.5

  The delay time shown above does not include the delay of DA. To include, add 7.6usec(Ts/2).

  - delay time is different for different machine
  - number of filters (c1scx has full of filters for ETMX suspension, c1tst has only 2) doen't seem to effect much to delay time
  - higher the sampling rate, larger the (delay time)/(sample time) ratio

Plan:
 - figure out how to run a model without IOP
 - where do the ripples come from?
 - why we didn't see significant ripple at previous measurement on c1sus?

CDS Objectives for the Week:

Monday/Tuesday:

1) Investigate ETMX SD sensor problems

2) Fully check out the ETMX suspension and get that to a "green" state.

3) Look into cleaning up target directories (merge old target directory into the current target directory) and update all the slow machines for the new code location.

4) Clean up GDS apps directory (create link to opt/apps on all front end machines).

5) Get Rana his SENSOR, PERROR, etc channels.

Tuesday/Wednesday:

3) Install LSC IO chassis and necessary cabling/fibers.

4) Get LSC computer talking to its remote IO chassis

Wednesday:

5) If time, connect and start debugging Dolphin connection between LSC and SUS machines

The last time(Friday) I made an arrangement for RF distribution unit.

I am making RF distribution unit for RF upgrade which is designed by Alberto.

To reduce a noise from loose connection,

I tried to make the number of hard connect as much as possible while reducing the number of connection via wire.

This is why I put splitters right next to the front pannel so that the connection between pannel plugs and splitters could be made of hard joints.

I attached the arrangement that I made on the last Friday.

Next time, I will drill the teflon(the supporting plate) for assembly.

Any suggestion would be really appreciated.

 [Joe, Suresh, Kiwamu]

 We will fully install and run the new C1LSC front end machine tomorrow.

And finally it is going to take care of the IOO PZT mirrors as well as LSC codes. 

 (background stroy)

 During the in-vac work today, we tried to energize and adjust the PZT mirrors to their midpoints.

However it turned out that C1ASC, which controls the voltage applying on the PZT mirrors, were not running.

We tried rebooting C1ASC by keying the crate but it didn't come back.

 The error message we got in telnet  was :

   memory init failure !!

 We discussed how to control the PZT mirrors from point of view of both short term and long term operation.

We decided to quit using C1ASC and use new C1LSC instead.

A good thing of this action is that, this work will bring the CDS closer to the final configuration. 

(things to do)

 - move C1LSC to the proper rack (1X4).

 - pull out the stuff associated with C1ASC from the 1Y3 rack.

 - install an IO chasis to the 1Y3 rack.

- string a fiber from C1LSC to the IO chasis.

- timing cable (?)

- configure C1LSC for Gentoo

- run a simple model to check the health

- build a model for controlling the PZT mirrors

The last time(Moonday) Jenne and I worked on the RF distribution unit's structure.

We are making RF distribution unit for RF upgrade which is designed by Alberto.

Rana, Koji, Jenne suggested a better design for RF Distribution unit.

So Jenne and I gathered information of parts and decided what parts will be used with specific numbers.

Specific circuit is shown in the attached picture.

Any suggestion would be really appreciated.

Looks like there was a power outage. The control room workstations were all off (except for op440m). Rosalba and the projector's computer came back, but rossa and allegra are not lighting up their monitors.

linux1 and nodus and fb all appear to be on and answering their pings.

I'm going to leave it like this for the morning crew. If it

The monitors for allegra and rossa's seemed to be in a weird state after the power outage.  I turned allegra and rossa on, but didn't see anything.  However, I was after awhile able to ssh in.  Power cycling the monitors did apparently got them talking with the computers again and displaying.

I had to power cycle the c1sus and c1iscex machines (they probably booted faster than linux1 and the fb machines, and thus didn't see their root and /cvs/cds directories).  All the front ends seem to be working normally and we have damped optics.

The slow crates look to be working, such as c1psl, c1iool0, c1auxex and so forth.

Kiwamu turned the main laser back on.

I checked the vacuum system and judged there is no apparent issue.

The chambers and annulus had been vented before the power failure.
So the matters are only on the TMPs.

TP1 showed the "Low Input Voltage" failure. I reset the error and the turbine was lift up and left not rotating.
TP2 and TP3 seem rotating at 50KRPM and the each lines show low pressur (~1e-7)
although I did not find the actual TP2/TP3 themselves.

I found that a few connections in the simulink model of c1scx was incorrect, so I fixed them correctly.

It had been a mystery why we had to put a funny matrix on ETMX (see this entry).

But now we don't have to do such a voodoo magic because the problem was solved.

Now the damping of ETMX is happily running with an ordinary output matrix.

 --(details)

 I looked at the wiring diagram of the ETMX suspension (it's on Ben's web page) and confirmed that the coils are arranged in order of UL, LL, UR, LR.

But then I realized that in our simulink model they had been arranged in order of UL, UR, LL, LR.

So UR and LL had been swapped incorrectly !

So I just disconnected and plugged them into the right outputs in the simulink model.

   I rebooted c1iscex in order to reactivate c1scx front end code.

After rebooting it, I changed the output matrix to the usual one, then everything looked okay.

(actually it's been okay because of the combination of the wrong connections and the funny matrix).

What else?

v: Edit on Dec 15 10PM
v: Edit on Dec 16 10PM


JD:  We should check OSEMs for all optics *after* table leveling.  Some of them (esp. BS and ITMX) are currently close to their limits right now.

KA: Check green alignment.

Take photos of the tables.

Fix the leveling weights


Location    Optics            Action
--------------------------------------------------------------
@ITMX -     v POX             alignment
            v POP1/POP2       alignment
            v Table Leveling

@ITMY -     POY               mirror replacement (45deg->0deg) / alignment
            v SR2-TT          alignment
            v SRM Tower       alignment / EQ-stop release
            v SRM             alignment
            v SRM OSEM
            vvSRM OPLEV (X2)  install (VIS)/ alignment
            v ITMY OPLEV (X2)   install (VIS)/ alignment
            v OM1/OM2         install (DLC 45deg)/ alignment       
            v Table Leveling

@BSC -      v OM3             install (DLC 45deg/ alignment)
            v OM4(PZT)          neutralize, adjustment
            IPPOS steering    alignment
            v BS OPLEV        alignment
            v PRM OPLEV(x2)     alignment
            Beam dumps
            Table Leveling

@IMC -      v REFL              mirror replacement　(45deg->0deg)

@ETMX -     Al foil removal
            Table Leveling

@ETMY -     ETMY damping
            OSEM
            OPLEV
            Al foil removal
            Table Leveling

@OMC -      v OM5(PZT)        neutralize, adjustment

@ITM/ETM -  Mirror Wiping



 [Jenne and Kiwamu]

 We wiped all the test masses with isopropyl alcohol.

They became apparently much cleaner.

(how to)

 At first we prepared the following stuff:

  * syringe

  * isopropyl alcohol 

  * lens papers

  * cleaned scissors

  Then we cut the lens papers into the half by the scissors such that the long side can remain.

This is because that the SOSs have relatively narrow spaces at their optic surfaces for putting a piece of paper. 

   We did vertical and horizontal wiping using the lens paper and appropriate amount of isopropyl alcohol.

Each wiping (vertical and horizontal) requires two or three times trials to appropriately remove dusts.

Amount of isopropyl:

   * vertical 15 [ul]

   * horizontal 10 [ul]

In addition to this, we also used the ionizer gun for blowing big dusts and fiber away from the surface.

(surface inspection)

   Before wiping them, all the test masses had small dusts uniformly distributed on the HR surfaces.

Especially ETMX was quite dirty, many small spots (dusts) were found when we shined the surface with the fiber illuminator.

ETMY was not so bad, only a couple of small dusts were at around the center.  ITMX/Y had several dusts, they were not as dirty as ETMX, but not cleaner than ETMY.

   After we wiped them,  we confirmed no obvious dusts were around the centers of the optics. They looked pretty good !

This was the error today:

GET /40m/ HTTP/1.1
Host: nodus.ligo.caltech.edu:8080
User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.6; en-US; rv:1.9.2.3) Gecko/20100401 Firefox/3.6.3
Accept: text/html,application/xhtml+xml,application/xml;q=0.9,*/*;q=0.8
Accept-Language: en-us,en;q=0.5
Accept-Encoding: gzip,deflate
Accept-Charset: ISO-8859-1,utf-8;q=0.7,*;q=0.7
Keep-Alive: 115
Connection: keep-alive
Referer: http://www.ligo.caltech.edu/~ajw/40m_upgrade.html
Cookie: elmode=threaded; __utma=65601905.411937803.1291369887.1291369887.1291369887.1; __utmz=65601905.1291369887.1.1.utmcsr=(direct)|utmccn=(direct)|utmcmd=(none); SITESERVER=ID=4981c5fd42ae53c9c9e0980f2072be4f

Found exactly the same error messages at the end of the log file.

Since Leo was trying to demo his LIGO Data Listener code, he noticed that there was and NDS2 issue. The NDS2 guy (JZ) noticed that the FrameBuilder had an issue.

We investigated. At 4PM on Dec 31, the GPS timestamp of the frame file names started to be recorded wrong. In fact, it started to give it a file name matching the correct time from 1 year in the past.

So that's our version of the Y2011 bug. Here's the 'ls' of /frames/full:

drwxr-xr-x 2 controls controls 252K Dec 26 03:59 9773
drwxr-xr-x 2 controls controls 260K Dec 27 07:46 9774
drwxr-xr-x 2 controls controls 256K Dec 28 11:33 9775
drwxr-xr-x 2 controls controls 252K Dec 29 15:19 9776
drwxr-xr-x 2 controls controls 244K Dec 30 19:06 9777
drwxr-xr-x 2 controls controls 188K Dec 31 16:00 9778
drwxr-xr-x 2 controls controls 148K Jan  1 08:53 9463
drwxr-xr-x 2 controls controls 260K Jan  2 12:39 9464
drwxr-xr-x 2 controls controls 252K Jan  3 16:26 9465
drwxr-xr-x 2 controls controls 248K Jan  4 20:13 9466
drwxr-xr-x 2 controls controls  36K Jan  5 00:22 9467
controls@fb /frames/full $

The culprit is the directory who's name starts out as 9463 whereas it should be 9779.

Email from Alex:

Turned out to be the lack of current year information in the IRIG-B signal
received by the Symmetricom GPS card in the frame builder machine caused
this. I have added a constant in daqdrc to bring the seconds forward:

controls@fb /opt/rtcds/caltech/c1/target/fb $ grep symm daqdrc
#set symm_gps_offset=-1;
set symm_gps_offset=31536001;

Hopefully we will be upgrading to the newer timing system at the 40M this
year, so this will not happen again next year.

Doing an 'ls -lrt' in /frames/full/ now shows that the names are correct:

drwxr-xr-x 2 controls controls 249856 Dec 30 19:06 9777
drwxr-xr-x 2 controls controls 192512 Dec 31 16:00 9778
drwxr-xr-x 2 controls controls 151552 Jan  1 08:53 9463
drwxr-xr-x 2 controls controls 266240 Jan  2 12:39 9464
drwxr-xr-x 2 controls controls 258048 Jan  3 16:26 9465
drwxr-xr-x 2 controls controls 253952 Jan  4 20:13 9466
drwxr-xr-x 2 controls controls 151552 Jan  5 13:54 9467
drwxr-xr-x 2 controls controls  12288 Jan  5 15:57 9783

This is a connection diagram for the input PZTs (i.e. PZT1 and PZT2).

As drawn in the diagram, the signals don't go through the anti-imaging filter D000186 in the current configuration.

Just a proof that the DAQ is working - ran DTT on nodus from 3 hours ago.

Lacking a better place, I've chosen the cabinet down the Y arm which had ethernet cables and various VME cards as a location to store some spare CDS computer equipment, such as harddrives.  I've added (or will add in 5 minutes) a label "FE COMPUTER HARD DRIVES" to this cabinet.

Today I have made the CCD Cable Upgrade Plan for improvement of sysmtem.

I have ~60 VIDEO cables to be worked for upgrades so I would like to ask all of your favor in helping me of replacing cables.

1. Background

Currently, VIDEO system is not working as we desire.

About 20 cables are of impedance of 50 or 52 ohm which is not matched with the whole VIDEO system.

Moreover, some cameras and monitors are out of connection.

2. What I have worked so far.

I have checked impedance of all cables so I figured out which cables can be used or should be replaced.

I measured cables' pathes along the side tray so that we can share which cable is installed along which path.

I have made almost of cables necessary for VIDEO system upgrades but no label is attached so far.

3. Upgrade plan (More details are shown in attached file)

4. This is a kind of  a first draft of the plan.

Any comment for the better plan is always welcome.

Moreover, replacing all the cables indicated in the files is of great amount of work.

I would like to ask all of your favors in helping me to replace the cables (from 1. to 2D. steps above).

I found this old plot in an old elog entry of Osamu's (original link).

It gives us the differential displacement noise of the arms. This was made several months after we discovered how the STACIS made the low frequency noise bad, so I believe it is useful to use this to estimate the displacement noise of the arm cavity today. There are no significant seismic changes. The change of the suspension and the damping electronics may produce some changes around 1 Hz, but these will be dwarfed by the non-stationarity of the seismic noise.

Joe and I built a very simple digital frequency to amplitude converter using the RCG. The input from an ADC channel goes through a filter bank (INPUT), is rectified and then split in two. One path is delayed by one DAQ cycle (1/16384 s) and then the two paths are multiplied together. Then the output from the mixer goes through a second filter bank (LP) where we can strip off twice the beat frequency. The DC output from the LP filter bank should be proportional to the input frequency.

Input Channel: C1:GFD-INPUT_xxx

Output Channel: C1:GFD-LP_xxx

Joe compiled the code and we tested it by injecting a swept sine [100, 500]Hz in the input filter bank. We confirmed that output of the LP filter bank changed linearly as a function of the input frequency.

The next thing we need to do is add a DAC output. Once that's in place we should inject the output from a 4kHz VCO into the ADC. Then we can measure the transfer function of the loop with an SR785 (driving the VCO input and looking at the output of the DAC) and play around with the LP filter to make sure the loop is fast enough.

The model is to be found here:

/opt/rtcds/caltech/c1/core/advLigoRTS/src/epics/simLink/c1gfd.mdl

The attached figures show the model file in Simulink and a realtime dataviewer session with injecting a swept sine (from 500Hz to 100Hz) into the INPUT EXC channel. We've had some frame builder issues so the excitation was not showing on the green trace and, for some reason, the names of the channels are back to front in dataviewer (WTF?), - the lower red trace in dataviewer is actually displaying C1:GFD-LP_OUT_DAQ, but it says it is displaying C1:GFD-INPUT_OUT_DAQ - which is very screwy.

However, the basic principle (frequency to amplitude) seems to work.

That's some pretty fast work! I thought we would be taking up to a week to get that happening. I wonder what's the right way to measure the inherent frequency noise of this thing?

Also, should the comparator part have some hysteresis (ala Schmidt trigger) or is it best to just let it twirl as is? Is it sensitive to DC offsets on the input or is there a high pass filter? What's the correct low pass filter to use here so that we can have a low phase lag feedback to the ETM?

We could try inputing a 4kHz carrier modulated width a depth of a few Hz at a modulation frequency of F1. Then we could take an FFT of the output of the discriminator and measure the width of the peak at F1 Hz. This seems like an arduous way to measure the frequency noise at a single frequency though.

It'll definitely be sensitive to DC offsets but there is already a filter bank on the INPUT filter so we can shape that as necessary. We could probably band-pass that from [4.5 - 5.3kHz] (which would correspond to a range of [73,87] MHz into a 2^14 frequency divider.

 One more thing ... we can calibrate the output of the LP filter to give a result in Hz with the following calibration:

LP_OUT = -1/(2*dt)*(LP_IN -1), where dt is 1/16384, the delay time of the delayed path.

Therefore LP_OUT = -8192*(LP_IN-1).

I've had a go at trying to estimate the frequency noise of the digital frequency discriminator (DFD). I input a 234.5Hz (0.5Vpp) signal from a 30MHz function generator into the ADC. The LP output of the DFD measured 234.5Hz. However, this signal is clearly modulated by roughly +/- 0.2Hz at harmonics of 234.5Hz (as you can see in the top plot in the dataviewer screenshot below). So the frequency noise can be estimated as rms of approximately 0.2Hz.

This is supported by taking the spectra of the LP output and looking at the RMS. Most of the power in the RMS frequency noise (above the minimum frequency) comes from the harmonics of the input signal and the RMS is approximately 0.2Hz.

I believe this stems from the rather basic LP filter (three or four poles around 10Hz?) that is used in the LP filter to remove the higher frequency components that exist after the mixing stage. (The currently loaded LPF filter is not the same as the saved one in Foton - and that one won't load at the moment, so I'm forced to remember the shape of the current filter).

 The attached screen capture from data viewer shows the LP_OUT hovering around 234.5Hz.

A prototype freq divider has been made which works up to ~40MHz.

74HC4060 (14bit binary ripple counter) divides the freq of the input signal, which is comverted by the comparator LT1016
into the rectangular signal. The division rate is 2^14.

Attachment1: Circuit diagram

Attachment2: Photo, the prototype bread board

Attachment3: Photo, the spectrum of the freq divided output. The 40MHz input has been divided into 2.4k.
There are the 3rd and 5th harmonics seen. The peak was pretty sharp but the phase noise was not evaluated yet.

The circuit was made on the prototype bread board which is apparently unsuitable for RF purposes.
Indeed, it was surprising to see its working up to 40MHz...

In order to increase the maximum freq of the system we need the following considerations

• RF PCB board
• Input RF buffer (or amplifier) with a 50Ohm input impedance.
• Faster comparator. LT1016 has the response time of 10ns, which is not enough fast.
• Faster counter. Faster chip 74HC4020 has already been ordered.

 Here is the spectrum of the input into the DFD (a 234.5Hz sine wave, 0.5 Vpp) and the spectrum and RMS of the LP output. The linewidth of the input signal is clearly much less than 0.1Hz, where as the RMS noise (above 2mHz) is approximately 0.2Hz and the main contributions are clearly the harmonics of the 234.5Hz signal.

The freq divider was built and installed in the beat detection path.

Attachment 1: Circuit diagram

• Input stage:  Wideband RF amp with DC block at the input and the output. The gain is 10dB typ.
• 2nd stage: Ultra fast comparator AD9696. Note: AD9696 is an obsolete IC and there are only a few extra at Wilson house.
  The output is TTL/CMOS compatible.
• 3rd stage: 14bit binary ripple counter (fmax~100MHz.)

Note: I have added 7805/7905 regulators to the circuit as I could not find -5V supply on the 1X1/2 racks.

Attachment 2: Packaging

• The box is german made Eurocard size box from Techno-Isel Linear Motion http://www.techno-isel.com/lmc/Products/EnclosureProfiles11055.htm
  The box is excellent but I didn't like the fixing bolts as they are self-tapping type. I tapped the thread and used #6-32 screws.
   
• The prototyping board is BPS's (BusBoard Prototype System http://www.busboard.us/)  SP3UT. The card size is 160mm x 100mm.
  The other side is a ground plane and the small holes on the board are through holes to the ground plane.
  This particular card was not easy to use.
   
• The input is SMA. Unfortunately, it is not isolated. The output is an isolated BNC.
   
• The supply voltage of +/-15V is given by the 3pin D-connector. The supply voltages have been obtained from the cross connect of 1X1.

Attachment 3: Input specification

• The input frequency is 10MHz~85MHz. At lower frequency chattering of the comparator against the multiple zero crossing of the (relatively) slow sinusoidal waves.
• The input amplitude. There are no apparent degradation of the freq jitter when the input power was larger than -30dBm.

- The freq divider and Rana's PFD were hooked up to the ADCs. (Attachment 1)
(I leave the analog PFD not explained in this entry.)
For this purpose, the VCO feedback signal has been disconnected and the beat signal was moved from the VCO loop to the analog PFD.

The output level of the splitter was +12dBm and was too high for the freq divider.
So, I had to stupidly add an attenuator of 10dB before the box.

- Gain of the digital PFD LPF

The LPF of the digital PFD had the gain of -4096 to let the output signal indicate the direct frequency reading.

The gain has been changed to -67.108864
such that the output shows the direct reading of the beat freq in the unit of MHz

-4096*2^14/10^6 = -67.108864

- Attachment 2 shows the acquired beat note through the freq divider.
The blue is the beat note between "green locked" and "IR locked only to MC" (i.e. MC vs XARM)
The red is the beat note with the both beam locked to the arm

The freq divider is a bit flaky in some freq region as the divided output sometimes shows freq jumps or the captured at a freq.
I still don't know why it happens. We have to check why this happens.

The freq fluctuation of the beat note has been measured with the following condition

• The IR beam only locked to the MC. The green beam locked to the arm
• Both of the IR and green locked to the x-arm

Calibration
- The output of the freq divider is already calibrated to have the unit of MHz.

- The transfer function between the analog PFD channel and the digital PFD output was measured to be -23dB = 0.7.
  The gain of the XARM-FINE channel was changed to 0.7 such that the output is calibrated in MHz.

Results

- I have not checked the analog noise level of the analog PFD path. We may need more whitening gain (by icreasing the gain of SR560).

- The analog PFD is always better than the digital PFD above 20Hz.

- Both the digital and analog PFD showed good agreement below 20Hz.
  Note the measurement was not simultaneous.

- When the arm is locked with the ETMX being actuated , the fluctuation of the arm length must be stabilized by a huge factor
(~10^5 according to Kiwamu's entry) However, we only could see the stabilization factor of 30.

As this residual is the difference of the freq noise felt by the IR and the green,
this is a real issue to be tackled.

- The RMS fluctuations of the arm with and without the IR beam being locked are 2MHz and 0.1MHz,
which correcponds to the arm length motion of 250nm and 13nm, respectively.
Ed: I had to use 532nm in stead of 1064nm. The correct numbers are 130nm and 7nm.

- Without the IR locked, The typical peak-to-peak fluctuation of the beat freq was 10MHz.

I found that some flakiness of the beat signals comes from the RF components for the beat detection.
They are touching the racks in an indefinite way. If we move the components the output of the analog PFD
goes crazy.

Once Kiwamu is back I will ask him to clean up all of the green setting in an appropriate way.

This diagram shows the setup of the analog Mixer-Frequency Discriminator (MFD).

The idea is similar to the one of the Schnupp Asymmetry for our Michelson interferometers. The signal from the PD (or any signal source for which you want to know the frequency) is split into two legs; one leg is much longer than the other. The two legs are recombined at a mixer/demodulator. The demodulator output varies sinusoidally with the phase difference of two legs, the same as when we try to measure the phase noise of an oscillator, for example. This is the same concept as the digital frequency discriminator that Aidan and Joe put into the GFD FE system recently.

With a ~1m cable length asymmetry, we get 180 deg of phase shift for a ~100 MHz signal (recall that the speed of light in most of our cables is ~2 x 10^8 m/s). The mixer gives a linear output at 50 MHz (and 150 MHz, 250 MHz, etc.).

This single mixer based setup is fine for most everything we do. In order to get even more resolution, one can just use 2 mixers by splitting the signal with a 4-way instead of 2-way mixer. One setup can have a 0.5-1 m asymmetry to have a large range. The other can have a ~10-30m asymmetry to get a comb of linear readouts.

Typically, we will have some kind of weak signal at the photodiode and will use a 20 or 40 dB gain RF amp to get the signal into the mixer. In this case, the mixer output noise will be at the level of tens of nV/rHz. Any usual low noise audio amplifier (SR560 variety) will be enough to read out the signal.

Why the 50 Ohm terminator? If you look at the specs of the BLP-1.9 filter from Mini-Circuits (its the same for almost all of their LP filters) you see that there's ~90 dB of attenuation above ~30 MHz (where our signals 2*f product will show up). If we use an RF input signal of ~0 dBm, this means that we get a high frequency product of -95 dBm (~10 uVrms) which is OK. But the return loss is 0 dB above 5 MHz - this means that all of the high frequency content is reflected back into the mixer! The 50 Ohm terminator is there to absorb the RF signals coming out of the mixer so as to prevent them from going back into the mixer and mixing with the RF/LO signals. The 50 Ohm terminator does attenuate the DC/audio frequency signals we get out of the mixer by a factor of two, but that's OK since we are not limited by the mixer's thermal noise.

Noise Measurement:

To checkout the noise, we used a 6m RG-58 cable in one leg. We used the DS345 signal generator for the source. We adjusted the frequency to (~21 MHz) give a ~zero mean signal at the demod output. The 6m cable makes the demod output's peak-peak swing correspond to ~16 MHz. We then used an SR560, DC coupled, G=1000, low-noise, 2pole low pass at 1 kHz, to get the signal into the ADC.

The attached plot shows the noise. We have caibrated the digital gain in the channel to make the output into units of Hz. The high frequency noise floor is ~0.3 Hz/rHz and the 1/f knee is at 10 Hz. This setup is already good enough for all of the green locking work at the 40m. In order to make this useful for the reference cavity work or the gyro, we will have to use a longer cable and a lower noise audio amplifier.

As can be seen from the plot, the ADC noise is below the measured noise. The noise of the SR560 with the input terminated is shown in grey - the measured noise of the MFD is very close to this. In order to improve the performance, the next step should be to use a longer cable. There's clearly going to be some trade-off between the temperature dependent effects which come with long cables (dphi/dT gets bigger) and trying to use a high gain ~1 nV/rHz amplfier at the mixer output.

Temperature Drift of the long cable:

This 24-hour minute-trend shows the frequency wander as well as the room temperature. This is not proof of a temperature dependence, but if it is then we get ~3 kHz/deg for the sensitivity. If this is actually the cable and not the amplifier, then we'll have to hunt for a lower tempco cable and put it in a box to isolate it.

Here's the reference for the self-reference frequency detection idea. See Figure 2.

http://www.phys.hawaii.edu/~anita/new/papers/militaryHandbook/mixers.pdf

 I did a quick back of the envelope calculation of the expected green phase change on reflection from the aLIGO ITM.

The phase change per nm, K1 = delta phi/delta Lambda, around 532nm is ~1.5 degrees/nm (from the LMA data) [this number is approximately 100x smaller at 1064nm]

I assumed that very small changes in the thickness of the coating appear equivalent to shifting the spectra for reflection/transmission/phase-change-on-reflection up or down by delta lambda, where

delta Lambda/Lambda = delta h/h

where h is the total thickness of the coating and delta h is the change in the thickness of the coating.

Assume that delta h/h = alpha deltaT, where alpha is the coefficient of thermal expansion and delta T is the change in temperature. (approximately 1K)

Then delta phi = K1* Lambda * alpha * delta T = 1.5 degrees/nm * 532nm * 10^-5 K^-1 * 1.0 K =  8 * 10^-3 degrees.

Assume that 360 degree phase change corresponds to one FSR.

Therefore, the frequency shift due to temperature change in the coating = 8*10^-3/360 * FSR = 2.2 *10^-5 * FSR.

Therefore, the expected frequency shift per degree temperature change = 2.2*10^-5 * FSR [Hz/K]

All of the SUS used to have only 1 filter module for SIDE. They now have 3 filter modules for SIDE just like the other DOFs.

Today I moved the filters around so that the sensor filters are in SDSEN, the servo filters are in SUSSIDE, and the dewhitening for the coil is in SDCOIL.

I noticed along the way that the bounce/roll mode notches for all of the suspensions are still set for the frequencies of the previous suspensions. Suresh has 'volunteered' to find the new frequencies and make the new bandstop filters by looking up the seminal work on this by Dan Busby / Sam Waldman.