[C1:PEM-ACC_MC1_X]
chnnum=15014
gain = 10

etc.

P_carrier   J_0(Gamma)^2 
--------- = ------------
P_SB        J_1(Gamma)^2

   f (MHz) |  before filter (dBm) | after filter (dBm)
   ---------------------------------------------------
     21.5  |       -12.8               -13.1       
     43            -24                 -46
     64.5          -50               < -80
     86            -64               < -80

• LC-LC 4th order low pass filter
  
• Replace the AD797 (U2) with an OP27. AD797's are bad - do not use them anywhere for any reason. The OP27 is slower and has a 3x worse input noise but doesn't compromise the bandwidth or noise performance of the PMC by any significant amount. The rule is: use OP27 everywhere unless you have a very good reason why not.
  
• There is no 'H1' jumper on board. R9 is 90.9 Ohms and R2=900 Ohms so that the U2 stage has a gain of 10.
  
• Cut a trace and inserted a 500 Ohm resistor between U2-pin6 and U5A-pin2 (the AD602). The AD602 has a 100 Ohm input impedance which cannot be driven without limiting by the AD797 or the OP27. The 500 Ohm resistor makes it a driveable load for low level signals which is all that should be there since its the error point of the servo. it also becomes a 6:1 voltage divider. Since the AD602 has a fixed output voltage noise of 100 nV/rHz, this will limit the noise performance if the VGA gain is less than 20 dB, but whatever.
  
• R11 7.87k -> 1.74k, R12 = 78.7k -> 700k. This increases the high frequency gain of that stage by 7.87/1.74 = 4.5 and lowers the low frequency pole from 2 to 0.2 Hz to give the PMC some more staying power at DC. The loop shape is now 1/f^2 in the 9-480 Hz band and so the phase dips enough to make it almost conditionally stable, but not quite.
  
• C26 changed from ??? + a 30 pF trim cap into a fixed NNN pF cap to set the notch frequency for the 14.5 kHz body mode that we measured. Once our brick configuration is more settled we can increase the Q of this notch from small to big.
  
• Grounded pin 5 of U14 & U15 (AD620). These have sometimes been used as "differential" drivers in LIGO by connecting this reference voltage pin to the remote ground of the next board. This has always lead to insidious oscillation and noise. This beauty also has an output noise of 100 nV/rHz. Just never use this chip if you can help it; we can make true differential drivers - we have the technology.
  

I've been measuring a bunch of transfer functions of the FSS related stuffs.
There are a lot to be analyzed yet, but here I put one mystery I'm having now.
Maybe I'm missing something stupid, so your suggestions are welcome.

Here is a conceptual diagram of the FSS control board

                                                          TP3             TP4
                                                           ^               ^
                                                           |               |
RF PD -->--[Mixer]-----[Sum Amp]------>--[Common Gain]--->----[Fast Gain]----[Filter]--> NPRO PZT
              ^     |      ^        |                  |     
              |     V      |        V                  |
LO ---->-------    TP1     IN      TP2                 -->---[Filter]--[High Volt. Amp.] --> Phase Corrector

What I did was first to measure a "normal" openloop transfer function of the FSS servo.
The FSS was operated in the normal gain settings, and a signal was injected from "IN" port.
The open loop gain was measured by TP1/TP2.
Now, I disconnected the BNC cable going to the phase corrector to disable the PC path and locked the ref. cav. 
only using the PZT. This was done by reducing the "Common Gain" and "Fast Gain" by some 80dB.
Then I measured the open loop gain of this configuration. The UGF in this case was about 10kHz.
I also measured the gain difference between the "normal" and "PZT only" configurations by injecting 
a signal from "IN" and measuring TP3/TP2 and TP4/TP3 with both configurations (The signal from the Mixer was
disconnected in this measurement). 

The first attachment shows the normal open loop gain (purple) and the PZT only open loop gain scaled by the 
gain difference (about 80dB). The scaled PZT open loop gain should represent the open loop gain of the PZT
path in the normal configuration. So I expected that, at low frequencies, the scaled PZT loop TF overlaps the normal
open loop TF.
However, it is actually much larger than the normal open loop gain.
When I scale the PZT only TF by -30dB, it looks like the attachment #2.
The PZT loop gain and the total open loop gain match nicely between 20kHz and 70kHz.
Closer look will show you that small structures (e.g. around 30kHz and 200kHz) of the two
TFs also overlap very well. I repeated measurements many times and those small structures are always there (the phase is
also consistently the same). So these are not random noise.

I don't know where this 30dB discrepancy comes from. Is it the PC path eating the PZT gain ?

I have measured many other TFs. I'm analyzing these.
Here is the TO DO list:

* Cavity response plot from AOM excitation measurements.
* Cavity optical gain plot.
* Reconstruct the open loop gain from the electric gain measurements and the optical gain above.
* Using a mixer and SR560(s), make a separate feedback circuit for the PZT lock. Then use the PC path
  to measure the PC path response.
* See the response of the FSS board to large impulse/step inputs to find the cause of the PC path craziness.
etc ...

PMC_cal (m/V) = (1064 nm)/2 / V_FSR

[1] RESET the RFM switches near the FB racks.
[2] Power cycle c1dcuepics.
[3] Power cycle all other crates with real time CPUs:
c1iscey, daqctrl, daqawg, c1susvme1, c1susvme2, c1sosvme, c1iovme, c1lsc, c1asc, & c1iscex
[4] Start up all FEs as described in Wiki.
[5] Burt restore everyone (losepics, iscepics, assepics, omcepics?)

• Find out why there is still 35 MHz signal at the error point. Order some low pass filters to cut off above 35 MHz.
  
• Explore brick + no-brick loop shapes and error spectra.
  
• Measure and set the OLG.