Koji, Manasa, Jenne, Jamie, Bob and Steve
Access connector removed this morning and work has began in the IOO chamber. BE WARE OF ANTS !
Manasa, Eric, Evan, Koji and Steve,
Access connector removed in order to complete alignment. Light aluminum with acetate windows AC installed.
Prior to the access connector removal, Manasa and I aligned the IFO mirrors.
The arms were locked and aligned by ASS.
ETMY sus damping was disabled. Green locking laser and associated electronics turned off. Computers and power supplies turned off at rack 1Y4
The electricians picking up ac power from 1Y4 manual disconnect box and installing conduit line to ISCT-ETMY east end optical table.
There will be no more daisy chaining this way.
The power is back on at ETMY . c1iscey has not been restarted.
Now I'm turning ac power off at ETMX for the same job to be done.
I was notified by CIT Utilities that there was a power surge or short power outage this after noon.
Lab conditions are normal: c1ioo is down. The south arm AC was off......I turned it back on.
CALIFORNIA INSTITUTE OF TECHNOLOGY
UTILITY & SERVICE INTERRUPTION
Date: Saturday, June 23, 2012
Time: 3:46 P.M.
Interruption: Electrical Power Disturbance
Contact: Tom Brennan, x-625-395-4984
*The City of Pasadena Water & Power Department had a 34,000-volt line event on Saturday June 23 at 3:46 p.m. This caused a city wide disturbance on the power grid. The Campus did not lose electrical power. However, the disturbance may have affected sensitive electronic equipment.
(If there is a problem with this Interruption, please notify the Service Center X-4717 or the above Contact as soon as possible.
If no response is received we will proceed with the interruption.)
Interim Director of Campus Operations & Maintenance
The power was turned back on at 4pm It took some time for Suresh to restart the computers. We have damping but things are not perfect yet. Auto BURTH did not work well.
Koji and I wanted to turn off the IFO-room AC so the wind would not blow on MC1-3. We could not. The switches were probably bypassed when the power transformer was replaced at the last scheduled power outage.
There is one three position manual/off/auto switch next to the filter for each unit at CES. They have to be in AUTO position when we want to turn AC on/off from the lab.
I turned it back on, maybe around 11am? Definitely a little while before the 12:30 meeting.
EDIT by KI:
Sorry, it's me. I was checking if AC was doing something bad on the ALS noise.
** The notation here is [UL, UR, LR, LL]
you asked for: diff 2008/09/25,0:00 2008/09/25,8:50:19 utc 'FSS[-_]SLOW'
LIGO controls: differences, 2008 09/25 00:00:00 utc vs. 2008 09/25 08:50:19 utc
__Epics_Channel_Name______ __Description__________ __value1____ __value2____
C1:PSL-FSS_SLOWKD 0.000000 0.001000
C1:PSL-FSS_SLOWKI -0.001000 -0.001700
C1:PSL-FSS_SLOWKP -0.000300 -0.001000
In this past weekend the ABSL laser was successfully frequency-locked to the PSL laser with a frequency offset of about 100 MHz.
In the current setup a mixer-based frequency discriminator is used for detection of the beat-note frequency.
Setup for frequency locking
The diagram below shows the setup for the frequency locking.
The shutter of the ABSL laser is closed for the vent work.
I found that the ref cav trans CCD view was blinking with 30-50 fringe amplitudes. This meant the laser freq was swinging ~50GHz.
I checked the ABSL laser and the SG out of a lock-in amplifier was connected to the slow input.
This was shaking the laser temp from 29degC to 46degC. This was the cause of the fringe swinging.
This big excitation changing the output power too as the temp was changed across it mode-hop region.
I have disconnected the excitation from the laser no matter how useful experiments were took place as there was no e-log entry about this.
I need the explanations
1. Why our precious laser is exposed to such a large swing of temperature?
2. Why the excitation is left like that without any attendance?
3. Why there was no elogging about this activity?
Hmm. Should have only been +/- 1 GHz. Some setting got changed apparently...
This is a part of the RefCav temperature measurement setup. You'll get an elog from Jenny very soon.
According the plan, I started to use the IR beam dumped after the doubling crystal for the IR beat lock (Sonali's project). The beat lock was disturbed when I shifted some clamps to make way for a few mirrors. So I set about fixing the beat lock. I reobtained the lock but noticed that the net beam power reaching the Newfocus 1611 detector was around 15mW. 10mW from the ABSL and 5mW from PSL.
I therefore started to adjust the power levels by using Y1-1064-45S mirrors at non-45 deg angles. However Rana pointed out that this would lead to amplitude noise due to the mirror vibrations. I then switched to using beam splitters as pick offs. This is better than using neutral density filters since the back scatter is lower this way.
David wanted some of the ABSL beam for his SURF student. So I changed the mirror after beam expanding telescope on the ABSL route to provide this power. We also installed a pair of half wave plates and a PBS to allow us smooth power level control on this beam.
The beat lock setup is now down and needs to be completed for PRCL and SRCL measurements.
What this means:
Of course we'll have to investigate the AA/AI situation as well. I'll try to asses that in a follow up post.
It looks like we have spare channels in the AA chassis for the existing c1ioo ADC inputs to accommodate the POP QPD.
We need AI interfaces for the ALS PZTs. What we ideally need is 3x D000186, which are the eurocard AI boards that have the flat IDC input connects that can come straight from the DAC break-out interfaces. I'm not finding any in the spares in the spare electronics shelves, though. If we can't find any we'll have to make our own AI interfaces.
I have the setup built for the AA/AI board testing around the PD testing area. Please let me leave it like that for a week or so.
12/4 TF Tested 5 PCBs
12/6 TF Tested 19 PCBs (12min/PCB) - found 1 failure (S2001479 CH1) -> Fixed 12/11
12/8 TF Tested 16 PCBs (12min/PCB)
PSD Tested 4 PCBs (11min/PCB)
12/11 TF Tested 10 PCBs + 1 fixed channel (All channels checked)
PSD Tested 10 PCBs (11min/PCB)
12/14 PSD Tested 4 PCBs (6.5min/PCB) fixed noise issue of 2 ch, TF issue of 1 ch
12/15 PSD Tested 32 PCBs (6.5min/PCB) fixed noise issue of 1ch
Temp dependence measurement
Here is the associated filter file:
# SAMPLING ULYAW 16384
# DESIGN ULYAW 0 zpk([0.512+i*1024;0.512-i*1024;2.048+i*2048;2.048-i*2048], \
# [515.838+i*403.653;515.838-i*403.653;318.182+i*623.506;318.182-i*623.506;59.2857+i*827.88; \
# DESIGN ULYAW 1 zpk([0.512513+i*1024;0.512513-i*1024;1.53754+i*2048;1.53754-i*2048], \
# DESIGN ULYAW 2 zpk([0.768769+i*1024;0.768769-i*1024;1.53754+i*2048;1.53754-i*2048], \
ULYAW 0 21 3 0 0 DAQAA 0.00091455950698073 -1.62010355523604 0.67259370084279 -1.84740554170818 0.99961738977942
-1.72089534598832 0.78482029284220 -1.41321371411946 0.99858678588255
-1.85800352005967 0.95626992044093 2.00000000000000 1.00000000000000
ULYAW 1 21 2 0 0 FEAA 0.018236566955641 -1.83622978049494 0.85804776530302 -1.84740518752455 0.99961700649533
-1.89200532023258 0.96649324616546 -1.41346289594856 0.99893883979950
ULYAW 2 21 2 0 0 ELP 0.015203943102927 -1.84117829296043 0.86136943504058 -1.84722827171918 0.99942556512240
-1.89339022414279 0.96048849609619 -1.41346289594856 0.99893883979950
We changed the range of the two SUS AA boards in the corner from +/-2 V to +/-10 V by changing the supply voltage from +/-5 V to +/-15 V. The change was made by switching the AA power feed wires on the cross connect. The max supply according to the spec of DRV134/INA134 is +/-18 V.
We checked the new range by applying the voltage to the input of AA and measuring the output going to the ADCs. The local damping MC1,2,3 appears to work.
Koji and Haixing,
We did a tolerance analysis to specify the conner frequency for passive low-pass filtering in the AA filter of Cymac. The
link to the wiki page for the AA filter goes as follows (one can have a look at the simple schematics):
Basically, we want to add the following passive low-pass filter (boxed) before connecting to the instrumentation amplifier:
Suppose (i) we have 10% error in the capacitor value and (ii) we want to have common-mode rejection
error to be smaller than 0.1% at low frequencies (up to the sampling frequency 64kHz), what would be
conner frequency, or equivalently the values for the capacitor and resistor, for the low-pass filter?
Given the transfer function for this low-pass filter:
and the error propagation equation for its magnitude:
we found that the conner frequency needs to be around 640kHz in order to have
This is sort of OK, except the capacitor connects across the (+) terminals of the two input opamps, and does not connect to ground.
Also, we don't care about the CMRR at 64 kHz. We care about it at up to 10 kHz, but not above. The sample frequency of the ADC is 64 kHz, but all of the models run at 16 kHz or less, so the Nyquist frequency is 8 kHz.
And doesn't the value depend on the resistors?
>> This sort of OK, except the capacitor connects across the (+) terminals of the two input opamps, and does not connect to ground:
>> Also, we don't care about the CMRR at 64 kHz. We care about it at up to 10 kHz, but not above.
In this case, the conner frequency for the low-pass filter would be around 100kHz in order to satisfy the requirement.
>>And doesn't the value depend on the resistors?
Yes, it does. The error in the resistor (typically 0.1%) is much smaller than that of the capacitor (10%). Since the resistor error propagates in the same as the capacitor,
we can ignore it.
Note that we only specify the conner frequency (=1/RC) instead of R and C specifically from the tolerance analysis, we still need to choose appropriate
values for R and C with the conner frequency fixed to be around 100kHz, for which we need to consider the output impedance of port 1 and port 2.
Given this new setup, we realized that the previous tolerance analysis is incorrect. Because the uncertainty in the capacitance value
does not affect the common mode rejection, as two paths share the same capacitor. Now only the imbalance of two resistors is relevant.
The error propagation formula goes as follows:
We require that the common-mode rejection error at low frequency up to 8kHz, namely
with , one can easily find out that the corner frequency needs to be around 24kHz.
Steve pulled the top AA filter box from 1X5 which handled some of the suspensions channels. We turned off all the watchdogs before pulling it out, as well as recorded which cables were connected to which inputs.
The case is undergoing a structural modification to have the ADC adapter card which previously was loosely connected via cables, securely attached to the case.
Steve still wants to do some cabling in the rack while the box is out, and will return it this afternoon once he has finished that.
Job is done. Sus damping are back on. Cabling-strain reliefing are not finished yet at 1X5 and 1X4
Koji fixed the problematic channel - the issue was a bad solder joint on the input resistors to the THS4131. The board was re-installed. I also made a custom 2x4-pin LEMO-->DB9 cable, so we are now recording the PMC and FSS ERR/CTRL channel diagnostics again (spectra tomorrow). Note that Ch32 is recording some sort of DuoTone signal and so is not usable. This is due to a misconfiguration - ADC0 CH31 is the one which is supposed to be reserved for this timing signal, and not ADC1 as we currently have. When we swap the c1ioo hosts, we should fix this issue.
I also did most of the work to make the MEDM screens for the revised ASC topology, tried to mirror the site screens where possible. The overview screen remains to be done. I also loaded the anti-whitening filters (z:p 150:15) at the demodulated WFS input signal entry points. We don't have remote whitening switching capability at this time, so I'll test the switching manually at some point.
The main issue is that in the AA chassis I built, Ch14 (with the first channel as Ch1) has the output saturated to 28V (differential). I'm not sure what kind of overvoltage protection the ADC has - we frequently have the inputs exceed the spec'd +/-20 V (e.g. when the whitening filters are engaged and the cavity is fringing), but pending further investigation, I am removing the SCSI connection from the rear of the AA chassis.
We used a function generator, an oscilloscope and the Data Viewer to check the gain of the new AA board (used for the seismometers). Putting a sine wave of 0.3V (using a function generator) to the AA board, we could see about 500 counts in the Data Viewer. The calibration of the ADC is 214 counts/volt, so the AA board gives to the ADC an output of 0.03V. This proves that the AA board has a gain of 0.1. Guralp1 and STS1 (Bacardi), both have a gain of 10 now, that balance the AAboard gain of 0.1. If we consider the gain of AA board in our calibrated power spectrum plot of seismic signals from Guralp1 and STS1 (Bacardi), we get the following plot:
The AA board shown in attachment 1 will be used in the seismometer hardware setup. A cartoon of this setup is shown in attachment 2.
BNC connectors are required for the seismometer breakout boxes. So the four-pin LEMO connectors present in the AA board were removed and panel mount BNC connectors were soldered to it. Red and blue colored wires were used to connect the BNC connectors to the board. Red wire connects the center of the BNC connector to a point on the board and that connection leads to the third leg (+IN) of the IC U### and the blue wire connects the shield of the BNC connector to the second leg (-IN) of the IC U###.
All the connections (including BNC to the AA board and in the AA board to all the filters) were tested using a multimeter by the beeping method and it was found that channel 10 (marked as C10) had a wrong connection from the point where the red wire (+ve) was connected to the third leg (+IN) of IC U91 and channel 32 (marked as C32) had opposite connections meaning the blue wire is connected to the third leg (+IN) of IC U311 and red wire is connected to the second leg (-IN) of IC U311.
We fixed the anti-aliasing board in its aluminum black box, the box couldn't be covered entirely because of the outgoing wires of the BNC connectors, so we drilled additional holes on the top cover to slide it backwards by 1cm and then screw it.
We had to fix the AA board box in rack 1X7, but there wasn't enough space, so we tried to move the blue chassis (ligo electro-optical fanout chassis 1X7) up with the help of a jack. We removed the blue chassis' screws but we couldn't move it up because of a piece of metal screwed above the blue chassis, then we weren't able to screw the two bottom screws again anymore because it had slided a bit down. Thus, the blue chassis (LIGO ELECTRO-OPTICAL FANOUT CHASSIS 1X7) is still not fixed properly and is sitting on the jack.
To accommodate the AA board (along with the panel-mounted BNC connectors) in rack 1X7 we removed the sliding tray (which was above the CPU) and fixed it there. Now the sliding tray is under the drill press.
But every ~40 min ETMX motion is much higher then ground motion at low frequencies (<5 Hz). I wonder if this a reaction of a table to outside disturbances or accelerometer issue.
This could come from AA board, its range is +/- 2.5 V, RMS of the ETMX table motion is a few times higher then ground motion, so ETMX accelerometer signal was corrupted.
As this small AA range has already caused problems before, I decided to increase it. I've looked through the board scheme and found that all its differential line receives and output amplifiers have absolute maximum range of 40V. We used KEPKO power supply for this board with a voltage range up to 6 V. So I've replaced it with a BK PRECISION power supply and set it to +/- 15 V. Now AA board range is 7.5 V.
I'll leave accelerometers near ETMX table. It's interesting to measure table motion in the morning when trucks drive by.
I'll leave accelerometers near ETMX table. It's interesting to measure table motion in the morning when trucks drive by.
That low frequency effect was due to AA board, now it is gone.
We would like to increase the UGF of the PRC loop so as to allow more suppression of the PRC signal and less pollution of the MICH signal (remember that the PRC/MICH optical gain ratio is huge).
We were already losing phase because of delay in the LSC - SUS digital link. In addition to that, a major source of delay is the analog anti-aliasing (on the LSC error signals before they enter the ADC) and the analog anti-imaging (between the SUS DAC and the coil driver).
IN addition to these, the other major sources of phase lag in the system are the FM5 filter in the LSC-PRC filter bank, the digital upsampling and downsampling filters, and the DAC sample and hold.
In the near term, we want to modify these analog filters to be more appropriate for our 64 kHz ADC/DAC sample rate. Otherwise, we are getting the double phase lag whammy.
Staring at the schematics for the AA (D000076-01) and the AI (D000186-A), we determined a plan of action.
For the AA, we want to remove the multi-pin AA chip filter from Frequency Devices, Inc. and replace it with a passive LC low pass. Hopefully, these chips are socketed. Rana will design an appropriate LC combo and elog; we should make the change on a Wednesday afternoon so that we have enough soldering help.
For the AI, the filter is a dual bi-quad using discrete components and LT1125 opamps. Not so clear what to do with these. The resistors are all the noisy thick film kind and maybe should be replaced. Koji will find some online design tool for these or do it in LISO. Changing the TF is easy; we can just scale the capacitors. But we also want to make sure that the noise of the AI does not destroy the noise reduction action of the dewhitening board which precedes it.
Jenne should figure out how low the noise needs to be at the input to the coil driver.
P.S. the matlab code which defines these filters
>> [z,p,k] = ellip(4,4,60,2*pi*7570,'s');
>> misc.ai = zpk(z,p,k*10^(4/20)) * zpk(,-2*pi*13e3,2*pi*13e3);
>> % Fudged Anti-Imaging Filter
>> [z,p,k] = ellip(8,0.001,80,2*pi*7570,'s');
>> misc.aa = zpk(z,p,k*10^(0.001/20)) * zpk(,-2*pi*32768,2*pi*32768);
To get the angle to length signal before the c1ioo processor gets going, we need a length signal. We can use either the error signal or the control signal.
I recommend using the control signal since its not puny. The 4-pin LEMO inputs to the OSEM ADC that Suresh has wired are differential so we can, in principle, use either the BNC output of the SERVO plug or the 2-pin LEMO output.
The analog whitening on the OSEM Whitening board should be engaged via the SUS MEDM screen so that we get a good SNR at the A2L dither frequencies.
If the ADC saturates, then we should use a pomona box RC low pass to cut everything off above 100 Hz.
Also, a comment about Yuta's elog: we estimated that the seismic motion was ~1e-7 - 1e-6 meters. The MC linewidth ought to be ~lambda/(2*Finesse) ~ 1e-9.
So, the MC servo as it was was not giving us enough gain (1/f above 50 Hz; UGF ~5-10 kHz) to get the error signal to stay in the linear PDH region. Kevin's filter gave us ~10x more gain at the seismic frequencies (1-3 Hz) of concern.
Here’s a quick summary of the Tip-Tilt Design updates (all files are in the dropbox in [TipTiltSus>TT_New]) that I have been working on with Koji and Steve's help.
1. Plate on top to hold mirror in place:
The plate is 0.5 mm thick. I did a rough FEA with 10 N force on the point of pressure on it, and it bent easily.
2. Weighted screw rod at the bottom for tilting the mirror-holder:
I did a very simplified free body analysis to calculate the required length of the rod to achieve a +/- 15 mRad tilt, and got around 1.5 inches.
3. Set-screws on both side of wire clamp to adjust its horizontal position:
1. Used the same screw size in most places to reduce complexity.
2. The mirror holder I have worked on is a little different from the actual piece I have on my table. Which one do you prefer (Koji)?
> 2. Weighted screw rod at the bottom for tilting the mirror-holder:
Too long. The design of the holder should be check with the entire assembly.
We should be able to make it compact if we heavier weights.
How are these weights fixed on the shaft?
Also can we have options for smaller weights for the case we don't need such a range?
Note the mass of the weights.
> 3. Set-screws on both side of wire clamp to adjust its horizontal position:
How much is the range of the clamp motion limited by the slot for the side screws and the slot for the protrusion? Are they matched?
Can you show us the design of the slot made on the mirror holder?
Where is the center of mass (CoM) for the entire mirror holder assy and how much is the height gap between the CoM and the wire release points. Can you do this with 3/8" and 1/2" fused silica mirrors?
Trawling through some past elogs, I saw that the ALS noise increase as a function of CARM offset reduction is not really a new thing (see e.g. this elog). In the past, when we were able to lock, when the CARM offset is reduced to zero, the arms would "buzz" through resonance. It just wasn't clear to me how much the buzzing was - in all the plots we presented, we were not looking at the fast 16k output, so it looked like the arm powers had stabilized. But today, looking at the frame data at 16k from back in 2016, it is clear to me that the arm transmission was in fact swinging all the way from 0 to some maximum. Once the IR signal (=REFL11) blending is turned on, we were able to stabilize the arm power somewhat. What this means is that we are in a comparable state as to when we were able to lock in the past (since I'm able to sit at 0 CARM offset with the PRMI locked almost indefinitely).
So, I think what I'll try for the next 3 days is to get this blending going, I think I couldn't enable the CM_slow path because when I was experimenting with the high bandwidth Y arm cavity locking, I had increased the whitening gain of this channel, but REFL11 has much more optical gain (=larger signal) than POY11, and so I'll start from 0dB whitening gain and see if I can turn the magic integrator on. Long term, we should try and compensate the optomechanical plant that changes as our CARM offset gets reduced, as this would further reduce the lock acquisition time and simplify the procedure (no need to fiddle with the integrator, offsets etc). A relevant thread from the past.
I made a noise budget for the ALS noise measurement that I did a week ago (see #4352).
I am going to post some details about this plot later because I am now too sleepy.
Over the last couple of days, I've been working towards getting the infrastructure ready to test out the scheme of sensing (and eventually, controlling) the homodyne phase using the so-called RF44 scheme. More details will be populated, just quick notes for now before I forget.