| ID |
Date |
Author |
Type |
Category |
Subject |
Text |
 |
|
5549
|
Mon Sep 26 17:49:51 2011 |
Koji | Update | PSL | c1psl | [Koji Suresh]
c1psl has got frozen during our ezcaread/write
business. |
|
|
15238
|
Mon Mar 2 16:29:40 2020 |
gautam | Update | Electronics | c1psl VME crate removed, Acro-crate installed | [JV, JWR, YD, GV]
The old c1psl VME crate,
and all the ribbon cables connected to it |
|
|
15194
|
Thu Feb 6 21:54:13 2020 |
Jon | Update | PSL | c1psl bench testing complete | Today I engineered the last piece
of the new c1psl system: the multi-bit
binary output (mbbo) channels that control |
|
|
12852
|
Fri Feb 24 20:38:01 2017 |
johannes | Update | Computers | c1psl boot-stall culprit identified | [Gautam, Johannes]
c1psl finally booted up again,
PMC and IMC are locked. |
|
|
15150
|
Thu Jan 23 23:07:04 2020 |
Jon | Configuration | PSL | c1psl breakout board wiring | To facilitate wiring the c1psl chassis
and scripting loopback tests, I've
compiled a distilled spreadsheet with the |
|
|
15117
|
Mon Jan 13 15:47:37 2020 |
shruti | Configuration | Computer Scripts / Programs | c1psl burt restore | [Yehonathan, Jon, Shruti]
Since the PMC would not lock, we
initially burt-restored the c1psl machine |
|
|
13742
|
Mon Apr 9 23:28:49 2018 |
johannes | Configuration | DAQ | c1psl channel list | I made a list of all the physical c1psl
channels to get a better idea for how many
acromags we need to replace it eventually. |
|
|
15253
|
Wed Mar 4 22:38:31 2020 |
Jon | Update | PSL | c1psl communications problem resolved | I investigated the problem
reported earlier today with the BIO1 channels.
By logging the systemd messages generated |
|
|
14817
|
Tue Jul 30 09:13:31 2019 |
gautam | Update | PSL | c1psl keyed, Agilent setup cleared |
IMC would not lock. c1psl EPICS
channels were unresponsive. I keyed the crate
and went through the usual burtrestore/PMC-relocking |
|
|
15184
|
Mon Feb 3 15:22:39 2020 |
Jon | Update | PSL | c1psl progress/Acromag ADC grounding | I tested the c1psl AO channels on the electronics
bench on Friday. While I found all the wiring
to be correct, some of the channels exhibited |
|
|
15115
|
Fri Jan 10 14:21:19 2020 |
Yehonathan | Update | PSL | c1psl reboot | PSL controls on the sitemap went blank.
Rebooted c1psl. PSL screens seem normal again. |
|
|
1976
|
Tue Sep 8 19:30:33 2009 |
rana | Update | PSL | c1psl rebooted for new RCPID database settings | The RC thermal PID is now controllable
from its own MEDM screen which is reachable
from the FSS screen. The slowpid.db and |
|
|
1983
|
Thu Sep 10 18:25:15 2009 |
rana | Update | PSL | c1psl rebooted for new RCPID database settings | I added a new database record (C1:PSL-FSS_RCPID_SETPOINT)
to allow for changing of the RC setpoint
while the loop is on. This will enable us |
|
|
15231
|
Thu Feb 27 17:50:36 2020 |
gautam | Update | PSL | c1psl setup setup | [many people]
in prep for the install tomorrow,
we did the following: |
|
|
15234
|
Fri Feb 28 08:05:22 2020 |
gautam | Update | PSL | c1psl setup setup | And so it begins.
|
|
|
15235
|
Fri Feb 28 10:04:41 2020 |
gautam | Update | PSL | c1psl setup setup | Summary:
There are several problems evident
already. |
|
|
17727
|
Thu Jul 27 17:03:57 2023 |
Koji | Summary | CDS | c1psl spare channel situation | I looked at the Acromag situation
of c1psl to prepare for the PSL air flow
speed sensor. |
|
|
15239
|
Mon Mar 2 16:35:12 2020 |
gautam | Update | CDS | c1psl test status | Channel |
|
|
12849
|
Thu Feb 23 15:48:43 2017 |
johannes | Update | Computers | c1psl un-bootable | Using the PDA520 detector on the AS port
I tried to get some better estimates for
the round-trip loss in both arms. While setting |
|
|
12850
|
Thu Feb 23 18:52:53 2017 |
rana | Update | Computers | c1psl un-bootable | The fringes seen on the oscope are mostly
likely due to the interference from multiple
light beams. If there are laser beams hitting |
|
|
12851
|
Thu Feb 23 19:44:48 2017 |
johannes | Update | Computers | c1psl un-bootable | Yes, that was one of the things that I
wanted to look into. One thing Gautam and
I did that I didn't mention was to reconnect |
|
|
12854
|
Tue Feb 28 01:28:52 2017 |
johannes | Update | Computers | c1psl un-bootable | It turned out the 'ringing' was
caused by the respective other ETM still
being aligned. For these reflection measurements |
|
|
14455
|
Thu Feb 14 23:14:12 2019 |
gautam | Update | CDS | c1rfm errors | The pressure is still 2e-4 torr according
to CC1 so I thought I'd give ASS debugging
a go tonight. But the arm transmission signal |
|
|
15240
|
Mon Mar 2 19:32:41 2020 |
gautam | Update | CDS | c1rfm errors | Had to reboot both end machines and the
c1rfm model to get the TRX and TRY signals
to the LSC models. Now both arms can be locked |
|
|
14457
|
Fri Feb 15 15:22:08 2019 |
gautam | Update | CDS | c1rfm errors persist | I restarted c1scy,
|
|
|
15920
|
Mon Mar 15 20:22:01 2021 |
gautam | Update | ASC | c1rfm model restarted | On Friday, I felt that the ASC performance
when the PRFPMI was locked was not as good
as it used to be, so I looked into the situation |
|
|
11883
|
Tue Dec 15 11:22:53 2015 |
gautam | Update | CDS | c1scx and c1asx crashed | I noticed what I thought was excessive
movement of the beam spot on ITMX and
ETMX on the control room monitors, and when |
|
|
7008
|
Mon Jul 23 18:57:52 2012 |
Jamie | Update | CDS | c1scx and c1scy models recompiled and restarted | After the changes listed in 7005
and 7007,
I have rebuilt, installed, and restarted |
|
|
6436
|
Thu Mar 22 16:45:06 2012 |
kiwamu | Update | CDS | c1scx and c1scy not properly running | It
seems that neither c1scx nor c1scy is working
properly as their ADC counts are showing |
|
|
6438
|
Thu Mar 22 17:41:15 2012 |
suresh | Update | CDS | c1scx and c1scy not properly running |
|
|
|
6439
|
Thu Mar 22 23:43:56 2012 |
Koji | Update | CDS | c1scx and c1scy not properly running | Did you guys checked if the simplant switch
is set to "REAL WORLD" mode? |
|
|
5535
|
Sat Sep 24 01:38:14 2011 |
kiwamu | Update | CDS | c1scx and c1x01 restarted | [Koji / Kiwamu]
The c1scx and c1x01 realtime
processes became frozen. We restarted them |
|
|
6175
|
Fri Jan 6 01:00:56 2012 |
kiwamu | Update | CDS | c1scx out of sync | Both
the c1scx and its IOP realtime processes
became out of sync. |
|
|
4173
|
Thu Jan 20 04:03:02 2011 |
kiwamu | Update | CDS | c1scy error | I found
that c1scy was not running due to a daq initialization |
|
|
4175
|
Thu Jan 20 10:15:50 2011 |
josephb | Update | CDS | c1scy error | This is
caused by an insufficient number of active
DAQ channels in the C1SCY.ini file located |
|
|
8626
|
Thu May 23 10:24:23 2013 |
Jamie | Summary | CDS | c1scy model continues to run at the hairy edge | c1scy, the controller model at the Y END,
is still running very long, typically at
55/60 microseconds, or ~92% of it's cycle. |
|
|
9441
|
Wed Dec 4 21:33:24 2013 |
Koji | Update | CDS | c1scy time-over issue mitigated | c1scy had frequent time-over. This caused
the glitches of the OSEM damping servos.
Today Eric Q was annoyed by the glitches |
|
|
5786
|
Wed Nov 2 17:29:10 2011 |
Katrin | Update | CDS | c1scy.mdl compiled | Slight modification on that model:
terminated Q_out of Lockins
to be able to compile the old model
|
|
|
16728
|
Tue Mar 15 14:10:41 2022 |
Anchal | Summary | CDS | c1su2 model remade, reinstalled, restarted after the update | I have restarted c1su2 model with the connections
of Run Acquire switch to analog filters on
coil drivers. Following steps were taken: |
|
|
16726
|
Tue Mar 15 11:52:34 2022 |
Anchal | Summary | CDS | c1su2 model updated for sending Run/Acquire Binary Output to Binary Interface card | I routed the XXX_COIL_DW signals from the
7 SOS blocks in c1su2.mdl (located at /cvs/cds/rtcds/userapps/trunk/sus/c1/models/c1su2.mdl)
to the binary outputs from the FE model. |
|
|
16533
|
Wed Dec 22 17:40:22 2021 |
Anchal | Summary | CDS | c1su2 model updated with SUS damping blocks for 7 SOSs | [Anchal, Koji]
I've updated the c1su2 model
today with model suspension blocks for the |
|
|
16537
|
Wed Dec 29 20:09:40 2021 |
rana | Summary | CDS | c1su2 model updated with SUS damping blocks for 7 SOSs | We want to maintain the 16 kHz sample rate
for the COIL DAQ channels, but nothing wrong
with reducing the others. |
|
|
7165
|
Mon Aug 13 20:12:29 2012 |
jamie | Update | CDS | c1sup model moved to c1lsc machine | I moved the c1sup simplant model to the
c1lsc machine, where there was one remaining
available processor. This requires |
|
|
6619
|
Mon May 7 22:39:37 2012 |
Den | Update | CDS | c1sus | [Jenne, Den]
We decided to reboot C1SUS machine
in hope that this will fix the problem with |
|
|
10135
|
Mon Jul 7 13:44:21 2014 |
Jenne | Update | CDS | c1sus - bad fb connection |
|
|
|
17847
|
Fri Sep 15 22:57:15 2023 |
Koji | Summary | Electronics | c1sus ADC1 AA chassis fix | c1sus ADC1 AA chassis fix.
Brought the chassis on
the workbench.
Opened the chassis |
|
|
17756
|
Sat Aug 5 01:42:19 2023 |
Koji | Update | PEM | c1sus DAC1/DAC2 negative side DAC outputs were isolated from the downstream chain | As reported already, we resolved the c1sus
DAC0 issue by introducing the differential
receivers for the DAC output CHs. |
9x |
|
3945
|
Thu Nov 18 11:06:20 2010 |
josephb | Update | CDS | c1sus and ADCs | Problem:
ADCs are timing out on c1sus when
we have more than 3. |
|
|
4733
|
Tue May 17 18:09:13 2011 |
Jamie, Kiwamu | Configuration | CDS | c1sus and c1auxey crashed, rebooted | c1sus and
c1auxey crashed, required hard reboot |
|
|
6737
|
Fri Jun 1 02:33:40 2012 |
Jenne | Update | Computers | c1sus and c1iscex - bad fb connections | Something bad happened to c1sus and c1iscex
~20 min ago. They both have "0x2bad"
's. I restarted the daqd on the framebuilder, |
|