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ID Date Author Type Category Subject
15108   Wed Jan 1 04:53:11 2020 gautamUpdatePSLMapping the PSL electronics

For the IMC servo board, it'd be easiest to copy the wiring scheme for the BIO bits as is configured for the CM board (i.e. copy the grouping of the BIO bits on the individual Acromag units). This will enable us to use the latch code with minimal modifications (it was a pain to debug this the first time around). I don't see any major constraint in the wiring assignment that'd make this difficult.

15109   Wed Jan 1 14:14:00 2020 YehonathanUpdatePSLPMC Linewidth measurement

Turns out the 35MHz sidebands are way too weak to resolve from the resonance when doing a PZT scan.

I connect the IFR2023B function generator on the PSL table to the EOM instead of the FSS box and set it to generate 150MHz at 13dbm.

To observe the resulting weak sideband I place a PDA55 at the peak-off path from the transmission of the PMC where there is much more light than the transmission of the PMC head mirror. Whoever is using this path there is a PD blocking it right now.

I do a PZT scan by connecting a triangular signal to the EXT DC on the PMC servo with and without the EOM (Attachment 1). A weak sideband can clearly be spotted now.

Using the above 150MHz sideband calibration I can find the roundtrip time to be 1.55ns.

I take a high-resolution scan of a resonance peak and fit it to a Lorentzian (Attachment 2) and find a roundtrip loss of 1.3%.

Using the above results the cavity decay time is 119ns.

We should investigate what's going on with the ringdown measurements.

Attachment 1: 150MHzSideBandCreation.pdf
Attachment 2: LinewidthMeasurment.pdf
15110   Wed Jan 1 16:04:37 2020 YehonathanUpdatePSLMapping the PSL electronics

Done.

Quote:

For the IMC servo board, it'd be easiest to copy the wiring scheme for the BIO bits as is configured for the CM board (i.e. copy the grouping of the BIO bits on the individual Acromag units). This will enable us to use the latch code with minimal modifications (it was a pain to debug this the first time around). I don't see any major constraint in the wiring assignment that'd make this difficult.

15111   Mon Jan 6 15:36:55 2020 JonUpdatePSLAssembly underway for c1psl upgrade

[Jon, Yehonathan]

We've begun assembling the new c1psl Acromag chassis based on Yehonathan's final pin assignments. So far, parts have been gathered and the chassis itself has been assembled.

Yehonathan is currently wiring up the chassis power and Ethernet feedthroughs, following my wiring diagram from previous assemblies. Once the Acromag units are powered, I will help configure them, assign IPs, etc. We will then turn the wiring over to Chub to complete the Acromag to breakout board wiring.

I began setting up the host server, but immediately hit a problem: We seem to have no more memory cards or solid-state drives, despite having two more SuperMicro servers. I ordered enough RAM cards and drives to finish both machines. They will hopefully arrive tomorrow.

15112   Mon Jan 6 16:07:12 2020 gautamUpdatePSLAssembly underway for c1psl upgrade

RTFE. Where did the spares go?

 Quote: I began setting up the host server, but immediately hit a problem: We seem to have no more memory cards or solid-state drives, despite having two more SuperMicro servers. I ordered enough RAM cards and drives to finish both machines. They will hopefully arrive tomorrow.
15113   Mon Jan 6 19:05:09 2020 not gautamUpdatePSLAssembly underway for c1psl upgrade

I found them, thanks. After c1psl, there are 4 2GB DIMM cards and 1 SSD left. I moved them into the storage bins with all the other Acromag parts.

Quote:

RTFE. Where did the spares go?

 Quote: I began setting up the host server, but immediately hit a problem: We seem to have no more memory cards or solid-state drives, despite having two more SuperMicro servers. I ordered enough RAM cards and drives to finish both machines. They will hopefully arrive tomorrow.
15114   Tue Jan 7 18:51:51 2020 JonUpdatePSLNew c1psl server assembled

I've assembled a new SuperMicro rackmount machine to replace c1psl. It is currently set up on the electronics bench.

• OS: Debian 10.2
• Hostname: c1psl1 (will become c1psl after installation)
• IP: 192.168.113.54 (registered in the martian DNS)
• Network drive mount point set up (/cvs/cds), which provides all the EPICS executables.
15115   Fri Jan 10 14:21:19 2020 YehonathanUpdatePSLc1psl reboot

PSL controls on the sitemap went blank. Rebooted c1psl. PSL screens seem normal again.

15116   Fri Jan 10 19:48:46 2020 yehonathanUpdatePSLAssembly underway for c1psl upgrade

{Yehonathan, Jon}

I finished pre-wiring the PSL chassis. I mounted the Acromags on the DIN rails and labeled them. I checked that they are powered up with the right voltage +24V and that the LEDs behave as expected.

Attachment 1: 20200110_194429.jpg
Attachment 2: 20200110_194516_HDR.jpg
15118   Mon Jan 13 16:05:18 2020 yehonathanUpdatePSLAssembly underway for c1psl upgrade

{Yehonathan, Jon}

I configured the Acromag channels according to the Slow Controls Wiki page.

We started testing the channels. Almost at the beginning we notice that the BIO channels are inverted. High voltage when 0. 0 Voltage when 1. We checked several things:

1. We checked the configuration of the BIOs in the windows machine but nothing pointed to the problem.

2. We isolated one of the BIOs from the DIN rail but the behavior persisted.

3. We checked that the voltages that go into the Acromags are correct.

The next step is to power up an isolated Acromag directly from the power supply. This will tell us if the problem is in the chassis or the EPICs DB.

15119   Mon Jan 13 23:30:53 2020 YehonathanSummaryPSLChanges made since Gautam left

As per Gautam's request, I list the changes that were made since he left:

1. The AOM driver was connected to a signal generator.

2. The first order beam from the AOM was coupled into the PMC while the zero-order beam is blocked. We might want to keep this configuration if the pointing stability is adequate.

3. c1psl got Burt restored to Dec 1st.

4. Megatron got updated.

Currently, c1susaux seems unresponsive and needs to be rebooted.

15120   Tue Jan 14 17:16:43 2020 yehonathanUpdatePSLAssembly underway for c1psl upgrade

{Yehonathan, Jon}

I isolated a BIO Acromag completely from the chassis and powered it up. The inverted behavior persisted.

Turns out this is normal behavior for the XT1111 model.

For digital outputs, one should XT1121. XT1111 should be used for digital inputs.

Slow machines Wiki page was updated along with other pieces of information.

I replaced the XT1111 Acromags with XT1121 and did some rewiring since the XT1121 cannot get the excitation voltage from the DIN rail.

I added an XT1111 Acromag for the single digital input we have in this system.

15124   Wed Jan 15 10:12:46 2020 gautamUpdatePSLAssembly underway for c1psl upgrade

I don't think this is an accurate statement. XT1111 modules have sinking digital outputs, while XT1121 modules have sourcing digital outputs. Depending on the requirement, the appropriate units should be used. I believe the XT1111 is the appropriate choice for most of our circuits.

 For digital outputs, one should XT1121. XT1111 should be used for digital inputs.
15125   Wed Jan 15 14:10:28 2020 JonConfigurationPSLNew EPICS database for C1PSL + C1IOO

### Summary

I have completed the new EPICS channel database for the c1psl and c1ioo channels (now combined into the new c1psl Acromag machine). I've tested a small subset of channels on the electronics bench to confirm that the addressing and analog channel calibrations are correct in a general sense. At this point, we are handing the chassis off to Chub to complete the wiring of the Acromag terminals to Dsub feedthroughs. At the 40m meeting today, we identified Feb. 17-22 as a potential window for installation in the interferometer (Gautam is out of town then). Below are some implementaton details for future reference.

### Analog channel calibration for Acromag

For analog input (ai) channels, the Acromag outputs raw values ranging from +/-30,000 counts, but the EPICS IOC interprets the data type as ranging from +/-2^15 = 32,768. Similarly, for analog output (ao) channels, the Acromag expects a drive signal in the range +/-30,000 counts. To achieve proper scaling, Johannes had previously changed the EGUF and EGUL fields from +/-10 V to +/-10.923 V. However, changing the engineering fields makes it much harder for a human to read off the real physical I/O range of the channel.

A better way to achieve the correct scaling is to simply set the field  ASLO=1.09225 (65,536 / 60,001) in addition to the normal EGUF and EGUL field values (+/-10 V). Setting this field forces a rescaling of the number of raw counts that works as so (assuming a 16-bit bipolar ADC or DAC, as are the Acromags):

OVAL = (RVAL * ASLO + AOFF + 2^15) * (EGUF - EGUL) / 2^16 + EGUL

In the above mapping, OVAL is the value of the channel in engineering units (e.g., V) and RVAL is its raw value in counts. It is not the case that either the ASLO/AOFF or EGUF/EGUL fields are used, but not both. The ASLO/AOFF parameters are always applied (but their default values are ASLO=1 and AOFF=0, so have no effect unless changed). The EGUF and EGUL parameters are then additionally applied if the field LINR="LINEAR" is set.

This conversion allows the engineering fields to remain unchanged from the real physical range. The ASLO value is the same for both analog input and output channels. I have implemented this on all the new c1psl and c1ioo channels and confirmed it to work using a calibrated input voltage source.

15126   Wed Jan 15 15:04:31 2020 gautamUpdatePSLPMC Linewidth measurement

For the ringdowns, I suggest you replicate the setup I had - infrastructurally, this was quite robust, and the main problem I had was that I couldn't extinguish the beam completely. Now that we have the 1st order beam, it should be easy.

15127   Wed Jan 15 16:08:40 2020 not gautamUpdatePSLAssembly underway for c1psl upgrade

You're right. We had the right idea before but we got confused about this issue. I changed all the XT1121s to XT1111 and vice versa. We already know which channels are sourcing and which not. Updated the wiring spreadsheet. The chassis seems to work. It's time to pass it over to Chub.

Quote:

I don't think this is an accurate statement. XT1111 modules have sinking digital outputs, while XT1121 modules have sourcing digital outputs. Depending on the requirement, the appropriate units should be used. I believe the XT1111 is the appropriate choice for most of our circuits.

 For digital outputs, one should XT1121. XT1111 should be used for digital inputs.
15131   Fri Jan 17 21:56:22 2020 YehonathanUpdatePSLAOM first order beam alignment

Today I noticed that the beam reflected from the PMC into the RFPD has a ghost (attachment) due to reflection from the back of the high transmission beam splitter that stirs the beam into the RFPD.

The two beams are focused into the RFPD.

In the past, the ghost beam was probably blocked by the BS mirror mount.

I put an iris to block the ghost beam.

Attachment 1: 20200117_174841.jpg
15132   Fri Jan 17 22:11:19 2020 YehonathanUpdatePSLRingdown measurements

I prepare for the ringdown measurement of the PMC according to Gautam's previous experiments.

1. I assembled the needed PDs and power supplies, lenses, beamsplitters and optomechanics needed for the measurement.

2. I surveyed the laser power with an Ophir power meter in the different parts of the experiment. All the measurements were done with the AOM driver excited with 1V DC.

For the PMC reflection, we chose to split off the beam that goes into the reflection camera. The power in that beam is ~ 0.11mW when the PMC is locked and 2.1mW otherwise.

For the PMC transmission, we chose to split the beam that is transmitted through the second steering mirror after the PMC. The power in that beam is 2mW.

For the peak off before the PMC, we chose to split the beam that goes into the fiber coupler. That path contains also the other AOM diffraction orders: 2.26mW in the 0th order beam, 6.5mW in the 1st order beam, 0.14mW in the 2nd order beam.

3. I placed a 10% beam splitter in the peak-off path such that 90% still goes into the fiber coupler (Attachment 1). I place a lens and PDA255 to measure the peak-off (Attachment 2).

It's getting late, I'll continue with the PD placements on Tuesday.

Attachment 1: 20200117_192455.jpg
Attachment 2: 20200117_192448.jpg
15133   Mon Jan 20 12:16:50 2020 gautamUpdatePSLPMC input reverted to AOM zeroth order beam

Summary:

1. The input beam to the PMC cavity was changed back to the zeroth order beam from the AOM.
2. The PMC was locked and nominal transmission levels were recovered.
3. The AOM driver voltage was set to 0V DC.
4. A razor beam dump was placed to catch the first (and higher order) beams from the AOM (see Attachment #1), but allow the zeroth order beam to reach the PMC cavity.
5. Some dangling cabling was cleared from the PSL enclosure.

Details

• HEPA turned to 100% while work was going on in the PSL enclosure.
• Input power to the PMC cut from ~1.3 W to ~20 mW using the first available HWP downstream of the laser head, before any realignment work was done.
• Next, the beam dump blocking the undeflected zeroth order beam was removed.
• Triangle wave was applied to the PZT servo board "EXT DC" input to sweep the cavity length to make the alignment easier.
• After some patient alignment, I could see a weak transmitted beam locked to some high order mode, at which point I increased the input power to 200mW, and did the fine alignment by looking at the mode shape of the transmitted beam.
• Once I could lock to a TEM00 mode, I bumped the power back up to the nominal 1.3W, I fine tuned the alignment further by minimizing PMC REFL's DC level.
• Dialled the power back down (using HWP) for installation of the beam block to catch the AOM's first (and higher order) beams.
• Checked that the reflected beam from the PMC cavity is well centered on the PMC REFL PDH photodiode. The ghost from the AR coating of the high-T beamsplitter is blocked by the iris installed by yehonathan on Friday.
• The beam was a little low on the PMC REFL CCD camera - I raised the camera by ~1cm.
• With the beam axis well matched to the PMC, I measured 1.33 mW going into the cavity, and 1.1 W transmitted, so $T_{\mathrm{PMC}} \approx 83 \, \%$. Whatever loss numbers we extract should be consistent with this fact.
• HEPA turned back down to 30% shortly after noon.

Note that for all the alignment work, only the two steering mirrors immediately upstream of the PMC cavity were touched.

Attachment 1: IMG_8362.JPG
15134   Mon Jan 20 15:11:20 2020 gautamUpdatePSLPMCT photodiode grounding issue

For a few days, I've noticed that the PSL overview StripTool panel shows PMC transmission and FSS RMTEMP channels with variation that is too large to be believable. Looking at these signals on an oscilloscope, there was no such fuzziness in the waveform. I ruled out flaky connections, and while these are the only two channels currently being acquired by the temporary Acromag setup underneath the PSL enclosure, the Acromags themselves are not to blame, because once I connected a function generator to the Acromag instead of the PMC transmission photodiode, both channels are well behaved. So the problem seems to be with the PMC transmission photodiode, perhaps a grouding issue? Someone please fix this.

Attachment 1: PMCT_anomaly.pdf
15135   Mon Jan 20 20:20:36 2020 gautamUpdatePSLPMC servo checkout

Summary:

The PDH discriminant of the PMC servo was measured to be ~0.064 GV/m. This is ~50 times lower than what is reported here. Perhaps this is a signature of the infamous ERA decay, needs more investigation.

Details:

• Calibration of the error and control points were done using 1 Hz triangle wave injection to the "EXT DC" input of the PMC servo. Two such sweeps are shown in Attachment #1 (measured data as points, fits as solid lines). For the control signal monitor, I've multiplied the signal obtained on the scope by 49.6, which is the voltage divider implemented for this monitor point.
• The PDH discrimiannt was calibrated into physical units knowing the modulation frequency of the PMC, which is 35.5 MHz. The error in this technique due to the free-running NPRO frequency noise is expected to be small since the entire fringe is crossed in <30 ms, in which time the laser frequency is expected to change by < 5 kHz.
• The drive to the PZT was calibrated into physical units using the same technique. This number is within a factor of 2 of the number reported here
• Attachment #2 shows the loop OLTF measured using the usual IN1/IN2 prescription (with an SR560). In fact, the 8kHz feature makes the loop unstable. For convenience, I've overlaid the OLTF from March 2017, when things were running smoothly. It is not clear to me why even though the optical gain is now lower, a smaller servo gain results in a larger UGF.

The light level hasn't changed by a factor of 50, leading me to suspect the modulation depth. Recall that the demodulation of the PMC is now done off the servo board using a minicircuits mixer (hence, the "C1:PSL-PMC_LODET" channel isn't a reliable readback of the LO signal strength over time). Although there is a C1:PSL-PMC_MODET channel which looks like it comes from the crystal reference card, and so should still work - this, however, shows no degradation over 1 year.

Somebody had removed the BLP-1.9 that I installed at the I/F output of the mixer to remove the sum frequency component in the demodulated signal, I reinstalled this. I find that there are oscillations in the error signal if the PMC servo gain is increased above 14.5 on the MEDM slider.

Attachment 1: PMCsweep.pdf
Attachment 2: OLTFmeas.pdf
15138   Wed Jan 22 11:00:21 2020 gautamUpdatePSLPMC REFL ghost beam

I looked into this a little more today.

1. The steering optic used to route PMC REFL to the RFPD is in fact a window (labelled W1-PW-1025-UV-1064-45P), not a High-T beamsplitter.
2. With the PMC unlocked, I measured ~10.70 mW in the stronger of the two beams, 5.39 mW in the weaker one.
• The window spec is Tp > 97%. Since we have ~1.3 W incident on the PMC, the primary reflection corresponds to T=99.2%, which is consistent with the spec.
• There is no spec given for the coating on the back side of this window. But from the measured values, it seems to be R = 100* 5.39e-3 / (1.3*T^2) ~ 0.4%. Seems reasonable.

Currently, the iris is set up such that the stronger beam makes it to the PMC RFPD, while the weaker one is blocked by the iris. As usual, this isn't a new issue - was noted last in 2014, but who knows whether the new window was intalled...

 Quote: Today I noticed that the beam reflected from the PMC into the RFPD has a ghost (attachment) due to reflection from the back of the high transmission beam splitter that stirs the beam into the RFPD.
15139   Wed Jan 22 11:22:39 2020 gautamUpdatePSLPMC modulation depth measurement

Summary:

I estimate the PMC servo modulation depth to be approximately 50 mrad. This is only 15% lower than what was measured in Jan 2018, and cannot explain the ~x50 reduction of optical gain measured earlier in this thread. Later in the day, I also confirmed that the LO input to the ZAD-6 mixer is +7 dBm. So the crystal is not to blame.

Details:

1. PSL frequency is locked to the IMC length.
2. Arm lengths are locked to the PSL frequency using POX/POY.
3. EX green laser locked to the X arm length using end PDH servo. GTRX was ~0.4 in this measurement, which is the nominal value.
4. The 20dB coupled port of the beat between the EX and PSL lasers was monitored using the AG4395A in "Spectrum" units.
5. The beat was set at ~90 MHz, and a spectrum was taken for ~100 MHz span centered at the beat frequency.
6. The modulation depth is estimated by considering the ratio of power at the beat frequency relative to that 35.5 MHz away. See Attachment #1.

Assuming a finesse of 700 for the PMC, we expect an optical gain of 2*Pin*J0(50e-3)*J1(50e-3)/fp  ~ 1.2e-7 W/Hz (=0.089 GW/m). I can't find a measurement of the PMC RFPD transimpedance to map this onto a V/Hz value.

Attachment 1: modDepth.pdf
15143   Wed Jan 22 20:12:36 2020 gautamUpdatePSLPMC demodulator electrical characterization

Summary:

The mixer + LPF combo used to demodulate the PMC PDH error signal seems to work as advertised.

Details:

Measurement setup --- Attachment #1. The IF signal was monitored using the scope in High-Z mode.

Results --- Attachment #2.

So the next step is to characterize the RF transimpedance of the PMC RFPD.

Attachment 1: demodChar.pdf
Attachment 2: mixerChar.pdf
15144   Thu Jan 23 14:37:05 2020 gautamUpdatePSLPMC VGA chip damaged?

[jordan, gautam]

Summary:

The AD602 chip which implements the overall servo gain for the PMC seems to be damaged. We should switch this out at the next opportunity.

Details:

1. According to the PSL cross connect wiring diagram, the VME DAC that provides the control voltage to the VGA stage goes to pins 7/8 of cross connect J16.
• Jordan and I verified that the voltage at this point [Vout], is related to the PMC_GAIN EPICS slider [dB] value according to the following relationship: $V_{\mathrm{out}} = (10-\mathrm{dB})/2$.
2. On the PMC servo board, this voltage is scaled by a factor of -1/10.
• This was confirmed by peeking at this voltage using a DMM (I clipped onto R31) while the gain slider was varied.
• This corresponds to +/- 1000 mV reaching the AD602.
• However, the AD602 is rated to work with a control voltage varying between +/- 625 mV.
• What this means is that the EPICS slider value is not the gain of the AD602 stage. The latter is given by the relation $G [\mathrm{dB}] = 32 \times V_{\mathrm{G}} + 10$.
• @team PSL upgrade: this should be fixed in the database file for the new c1psl machine.
3. Using TP1 and TP2 connected to the SR785, I measured the transfer function of the AD602 for various values of the EPICS slider.
• Result is shown in Attachment #1.
• I did this measurement with the PMC locked, so I'm using the in-loop error signal to infer the gain of the VGA stage.
• As expected, the absolute value of the gain does not match that of the EPICS slider (note that the AD602 has an input impedance of 100 ohms. So the 499 ohm series resistor between TP1 and the input of AD602 makes a 1/5 voltage divider, so the gain seen between TP1 and TP2 has this factor folded in).
• Moreover, the relative scaling of the gain for various slider values also doesn't appear to be liner.
• For the highest gain setting of +15 dB, the servo began oscillating, so I think the apparent non-flatness of the gain as a function of frequency is an artefact of the measurement.
• Nevertheless, my conclusion is that the IC should be changed.

I will pull the board and effect the change later today.

I pulled the board out at 345pm after dialling down all the HV supplies in 1X1. I will reinstall it after running some tests.

Attachment 1: VGAchar.pdf
15146   Thu Jan 23 16:37:14 2020 ranaUpdatePSLPMC VGA chip damaged?

doesn't seem so anomolous to me; we're getting ~25 dB of gain range and the ideal range would be 40 dB. My guess is that even thought this is not perfect, the real problem is elsewhere.

15147   Thu Jan 23 18:52:31 2020 gautamUpdatePSLPMC RFPD characterization

Summary:

The RF transimpedance of the PMC PDH RFPD was measured, and found to be 1.03 kV/A

Details:

With the new fiber coupled PDFR system, it was very easy to measure the response of this PD in-situ 🎉 . The usual transfer function measurement scheme was used, with the AG4395 RF out modulating the pump current of the diode laser, and the measured transfer function being the ratio of the response of the test PD to the reference PD.

I assume that the amount of light incident on the reference NF1611 photodiode and the test photodiode were equal - I don't know what the DC transimpedance of the PMC REFL photodiode is (can't find a schematic), but the DC voltage at the DC monitor point was 16.4 mV (c.f. -2.04 V for the NF1611). The assumption shouldn't be too crazy because assuming the reference PD has an RF transimpedance of 700 V/A (flat in the frequency range scanned), we get a reasonable shape for the PMC REFL photodiode's transimpedance.

The fitted parameters are overlaid in Attachment #1. The 2f notch is slightly mistuned it would appear, the ratio of transimpedance at f1/2*f1 is only ~10. The source files have been uploaded to the wiki.

Knowing this, the measured PDH discriminant of 0.064 GV/m is quite reasonable:

• expected optical gain from modulation depth assuming a critically coupled cavity is 0.089 GW/m.
• Assume 0.7 A/W responsivity for InGaAs.
• Account for the fact that only 0.8 % of the reflected light reaches the PMC photodiode because of the pickoff window.
• Account for a conversion loss of 4.5 dB in the mixer.
• Account for the voltage division by a factor of 2 at the output of the BLP-1.9 filter due to the parallel 50 ohm termination.
• Then, the expected PDH discriminant is 0.089e9 W/m * 0.7 A/W * 0.8e-2 * 1.03kV/A * 10^(-4.5/20) * 0.5 ~ 0.15 GV/m. This is now within a factor of ~2 of the measured value, and I assume the total errors in all the above assumed parameters (plus the cable transmission loss from the photodiode to the 1X1 rack) can easily add up to this.

So why is this value so different from what Koji measured in 2015? Because the monitor point is different. I am monitoring the discriminant immediately after the mixer, whereas Koji was using the front panel monitor. The latter already amplifies the signal by a factor of x101 (see U2 in schematic).

Conclusion:

I still haven't found anything that is obviously wrong in this system (apart from the slight nonlinearity in the VGA stage gain steps), which would explain why the PMC servo gain has to be lower now than 2018 in order to realize the same loop UGF.

 So the next step is to characterize the RF transimpedance of the PMC RFPD.
Attachment 1: PDresp.pdf
15149   Thu Jan 23 22:10:01 2020 gautamUpdatePSLPMC servo pulled out

While I have the board out, I'll try and do a thorough investigation of TFs and noise of the various stages. There is no light into the IFO until this is done.

 I pulled the board out at 345pm after dialling down all the HV supplies in 1X1. I will reinstall it after running some tests.
15150   Thu Jan 23 23:07:04 2020 JonConfigurationPSLc1psl breakout board wiring

To facilitate wiring the c1psl chassis and scripting loopback tests, I've compiled a distilled spreadsheet with the Acromag-to-breakout board wiring, broken down by connector. This information is extractable from the master spreadsheet, but not easily. There were also a few apparent typos which are fixed here.

The wiring assignments at the time of writing are attached below. Here is the link to the latest spreadsheet.

Attachment 1: c1psl_feedthrough_wiring.pdf
15152   Fri Jan 24 15:42:08 2020 gautamUpdatePSLPMC servo restored

The PMC servo was re-installed at ~345pm. HV supplies were re-energized to their nominal values. I will update the results of the investigation shortly. The new nominal PMC servo gain is +9dB.

Quote:

While I have the board out, I'll try and do a thorough investigation of TFs and noise of the various stages. There is no light into the IFO until this is done.

 I pulled the board out at 345pm after dialling down all the HV supplies in 1X1. I will reinstall it after running some tests.
15154   Sat Jan 25 11:54:42 2020 YehonathanUpdatePSLRingdown measurements

Zero order beam PMC ringdown

On Wednesday I installed 3 PDs (see attached photos) measuring:

1. The input light to the PMC. Flip-mirror was installed (sorry Shruti) on the beam path to the fiber coupler.

2. Reflected light from the PMC.

3. PMC transmitted light.

I connected the three PDs to the oscilloscope and the AOM driver to a function generator. I drive the AOM with a square wave going from 1V to 0V.

I slowly increased the square wave frequency. The PMC servo doesn't seem to care. I reach 100KHz - it seems excessive but still works. In any case, I get the same results doing a single shut-down from a DC level.

I download the traces. I normalize the traces but I don't rescale them (Attachment 4) so that the small extinction can be investigated.

I notice now that the PDs show the same extinction. It probably means I should have taken dark currents data for the PDs.

Also, I forgot to take the reflected data when the PMC is out of resonance with the laser which could have helped us determine the PMC transmission.

Again, the shutdown is not as sharp as I want. There is a noticeable smoothening in the transition around t = 0 which makes the fit to an exponential difficult. I suspect that the function generator is the limiting device now. I hooked up the function generator to the oscilloscope which showed similar distortion (didn't save the trace)

I try to fit the transmission PD trace to a double exponential and to Zucker model (Attachment 5).

The two exponentials model, being much less restrictive, gives a better fit but the best fit gives two identical time constants of 92ns.

The Zucker model gives a time constant of 88ns. Both of these results are consistent with more or less with the linewidth measurement but this measurement is still ridden with systematics which hopefully will become minimized IMC ringdowns.

Attachment 1: Input_beam_path.jpg
Attachment 2: Reflected_Beam_Path.jpg
Attachment 3: Transmitted_Beam_Path.jpg
Attachment 4: PMCRingdownNormalizedRawdata.pdf
Attachment 5: TransPDFits.pdf
15156   Sun Jan 26 13:47:00 2020 gautamUpdatePSLPMC servo characterization

Summary:

1. I investigated the stage-by-stage transfer functions of the PMC servo up till the HV stage. See Attachment #1. There were no unexpected features.
2. I replaced the AD602 used to implement the VGA capability. After the replacement, the gain of the VGA stage had the desired performance, see Attachment #2, Attachment #3.
3. The servo board was re-installed and the OLTF of the PMC loop was measured. See Attachment #4.

​To avoid driving the PA85 without the HV rails connected, I removed R23. This was re-installed after my characterization.

Input stage:

Since we do the demodulation of the PMC PDH signal off this servo board, the I/F mixer output is connected to the "FP1test" front panel LEMO input.

• A DG190 is used to enable/disable this path.
• Initially I tried checking the enable/disable functionality by measuring the resistance across the IC's I/O pins. However, this method does not work - the resistance read off from a DMM varied from ~23 ohms in the "ON" state to ~123 ohms in the "OFF" state. While the former value is consistent with the spec, the latter is confusing.
• But I confirmed that the switch does indeed isolate the input in the "OFF" state by injecting a signal with a function generator (100 Hz sine wave, 100mVpp) and monitoring the output on an oscilloscope.

Electronic TFs:

Using some Pomona mini-grabbers, I measured the electronic TFs between various points on the circuit. There were no unexpected features, the TFs all have the expected shape as per the annotations on the DCC schematic. I did not measure down to 0.1 Hz to confirm the low frequency pole implemented by U6, and I also didn't measure the RF low pass filter at the input stage (expected corner frequency is 1 MHz).

VGA characterization:

After replacing the IC, I measured the transfer function between TP1 and TP2 for various values of the control voltage applied to pin 4A on the P1 connector, varying between +/- 5 V DC.

• Pin 9A on the P1 connector has to be grounded for the signal to be allowed to pass through the VGA.
• Note that there is an overall gain of -1/10 applied to the control voltage between pin 4A and pin #1 of the AD602, which is what actually sets the gain.
• Furthermore, the input impedance of the AD602 is spec-ed to be 100 ohms. Because of the series resistance of 500 ohms from TP1 to the input of the AD602 (so that the upstream OP27 isn't overdrawn for current), the relation between the control voltage applied to Pin 4A and gain (measured between TP1 and TP2) is modified to G [dB] = 32*(-0.1 * V_pin4A) - 6.
• The gain behavior after the IC swap is as expected, both in terms of absolute gain, and the linearity w.r.t. the control voltage.
• Note that in Attachment #2, each color corresponds to a different control voltage to the AD602, varying from -5V DC to +5V DC in 1V steps.

PZT Capacitance measurement

I confirmed that the PZT capacitance is 225 nF. The measurement was made using an LCR meter connected to the BNC cable delivering the HV to the PZT, at the 1X1 rack end.

OLTF measurement

After re-soldering R23, I put the board back into its Eurocrate, and was able to lock the PMC. For subsequent measurements, the PSL shutter was closed.

• I measured the OLTF using the usual IN1/IN2 prescription, implemented with the help of an SR560.
• At the original PMC Servo gain of +12dB, I found that the feature at ~8kHz results in an OLTF with multiple unity gain crossings.
• So I lowered it to +9dB. This yields an OLTF with ~60deg phase margin, ~2.3 kHz UGF.
• The feature that sets the gain margin is actually not any of the peaks fit by LISO, but is one of the high frequency features at ~40 kHz. At the new setting of +9dB gain, the gain margin is ~10 dB.
• The measured TF (dots in Attachment #5) was fit with LISO (solid lines in Attachment #5) to allow inferring the out-of-loop servo noise by monitoring the in-loop noise (that plot to follow).
Attachment 1: elecTFs.pdf
Attachment 2: VGAchar_postFix.pdf
Attachment 3: VGAlinearity_postFix.pdf
Attachment 4: newOLTFs.pdf
15160   Mon Jan 27 21:35:06 2020 YehonathanUpdatePSLRingdown measurements

Zeroth order IMC ringdown setup

Following Gautam's IMC ringdown setup, I took the REFL PD form the PMC ringdown experiment and installed it in the IMC REFL path blocking WFS2 (Attachment 1).

I also ran a BNC cable from the transmission PD that Gautam installed on the IMC table to the vertex where the signals are measured on the scope.

I offloaded the WFS servo output values onto the MC alignment (using the WFS servo relief script) so that its dc values would be correct when the servo is off.

Unfortunately, it seems like the script severely misaligned the MC mirrors at some point when the MC got unlocked. We should fix the script such that it stops when the offloading is complete.

We got the MC realigned but left it in a state where it is not locking easily.

Attachment 1: IMC_REFL_Beam_Path.jpg
15161   Mon Jan 27 21:48:49 2020 gautamUpdatePSLRingdown measurements

It's fine to block the WFS while doing ringdowns but please return the config to normal so I don't have to spend time every night recovering the interferometer before doing the locking. As I mention in that post, it is possible to do this in a non-invasive way without having to run any extra cables / permanently block any beams. If there is some issue with the data quality, then we can consider a new setup. But I see no reason to re-invent the wheel.

The IMC was also massively misaligned. I had to re-align both MC1 and MC2 to recover the lock. I took this opportunity to reset the WFS offsets. Please do not disturb the alignment of the existing optical layout unless you verify that everything is working as it should be after your changes.

And for whatever reason, ITMX was misaligned. If you do something with the interferometer, no matter how minor it seems, please leave a note on the ELOG. It will save many painful debugging hours.

As I fix these, the seismic activity has gone up . I'll wait around for an hour, but not an encouraging restart to the locking 😢

 Quote: Zeroth order IMC ringdown Following Gautam's IMC ringdown setup, I took the the REFL PD form the PMC ringdown experiment and installed it in the IMC REFL path blocking WFS2 (Attachment 1).
Attachment 1: elevatedSeis.pdf
15163   Tue Jan 28 14:33:24 2020 gautamUpdatePSLInferred free-running frequency noise

To conclude my PMC noise investigations: Attachment #1 shows the PMC noise inferred from the calibrations earlier in this thread and the fitted OLTF for the PMC loop. Attachment #2 compares the frequency noise (inferred from the error point of the PMC servo) when the IMC is locked / unlocked. I don't know what to make of the fact that the PMC suggests improvement from ~20 Hz onwards already - does this mean that the NPRO noise model is wrong by 1 order of magnitude at 30 Hz?

• The IMC was locked for the measurement shown in Attachment #1.
• The in-loop spectra of the error (at the I/F output of the mixer) and control (at TP3) signals were measured with the SR785.
• The control signal voltage monitors don't seem to work - neither the front panel LEMO nor the signals hooked up to the CDS system show me sensible shapes for the spectra between 1-3 Hz.
• To convert in loop to free-running, I multiplied the measured error (control) signal spectra by $\left | 1-L \right |$ ($\left | \frac{L}{1-L} \right |$), where L is the OLTF. THe control signal was pre-processed by multiplying by a pole at 11.3 Hz, corresponding to the LPF formed by the 63.3 kohm series resistor and the 225 nF PZT capacitance.
• The "NPRO noise model" curve is 10^4/f Hz/rtHz.

While I initially thought the 1/f^2 rise below ~100 Hz is attributable to the IMC cavity length fluctuations, I found that this profile is present even in the measurement with the PSL shutter closed. I am not embarking on a detailed PMC noise budgeting project for now. Note however that we are not shot noise limited anywhere in this measurement band.

 The measured TF (dots in Attachment #5) was fit with LISO (solid lines in Attachment #5) to allow inferring the out-of-loop servo noise by monitoring the in-loop noise (that plot to follow).
Attachment 1: inLoopNoise_IMClocked.pdf
Attachment 2: freqNoiseComparison.pdf
15168   Tue Jan 28 19:12:30 2020 JonConfigurationPSLSpare channels added to c1psl chassis

After some discussion with Gautam, I decided to build more spare channels into the new c1psl machine. This is anticipation of adding new laser and ISS channels in the near future, to avoid having to disconnect the installed chassis and pull it out of the rack. The spare channels will be wired to DB37M feedthroughs on the front side of the chassis, with enough wire length to be able to pull the breakout boards out of the front to reconfigure their wiring as needed (e.g., split off channels onto a separate connector).

To have enough overhead, this will require installing 1 additional ADC unit (XT1221) and 1 additional DAC (XT1541). We have enough spare BIO channels among the existing units (both sinking and sourcing). This will give us:

• 14 spare DAC channels
• 16 spare sinking BIO channels
• 12 spare sourcing BIO channels

The updated c1psl chassis wiring assignments are attached. It adds 4 new DB37M connectors for the spare channels (highlighted in yellow) and fixes one typo Jordan found while wiring today. The most current spreadsheet is available here.

Attachment 1: c1psl_feedthrough_wiring_v2.pdf
15178   Thu Jan 30 17:31:28 2020 JonUpdatePSLErrant FSS_INOFFSET change

A script I was testing errantly set C1:PSL-FSS_INOFFSET => 10 V at about 5:30 pm. I manually reverted the channel value to 0, but I don't know what the value was initially. Someone please check this value if there are problems locking the FSS.

15179   Thu Jan 30 17:41:10 2020 gautamUpdatePSLErrant FSS_INOFFSET change

You can trend the data for the past few hours and see what the appropriate value. I think these tests should only be done when whoever is running a test is in the lab.

P.S. I was surprised that the IMC didn't lose lock when this step was applied. I manually stepped this voltage between +/- 10 V and didn't see any response in the FSS readbacks. Either the channel doesn't work, or there is a divide by 40 in the physical circuit or something...

 Quote: A script I was testing errantly set C1:PSL-FSS_INOFFSET => 10 V at about 5:30 pm. I manually reverted the channel value to 0, but I don't know what the value was initially. Someone please check this value if there are problems locking the FSS.
15184   Mon Feb 3 15:22:39 2020 JonUpdatePSLc1psl progress/Acromag ADC grounding

I tested the c1psl AO channels on the electronics bench on Friday. While I found all the wiring to be correct, some of the channels exhibited excess noise with all appearances of a grounding problem.

Today Jordan, Gautam, and I investigated this further. It is indeed a grounding problem, but actually with the Acromag ADCs. The Acromag DAC outputs are single-ended (return is grounded), so (for the purpose of a loopback test) I would expect to leave the ADC inputs ungrounded. This is the configuration I tested Friday. Today we also tested driving the ADC with a floating source. The ADC noise behavior is exactly the same, whether the source end is grounded or not.

However, grounding the minus pin of the ADC channel eliminates the noise. We don't understand why this seems to be required irrespective of the driving source, so there something we're missing about the ADC design. As it turns out, this same fix was made to the AI channels of the previously-upgraded Acromag machines. I know Chub and I had to do this for the AI channels of c1vac, but at the time we thought the source grounding was causing the issue. However, today Jordan and I looked inside c1iscaux, which Chub wired, and confirmed that its AI channels are wired in the same way.

So in any case, Jordan is grounding the c1psl AI channels in the same way as c1iscaux. Once this is done, we'll continue with the bench testing tomorrow.

gautam: here are my notes about this issue when i was doing the c1iscaux testing. As I note there, "previously-upgraded Acromag machines" in the plural may be a bit of a stretch - I have no idea what the grounding situation is in c1susaux / c1auxex for example.

15186   Tue Feb 4 18:13:01 2020 YehonathanUpdatePSLBench testing of PSL ai channels

{Yehonathan, Jon, Jordan}

I tested the ai channels of the new PSL Acromag by looping an already-tested ao channel (C2:PSL-FSS-INOFFSET) back to the different ai channels.

I use Jon's IFOTest with /users/jon/ifotest/PSL.yaml.

I created a spreadsheet for the testing based on the current wiring spreadsheet. I added two columns for the high and low readings for each ai channel (attached pdf).

I marked in red the failed channels. Some of them are probably calibration issues, but the ones that show the same voltage for high and low are probably disconnected wires.

I redid the test on the channel that seemed disconnected to confirm.

I created a yaml file with all the failed channels for retesting called /users/jon/ifotest/PSL_failed_channels.yaml.

Attachment 1: c1psl_wire_testing_-_By_Connector.pdf
15187   Wed Feb 5 08:57:11 2020 YehonathanUpdatePSLBench testing of PSL ai channels

I checked the failed channels against the EPICS database definitions and the yaml file inputted to IFOTest. The channels where the readings are something other than +10/0 V, but the high/low values do change, I think can be attributed to one of two things:

• An incorrect gain and/or offset conversion parameter in the yaml file
• The EPICS SMOO parameter (smoothing) is set to some long value

I fixed the channel gains/offsets in the master yaml file (PSL.yaml). I also disabled smoothing in the EPICS defintions of the new PSL channels for the purpose of testing. We can uncomment those lines after installing the new chassis if noise is a problem. Please go ahead and re-test the channels again.

 Quote: I marked in red the failed channels. Some of them are probably calibration issues, but the ones that show the same voltage for high and low are probably disconnected wires.
15189   Wed Feb 5 21:04:10 2020 YehonathanUpdatePSLBench testing of PSL ai channels

{Yehonathan, Jon}

We retested the failed ai channels. Most of them got fixed by applying the inverse calibration in the yaml file.

We still find some anomalous channels, mostly in the DB25 connector. Turns out, their limits were ill-defined in the EPICS database. Specifying the right limit fixed the issue.

We find one miswired channel (BNC4). We connected the BNC to the right channel on the Acromag unit which fixed the issue.

Overall all the ai channels were successfully bench-tested.

Quote:

I checked the failed channels against the EPICS database definitions and the yaml file inputted to IFOTest. The channels where the readings are something other than +10/0 V, but the high/low values do change, I think can be attributed to one of two things:

• An incorrect gain and/or offset conversion parameter in the yaml file
• The EPICS SMOO parameter (smoothing) is set to some long value

I fixed the channel gains/offsets in the master yaml file (PSL.yaml). I also disabled smoothing in the EPICS defintions of the new PSL channels for the purpose of testing. We can uncomment those lines after installing the new chassis if noise is a problem. Please go ahead and re-test the channels again.

 Quote: I marked in red the failed channels. Some of them are probably calibration issues, but the ones that show the same voltage for high and low are probably disconnected wires.
15194   Thu Feb 6 21:54:13 2020 JonUpdatePSLc1psl bench testing complete

Today I engineered the last piece of the new c1psl system: the multi-bit binary output (mbbo) channels that control the MC servo board gains. These 6-bit channels have to be split across two 4-bit Acromag registers. To enforce synchronous switching, I adapted the latch.py script developed by Gautam to address this problem in c1iscaux. Analogously to the c1iscaux implementation, I scripted the code to automatically run as a systemd service which is launched by the main modbusIOC service. I tested this all using the DB37 LED test board and confirmed it to work.

This now completes the electronics bench testing.

There are still several DB37 connectors to be wired, which carry only spare channels for future use and are not interfaced with the EPICS IOC. Jordan and I discussed this today and he or Chub will complete it shortly. To allow time for the spare channel wiring to be completed (as well as for more locking progress before interruption), Gautam and I think Monday/Tuesday next week would be the earliest possible window to install the new system.

15202   Mon Feb 10 10:07:20 2020 gautamUpdatePSLPMC re-locked

I found the PMC unlocked this morning. It was re-locked using the usual procedure. I feel like this has been happening more frequently in the last month than before. In the past, the cause seems to have been the PZT voltage drifting too close to one of the rails - however, in this case, it looks like an IMC unlock event is what triggered the PMC lockloss (admittedly the PZT voltage was somewhat close to the rail). It would be good if someone can re-connect the PMC Transmission photodiode, it was a useful diagnostic channel we had working fine before the ringdowns started.

I also tweaked the input pointing into the PMC and ran the WFS DC offset relief script.

Attachment 1: PMCunlock.png
15204   Mon Feb 10 15:54:47 2020 JordanUpdatePSLCompleted Acromag Wiring

All spare channels on the PSL acromag chassis are connected with ~12in of spare wiring for future use.

15205   Mon Feb 10 15:55:46 2020 JordanUpdatePSLPMCTRANSPD

[Gautam, Jordan]

Gautam showed me how the PMCTRANSPD signal was reading zero, and he suspected it might have to do with the acromag wiring. Disconnected the acromag box underneath the PSL table and checked the ADC wiring. Side note: When benchtesting the c1psl acromag chassis there was excess noise in the AI channels, and grounding the minus pin of the ADC channel eliminates the noise.

So I grounded the (-) pins on the ADC1 (192.168.113.122), which PMCTRANSPD is connected to and that seemed to fix the problem. As of right now PMCTRANSPD is reading ~.75 V.

See attached pictures

gautam: While this fix seems to have worked, I wonder why this became necessary only in the last month. Note that the problem was a noisy readback on the PMC transmission PD, which also made the FSS_RMTEMP channel noisy, leading me to suspect some kind of ground loop issue.

15231   Thu Feb 27 17:50:36 2020 gautamUpdatePSLc1psl setup setup

[many people]

in prep for the install tomorrow, we did the following:

• Install the c1psl Supermicro in the 1X2 rack (Attachment 1). To make room we removed the anti-image filter and mounted it on the OMC rack.
• Set up a local workstation (monitor+mouse+keyboard) for the Supermicro so we can do some local testing (Attachment 2).
• Clear up the immediate area around the 1X1/1X2 rack, setup a cart for the Acromag.
• Make sure there are sufficient adaptor boards cables (DB37, DB15, DB9, DB25, ethernet) etc available at the cart.
• Label cables, connect on Acromag chassis end (Attachment 3).
• Keep some large (A3) printouts of the channel mapping handy by the cart.
• made sure we have open fuse-able DIN rail connectors for +/-15 V DC and +/-24 V DC for the Acromag box (we are waiting on some thinner gauge cabling for the 24V supply, once that arrives, we will power the box from the Sorensens. For now, they are powered by bench supplies on the cart).
• made sure c1psl1 (still this name for the Supermicro) is ssh-able.

Barring objections, tomorrow (Friday 28 Feb 2020) morning I will commence the switch (I still want to work on the IFO tonight).

Attachment 1: 20200227_173535.jpg
Attachment 2: 20200227_173454_HDR.jpg
Attachment 3: 20200227_172659.jpg
15234   Fri Feb 28 08:05:22 2020 gautamUpdatePSLc1psl setup setup

And so it begins.

 Quote: Barring objections, tomorrow (Friday 28 Feb 2020) morning I will commence the switch
15235   Fri Feb 28 10:04:41 2020 gautamUpdatePSLc1psl setup setup

Summary:

There are several problems evident already.

1. Several EPICS database entries were missing. WTF.
2. After fixing the missing entries, the PMC could be locked. However, the IMC could not be locked.
3. I think the FSS Interface card is not configured correctly.

For now, I've returned the old c1psl connections, the PMC and IMC are both locked. Need to do some debugging on the bench.

15236   Fri Feb 28 19:37:18 2020 gautamUpdatePSLNew c1psl installed
1. The new c1psl Acromag crate is now interfaced to the Eurocrate electronics in 1X1 (formerly VME c1psl) and 1X2 (formerly c1iool0).
2. The PMC and IMC can be locked. We will investigate stability / duty cycle over the weekend.
3. There were a few issues with the wiring - specifically, the worng kind of Acromag BIO unit (sourcing, whereas we want sinking) was used for the FSS board switches. Once Jordan fixed this issue, the IMC could be locked.
4. I began to do the detailed tests of the IMC Servo card channels - there may be some issues with the boost stages, but I ran out of time yesterday, so tbc Monday.

On Monday, we will remove the old c1psl and c1iool0 machines from the electronics rack and install the Acromag crate in a more permanent way. We will also clean up some of the old cabling and cross connects, althoug the situation seems so complicated (some cross connects are also used by the rtcds c1ioo expansion chassis) that I am inclined not to remove any cables.

The area around 1X1/1X2 has a lot of dangling cables and general detritus. Be careful if you are walking around there. We will clean up on monday.

ELOG V3.1.3-