The returning spot diameter on the qpd ~10 mm. In order to reduce the spot size I moved the f 1145 mm lens toward the PRM ~ 25 cm. The spot size was reduced to ~8 mm, 3200 counts.
I'll try to find an other lens tomorrow.
I swapped the name of two demodulation boards (AS55 and REFL55).
Now the REFL11 and AS55 demodulation boards are ready to go for the PRMI locking.
The physical labels, which are on the front surface of the boards, are also corrected to avoid a confusion.
Here is the latest RF status.
The files are on https://nodus.ligo.caltech.edu:30889/svn/trunk/suresh/40m_RF_upgrade/.
.....Happy.... Birthday.... to.... Joseph... and... Jamie...Happy....Birthday..... to.... You............sing with us........Happy Birthday.....to you
I had a quick look at PRM optical lever.
The He-Ne beam is still successfully coming out from the chamber and I could guide it to the QPD by using steering mirrors.
But the beam size looks too big for the QPD. We should slide the lens which is standing before the injection to get a moderately smaller beam size at the QPD.
- activation of PRM oplev
Today we will try to lock the PRMI. Here is a plan for it.
(to be done in the daytime)
- setup REFL11 RFPD
- setup AS55 RFPD
- install a demod board for 55 MHz
- install a 3-way RF combiner on EOM.
- prepare 55 MHz RF source (Marconi or RF source box ?)
- adjustment of each demodulation phase
- AS55_Q ==> BS
- REFL11_I ==> PRM
There is a useful script for this particular job : shutting down all the suspensions and bringing it back to operation after 5 hrs.
It is called opticshudown, which resides in /cvs/cds/rtcds/caltech/c1/scripts/SUS/.
Also I added this script on the list in the wiki where all the scripts will be listed.
If you find any other useful scripts, please add them on the wiki.
I leave all the suspensions free from the watchdogs for 5 hours from now.
- AC coupling for the comparator circuit of the green locking
In order to relieve the power consumption of the RF buffer, ac coupling circuits have been added.
The ac coupling before the buffer amp helps to relieve the power consumption in the chip.
But because of the distortion of the signal (and the limitation of the bandwidth), the output still has some DC (~0.6V).
Therefore, the output is also AC coupled.
Note that the BW pin of BUF634P should be directly connected to -15V in order to keep the bandwidth of the buffer.
The drawings are also uploaded on the green electronics wiki
As a part of the DRMI preparation,
Please DO NOT touch them.
I will check the spectra and the mechanical resonant frequencies on Monday.
Also I will renew all the input matrices of the local dampings based on these free swinging spectra.
[Joe, Jamie, Suresh]
We have installed the IDE to SCSI adaptor module into the 1X2 rack and have connected the AA filter outputs to it.
We have removed the following cables running between the 1X2 and 1X3 racks.
The long twisted pair ribbon cable which previously carried the ADC signals.
1X2-ASC 6, 1X2-ASC 47, 1X2-ASC 9, 1X2-ASC 8, 1X2-ASC 10, 1X2-ASC 7,
CAB-1X2-LSC 42, CAB 1X2-LSC 56, CAB 1X2-LSC 41, CAB 1X2-LSC 43
1X3-2 ASC 47
We have also removed the following by mistake. We will put them back them on Monday
1X2-LSC 21, 1X2-LSC-20.
We have also removed the ASC QPD cables and moved the QPD cards which were present in the middle Eurocate (#2) to the unused Eurocrate at the bottom position (#3).
The binary input cables at the back of the cards require to be supported so that their weight does not pull them out of the sockets at the back of the crates.
Some of the slots where we plan to plug in Demod boards (the 165 MHz boards) are not currently connected to any binary output on the C1:LSC computer. We need these binary controls for the fitlter modules on the cards.
When we eventually begin to use the 15PDs as planned, then we will occupy 30 ADC channels (I & Q outputs). Currently we have just one ADC card installed on the C1:LSC providing 32 ADC channels. Joe found another 16bit 32 channel ADC card in his stash but we need to get a timing+adaptor board for it. In general we are going to need the third Eurocrate.
A platform for the power supply of the RF Distribution box needs to be built and the power supply needs to be moved into the 1X2 rack rather than sit on top of 1X2 rack.
Way back, Jay had D-sub to SCSI adapters made to adapt our existing Sander box AA filters to the new SCSI based IO chassis. However, these did not fit inside the box.
At the time, we simply left the cards outside hanging, which was a hack and needed to be replaced.
Steve modified a black AA filter box so that it could fit the D-sub to SCSI adapter board on it, plus strain relief the SCSI cable, rather than let it hang. The back of the box was cut, and an extending piece of metal attached to the bottom of the box. The adapter board was screwed into the box, the SCSI plugged in, then the SCSI cable is clamped to the extending metal as well.
This modification will be propagated to the 3 remaining AA filter boards using the D-sub to SCSI adapter.
The same modification was carried out at 1X5 for PRM & SRM.
Note: D68L8EX-850Hz are removed and bypassed in 7 channels.
* Farfalla, a lab laptop, seems out of network.
If you look at the real host table instead of the misleading host table in the wiki, you will see that someone has deleted Farfalla from there. She needs to be re-added.
As far as I know, this button works only once after the launch of MEDM...
* reload button on sitemap.adl doesn't work.
First of all, the conclusions / results from the exercise of the Y arm locking yesterday are:
The position of the beam spots on both ETMY and ITMY are now not so bad ( ~ 5 mm off from the center).
The input PZTs are coarsely aligned to the Y arm.
Nevertheless IP_ANG is still too high to come out from the view port at the Y end station.
After the alignments of PRM, SRM and Michelson, POP is still largely clipped.
(what I did)
- Alignments of the Input PZTs
- Adjustment of the demodulation phase for the Y arm PDH.
- Activation of oplev on ITMY
- PDH locking
(Broken or likely broken stuff)
* IP_ANG doesn't give a signal to the digital side.
* ETMY coils look weak and 2 - 3 times weaker than the other test masses. (or OSEM readout gain maybe lower)
* reload button on sitemap.adl doesn't work.
The Y arm has been locked with the IR beam. The purpose is to use the arm as an alignment reference for the input PZTs.
Detail will be posted later. Here is a picture of ITMY suspension. You can see there is a beam spot in the middle of the test mass.
I tried the idea that the PRC can resonate f1 and f2 at the same time if the arm gives the reflection phase to f1 and f2 with the ratio of 1 vs 5.
The details are described on wiki. The point is this removes all of the PRC/SRC/asymmetry mumbo jumbo.
The calculated cavity lengths for f_mod of 11.065399MHz are:
Arm Length: 37.7974 [m]
PRC Length: 6.7538 [m]
SRC Length: 5.39915 [m]
Asymmetry (lx-ly): 0.0342 [m]
Here is the actual values derived from the photos.
Arm Length: 37.54 [m] (0.26m too short)
PRC Length: 6.760 [m] (6mm too long)
SRC Length: 5.415 [m] (16mm too long)
Asymmetry (lx-ly): 0.0266 [m] (8mm too long)
With some assistance from Kiwamu and Koji, I've drawn up the electronics design for the Beat Box for the vertex green locking. The Omingraffle schematic is posted on the Green Locking Wiki page. It's also attached below. Some final touches are necessary before we can Altium this up.
Attachment 1: Schematic of beatbox
Attachment 2: Front and back panel designs.
We are now using the LIGO CDS SVN for storing our control models.
The SVN is at:
The models are under cds_user_apps, then trunk, then approriate subsystem (ISC for c1lsc for example), c1 (for caltech 40m), then models.
We have checked out /cds_user_apps to /opt/rtcds/.
So to find the c1lsc.mdl model, you would go to /opt/rtcds/cds_user_apps/trunk/ISC/c1/models/c1lsc.mdl
This SVN is shared by many people LIGO, so please follow good SVN practice. Remember to update models ("svn update") before doing commits. Also, after making changes please do an update to the SVN so we have a record of the changes.
We are creating soft links in the /opt/rtcds/caltech/c1/core/advLigoRTS/src/epics/simLink/ to the models that you need to build. So if you want to add a new model, please add it to the cds_users_apps SVN in the correct place and create a soft link to the simLink directory.
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1sus.mdl -> /opt/rtcds/cds_user_apps/trunk/SUS/c1/models/c1sus.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1sup.mdl -> /opt/rtcds/cds_user_apps/trunk/SUS/c1/models/c1sup.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1spy.mdl -> /opt/rtcds/cds_user_apps/trunk/SUS/c1/models/c1spy.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1spx.mdl -> /opt/rtcds/cds_user_apps/trunk/SUS/c1/models/c1spx.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1scy.mdl -> /opt/rtcds/cds_user_apps/trunk/SUS/c1/models/c1scy.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1scx.mdl -> /opt/rtcds/cds_user_apps/trunk/SUS/c1/models/c1scx.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1mcs.mdl -> /opt/rtcds/cds_user_apps/trunk/SUS/c1/models/c1mcs.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1x05.mdl -> /opt/rtcds/cds_user_apps/trunk/CDS/c1/models/c1x05.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1x04.mdl -> /opt/rtcds/cds_user_apps/trunk/CDS/c1/models/c1x04.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1x03.mdl -> /opt/rtcds/cds_user_apps/trunk/CDS/c1/models/c1x03.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1x02.mdl -> /opt/rtcds/cds_user_apps/trunk/CDS/c1/models/c1x02.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1x01.mdl -> /opt/rtcds/cds_user_apps/trunk/CDS/c1/models/c1x01.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1rfm.mdl -> /opt/rtcds/cds_user_apps/trunk/CDS/c1/models/c1rfm.mdl
lrwxrwxrwx 1 controls controls 55 Apr 28 14:41 c1dafi.mdl -> /opt/rtcds/cds_user_apps/trunk/CDS/c1/models/c1dafi.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1pem.mdl -> /opt/rtcds/cds_user_apps/trunk/ISC/c1/models/c1pem.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1mcp.mdl -> /opt/rtcds/cds_user_apps/trunk/ISC/c1/models/c1mcp.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1lsp.mdl -> /opt/rtcds/cds_user_apps/trunk/ISC/c1/models/c1lsp.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1lsc.mdl -> /opt/rtcds/cds_user_apps/trunk/ISC/c1/models/c1lsc.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1ioo.mdl -> /opt/rtcds/cds_user_apps/trunk/ISC/c1/models/c1ioo.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1gpv.mdl -> /opt/rtcds/cds_user_apps/trunk/ISC/c1/models/c1gpv.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1gfd.mdl -> /opt/rtcds/cds_user_apps/trunk/ISC/c1/models/c1gfd.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1gcv.mdl -> /opt/rtcds/cds_user_apps/trunk/ISC/c1/models/c1gcv.mdl
lrwxrwxrwx 1 controls controls 54 Apr 28 14:41 c1ass.mdl -> /opt/rtcds/cds_user_apps/trunk/ISC/c1/models/c1ass.mdl
Since Suresh has installed the RF source box and changed the cable configuration somewhat,
the demodulation phase for the MC locking became off by about 10 degree.
I changed the length of some cables and obtained a good demodulation phase by the same technique as Suresh and Koji did before (see here for detail).
I maximized the Q signal. The lock of the MC looks healthy.
RF Source box has been mounted in the 1X2 rack.
First, I disabled front end starts on boot up, and brought c1sus up. I rebuilt the models for the c1sus computer so they had a new specific_cpu numbers, making the assumption that 0-1 were one real core, 2-3 were another, etc.
Then I ran the startc1SYS scripts one by one to bring up the models. Upon just loading the c1x02 on "core 2" (the IOP), I saw it fluctuate from about 5 to 12. After bringing up c1sus on "core 3", I saw the IOP settle down to about 7 consistently. Prior to hyper-threading it was generally 5.
Unfortunately, the c1sus model was between 60 and 70 microseconds, and was producing error messages a few times a second
[ 1052.876368] c1sus: cycle 14432 time 65; adcWait 0; write1 0; write2 0; longest write2 0
[ 1052.936698] c1sus: cycle 15421 time 74; adcWait 0; write1 0; write2 0; longest write2 0
Bringing up the rest of the models (c1mcs on 4, c1rfm on 5, and c1pem on 6), saw c1mcs occasionally jumping above the 60 microsecond line, perhaps once a minute. It was generally hovering around 45 microseconds. Prior to hyper-threading it was around 25-28 microseconds.
c1rfm was rock solid at 38, which it was prior to hyper-threading. This is most likely due to the fact it has almost no calculation and only RFM reads slowing it down.
c1pem continued to use negligible time, 3 microseconds out of its 480.
I tried moving c1sus to core 8 from core 3, which seemed to bring it to the 58 to 65 microsecond range, with long cycles every few seconds.
I built 5 dummy models (dua on 7, dub on 9, duc on 10, dud on 11, due on 1) to ensure that each virtual core had a model on it, to see if it helped with stabilizing things. The models were basically copies of the c1pem model.
Interestingly, c1mcs seemed to get somewhat better and only taking to 30-32 microseconds, although still not as good as its pre-hyper-threading 25-28. Over the course of several minutes it was no longer having a long cycle.
c1sus got worse again, and was running long cycles 4-5 times a second.
At this point, without surgery on which models are controlling which optics (i.e. splitting the c1sus model up) I am not able to have hyper-threading on and have things working. I am proceeding to revert the control models and c1sus computer to the hyper-threading state.
1) Turn off MC1, MC2, MC3, BS, ITMX, ITMY, PRM, SRM watchdogs.
2) Turn c1sus computer off (sudo shutdown now)
3) Go connect monitor and keyboard to c1sus. Turn c1sus on.
4) Hit "del" key at the right time to go to setup (BIOS).
5) Go to BIOS advanced tab, CPU options, enable Multi-threading.
6) Hit F10 to save and let the computer continue booting.
Once c1sus was up, I noticed several red lights and dead keep alives for the c1sus models.
Typing dmesg on c1sus revealed many messages like:
[ 107.583420] c1x02: cycle 33737 time 20; adcWait 10; write1 0; write2 0; longest write2 0
[ 107.583771] c1x02: cycle 33760 time 19; adcWait 11; write1 0; write2 0; longest write2 0
This indicates the Input/Output Processor (IOP) is not completing its duties within the 15 microseconds (1/64 kHz) that it has. These lines indicate its take 20 or 19 microseconds. (I saw messages ranging from 16 to 22 microseconds).
So this seems to agree with Rolf's observations that hyperthreading can cause a 5-10 microsecond increase in computation time.
So the next thing to do is modify which core the codes are running on, and try to get them paired up on the same physical core.
RF Distribution box has been mounted in the 1Y2 rack and is ready for use.
The box receives 11 and 55 MHz Demod Signals from the RF source located in the 1X2 rack.
Heliax cables have been directly attached to the box and anchored on the side of the 1X2 rack. Here is a list of Helix cables which have been connected so far.
On the back side of 1Y2 rack I found a cable, CAB-1X2-LSC_7, which is supposed to be connected to the whitening filter was disconnected.
I plugged it back and confirmed that the whitening filter is under control of EPICS.
Now all the gain sliders seem to be working because I can change the amplitude of signals with the sliders.
To check if the gain sliders are working or not, I intentionally disconnected all the inputs to the whitening filter.
Then I brought a gain slider of interest to the maximum. Due to the big gain I was easily able to see noise lying above ADC noise.
Also if the gain slider is 0 dB, which is the minimum value, the spectrum becomes just ADC noise.
In this way I checked all the gain sliders from PD1 to PD4. The picture below is just an example screenshot when I was doing this test.
Note that each filer is designed to have two poles at 150 Hz and two zeros at 15 Hz.
While checking whitening filters on the LSC rack, I found some epics controls for the whitening looked not working.
So I powered two crates off : the top one and the bottom one on 1Y3 rack.
These crates contain c1iscaux and c1iscaux2. Then powered them on. But it didn't solve the issue.
I worked on AS_11 today. Its ready for its noise / optical gain calibrations. I have left it on Suresh's desk.
This was one of the 24.5 MHz Black Box (Ben Abbott) style RFPDs rescued from LLO. The tunable inductor that was installed was too small to get the frequency down to 11 MHz and so I swapped in one of the shielded, ferrite core ones from our '7mm' CoilCraft kit. It had a range of 1.2 - 1.8 uH according to the datasheet.
I wasn't able to simulataneously get the peak at 11.06 MHz and the notch at 59.3 MHz and so I took Koji's advice and tuned the peak best. The plot above shows how the notch is slightly off. I think its not a problem; to get it better we would have to change out the inductor for the "2-omega" notch, but I was too lazy. The thinking is that its more important to have the gain be symmetric around the signal readout frequency so as to not imbalance the audio sidebands.
Since this one is going to be AS_11, we think that the 22 MHz signal will be tiny: the transmission of the 11 MHz sidebands to the dark port is small. If we later want to put in a 22 MHz notch anyway, there is space to do this via the 'active notch' pads around the MAX4107.
For the above plot, I used the Jenne laser. The DC output of the PD was ~30 mV (~0.6 mA). The RF drive to the laser was -10 dBm: no saturations. I have calibrated out the cable responses, but not using the 1811 setup, so the absolute calibration has yet to be done.
Also, it needs some new stickers. It would be handy if someone can figure out how to get some sheets of stickers that we can put into the printer. Then we can laser printer all of the data onto the stickers and stick them to the RFPD box.
POX11 (see this entry) is now listed as REFL11 (on the very top row).
We will rename POY11 to POP11 for DRMI locking.
Figure.1 I-Q relative phase measurement as a function of LO power.
Blue curve : relative phase of AS55 that I have modified today (#4572).
Red curve : relative phase of AS11 that I had modified a week ago (#4554). Just for comparison.
The relative phase of AS55 agrees approximately what we expected according to the datasheet of PSCQ-2-51W. We expected 85 degree.
Figure.1 I-Q amplitude imbalance as a function of LO power.
From - 5 dBm to 5 dBm in LO power the imbalance is within 3 %.
But the precision of the measurement is also about 2 % (because I used an oscilloscope). Even so the imbalance is still good.
Some plots will be posted later.
A new 90 deg splitter, PSCQ-2-51W, has been installed on another demod board called AS55.
It shows a reasonably close 90 degree separation between the I and Q signals at 55 MHz with various LO and RF power.
So far we have ordered only three PSCQ-2-51Ws for test. Now we will order some more for the other demodulators.
Some plots will be posted later.
I used the Jenne AM laser to tune up the PD (used to be POX_11 but now is called REFL_11). In addition to the notch at 22 MHz, I have also put in a LC notch at 5*f = 55.3 MHz. The transfer function below shows the RF OUT of the PD v. the drive to the laser. I didn't divide out by the 1811 because its not on the EE bench.
The performance plots for POX_11 in the wiki are horrendous and the schematic is missing.
I opened up the box and found all kinds of horrors. There were multiple tunable parts and a flurry of excess nonsense.
The top 2 worst offenders:
1) The main tunable inductor was busted. I removed it and found that the coil was open. Too much indelicate soldering in its vicinity had melted the wire. Someone had put extra inductors and capacitors around it to make it seem as if the PD was working fine, but the noise performance was off by a factor of ~100.
2) The MAX4107 had a 1.4k series resistor. This make the output go through a 1450/50 voltage division which is not nice for the SNR. I removed it.
I then struggled for awhile to get a sensible response. It turned out that the TEST IN input was not giving me a sensible TF. Jenne and I fired the Jenne laser at it and found that the 11 MHz main resonance is there. In the morning I'll finish this off and post more results. I think its going to end up being fine.
40m wiki seems to have been down for quite a while now but I can't see any info in the elog about it. Is there some ongoing problem?
There was an email from Dave Barker about this. They had to reorganize the DNS at LHO. The URL that should be used is: http://blue.ligo-wa.caltech.edu:8000/40m
Thanks Jamie, I've updated the links from the ATF wiki to reflect this.
Nope. I know I had the right address, and it was down for me too all weekend. It's better now though. blue.ligo-wa.caltech.edu was up though.
To design a new resonant EOM box I started reviewing the prototype that I've built.
As a part of reviewing I checked an important thing that I haven't carefully done so far :
I compared the measured input impedance with that of predicted from a circuit model. I found that they show a good agreement.
So I am now confident that we can predict / design a new circuit performance.
* * * (input impedance) * * *
Performance of a resonant circuit is close related to its input impedance and hence, in other words, determined by the input impedance.
Therefore an investigation of input impedance is a way to check the performance of a circuit. That's why I always use impedance for checking the circuit.
The plot below is a comparison of input impedance for the measured one and one predicted from a model. They show a good agreement.
(Note that the input impedance is supposed to have 50 Ohm peaks at 11, 29.5 and 55 MHz.)
* * * (circuit model) * * *
To make the things simpler I assume the following three conditions in my model:
1. inductor's loss is dominated by its DC resistance (DCR)
2. capacitor's loss is characterized only by Q-value
3. Transformer's loss is dominated by DCR and its leakage inductance
All the parameters are quoted from either datasheet or my measurement. The model I am using is depicted in the schematic below.
Basically the Q-vaules for the capacitors that I used are quite low. I think higher Q capacitors will improve the performance and bring them to more 50 Ohm.
Amplitude imbalance between I and Q in a demod board, AS11, with the new 90 deg splitter was measured.
It shows roughly 10% amplitude imbalance when the LO power is in a range from 0 to 5 dBm. Not so bad.
With the handmade coil there used to be a huge imbalance (either I or Q goes to zero volt while the other keeps about 1 V rms) as the LO power decreases.
But with the new 90 deg splitter now there are no more such a huge imbalance.
The remaining 10 % imbalance possibly comes from the fact that we are using ERA-5 in each I and Q path. They may have such gain imbalance of 10%.
We should check the ERA-5 gains so that we can confidently say ERA-5 causes the amplitude imbalance.
Then our plan replacing the ERA-5s (see here) will sound more reasonable.
The new 90 deg splitter works better.
I will also measure amplitude unbalances between I and Q.
RF Amp operating temperature
Earlier measurement reported by Alberto in LIGO-T10004-61-v1 based on the LM34 temperature sensor were lower than that shown by placing a calibrated thermocouple sensor directly on the heat sink by about 5deg C. The difference probably arose because the LM34 was located on a separate free-hanging copper sheet attached to the RF Amp by a single screw, resulting in a gradient across the copper strip. I tried to move the LM34 which was glued down, but broke the leads in the process. I then replaced it with another one mounted much closer to the heat sink and held it down with a copper-strip clamp. There is no glue involved and there is heatsink compound between the flat surface of the LM34 and the heatsink. Picture attached.
The picture also shows the new filters which have been put in place to reduce the harmonics. Note that the SBP-10.7 which was to go on the 11 MHz Demod output is located much farther upsteam due to space constraints.
As seen in the previous measurement the first harmonic of both the 11 MHz and 55 MHz outputs are about 30dB
higher than desired. In an attempt to attenuate these and higher harmonics I introduced SBP-10.7 filters into
the 11MHz outputs and SLP-50 filters into the 55 MHz outputs.
Then I measured the height of the harmonics again and found that they were suppressed as expected. Now harmonic
at 22 MHz is 58dB lower than the 11 MHz fundamental. And the 110 MHz is lower by 55 dB compared to the 55 MHz
fundamental. None of the higher harmonics are seen => they are below 70dB
SLP-50 has an insertion loss(IL) of 4.65 dB and Return Loss(RL) of 3dB. It would be better to use SBP-60
(IL=1.4 dB and RL=23dB)
The filter on the 11 MHz lines is okay. The SBP-10.7 has IL=0.6 dB and RL=23 dB.
Restarted the elog with the script.
A less LO power dependence on the relative phase was found. The new 90 deg splitter works better.
From -3 dBm to 10 dBm in LO power, the relative phase is within 90 +/- 5 deg.
As a comparison I plot the phase that I measured when the handmade coil had been there (green curve in the plot).
A 90 degree splitter, PSCQ-2-51W, has arrived today and I installed it on a demod board called AS11.
Results of the I-Q phase measurement with the new splitter will be reported soon.
A new 90 degree splitter, PSCQ-2-51W, has arrived today and I installed it on a demod board called AS11.
* Picture 1 = before removal of the handmade coil
* Picture 2 = after removal of the coil and the associated capacitors
* Picture 3 = after soldering PSCQ-2-51-W
First of all we will replace the home-made 90 degree splitter (see this entry) by a commercial splitter, PSCQ-2-51-W+ from Mini circuit. This is the step 1 basically.
The east side window guides will be replaced by one long U-channel. There will be drilling into 2x2 steel frame. It should be done by 2pm today
This should remove the jerking motion of windows hitting the individual guides.
The installation went smoothly. There will be no more banging the doors into guides on the east side.
Atm2 showing the west side as is today
The anti aliasing box was opened up at the back to accommodate the junction board and the SCSI cable towards the ADC. Aluminum plate was attached to the bottom to hold the strain relief clamp.
Three more hanging junction cards will be replaced in this manner.
New right angle PVC, 2 x 2 x 1/4" installed at the AP table to strain relief the 1/4" spiral corrugated RF coaxes.