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Magnitude    4.0
Date-Time    * Friday, April 24, 2009 at 03:27:50 UTC
             * Thursday, April 23, 2009 at 08:27:50 PM at epicenter 
Location     33.910°N, 117.767°W
Depth	     0 km (~0 mile) (poorly constrained)
Region	     GREATER LOS ANGELES AREA, CALIFORNIA
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 I've seen this before. At that time, the problem was gone spontaneously the next day.

You could stop just before the offset reaches zero and then try to slowly reduce the offset manually to see where is the threshold.

Koji, Yoichi

The inner and outer screw holes of the EQ stop Jenne is talking about are shown in the photo below.

 Since we had a similar trouble with the DAC at CLIO, I checked if this problem comes from the same origin.

The origin of the problem we had was that although the board was sold as 16 channel DAC, the firmware was set to use only 8ch.

To see if this problem exist in the DAC boards of c1sus, I added the following code to the /cvs/cds/caltech/cds/advLigoRTS/src/fe/map.c

printk("DAC ASSC = 0x%x\n",dacPtr[devNum]->ASSC);

in the definition of mapDac() function.

This code prints the information of the ASSC (Assembly Configuration) register of the PMC66-16AO16 board as a kernel message at the start up time of the realtime code. You can check the message with dmesg command.

After the modification, I recompiled the c1sus and installed it.

make c1sus; make install-c1sus

After starting c1sus, I checked the dmesg. Then found that the ASSC register was set to 0x130006. To decipher this magic number, you have to consult with the manual of the DAC, which is available online.

http://www.generalstandards.com/view-products.php?product=pmc66-16ao16

The manual says the 17th and 18th bits of this number set the number of channels. Those bits are 11 for 0x130006. According to the manual, 11 means 16 channels are present. So it seems that the ASSC register is correctly set. In the case of CLIO, the ASSC register was 0x110003, meaning only 8 channels are present.

Unfortunately, the ASSC register was not the cause of the problem, but at least this possibility was checked.

I added COMSOL example files to the 40m svn to demonstrate how to make transfer function measurements in COMSOL.

https://nodus.ligo.caltech.edu:30889/svn/trunk/comsol/MechanicalTF/

The directory also contains an (incomplete) explanation of the method in a PDF file.

inline cdsToggle /opt/rtcds/caltech/c1/userapps/release/cds/common/src/cdsToggle.c

void cdsToggle(double *in, int inSize, double *out, int outSize){
  static double x = 0;
  static double y = 0;

  if (*in != y){
    y = *in;
    if (y == 1){
      x = (x == 1) ? 0 : 1;
      *out = x;
    }
  }
}

Yoichi, Rana

Here is the open loop gain of the XARM loop.

The reference is from the pre-upgrade era. We get the extra phase delay because we have two anti-aliasing filters. One is the hardware filter at about 7kHz for 16kHz sampling. This filter should have been replaced to the one for 64kHz sampling but it has not yet happened. The second one is the software anti-aliasing filter applied when down sampling from 64kHz to 16kHz. So we have double AA filters, which are the culprits for the extra phase delay.

We should either replace the hardware AA filter to the 64kHz one (preferred way), or change the software AA filter to a less aggressive one (easier temporary fix).

Yoichi, Rana

Here is the noise spectrum of the X-arm error signal along with the TRX DC power fluctuations.

The spectra were taken while the whitening filters for POX11 were OFF.

EDIT (Integrity Fairy): Shall we assume these units are "Intergalactic translational qubits/sqrt(Hz)"?

 I started working on the characterization of the MC servo.

The current MC servo topology is shown in the figure attached along with a simplified schematic diagram of the MC board. 

A usual way to measure the open loop gain of this servo is to inject a signal from, say, EXCA of the MC board and measure the transfer function from TP2A to TP1A. It works OK at frequencies around the UGF. The second attachment is the OPLTF measured in this way with the Agilent 4395A. The UGF is about 100kHz with the phase margin of 40 to 50 deg. 

Now we have two issues here. First, I expected the UGF to be more than 100kHz, like 300kHz or so. The phase babble is peaked around 100kHz. According to our old measurement (http://nodus.ligo.caltech.edu:8080/40m/1431) the phase babble peak was at a much higher frequency when the FSS was using the reference cavity. One reason could be that the MC is located much farther from the laser than the reference cavity, so that there is some phase lag caused by the time delay. I will make a model of the MC servo system later to check this theory.

The second issue is that, as you can see in the plot, the OPLTF measurement becomes noisy at lower frequencies. With 4395A, which has the minimum IFBW of 2Hz, OPLTF measurement below 10kHz was impossible with the traditional method. We could use SR785 with a long averaging time to improve the SNR, but it requires a patience which I don't have.

The measurement becomes difficult at low frequencies because the loop gain is too high. When the open loop gain (G) is high, the injected signal (x) from EXCA is immediately suppressed by a factor of 1/(1+G) at TP2A. This makes the injected signal hidden in other noises at TP2A.

How do we solve this problem ? Let's consider a simple servo model shown in the third attachment. A traditional OPLTF measurement is done by injecting a signal from EXC port and measuring the TF from TP2 to TP1. The problem was that at TP2, the signal is attenuated by 1/(1+G1*G2), which is too much when G (=G1*G2) is large. However, at TP3, the attenuated signal is amplified by G1. So the injected signal x becomes x*G1/(1+G) at TP3. If G1's contribution to the overall gain G is large enough,  the signal at TP3 is not so small. Then we can easily measure G2 using TP3 and TP1. In a typical situation, G1 is the transfer function of the electric circuits, which we can know either from standalone measurements or from model calculations, and G2 is an interferometer response, which we want to measure. So, by combining the knowledge of G1 and the measurement of G2, we can obtain the overall loop gain G even at lower frequencies.

 The final attachment shows an example of the measurement of G2. In our case, this is the transfer function from MC_Out_Mon to Q-Mon (see the first attachment) . G1 is the transfer function of the MC board. Since G1 is large at low frequencies, we can measure G2 down to 100Hz with a reasonable integration time (10000 cycles per point).

Last night, I took a bunch of TFs with this method. Now I'm analyzing the data to recover the overall gain G. I will post the results later.

 I calculated the MC open loop transfer function with the combination method. For that, I made a circuit model of the MC board (from the input to the output). The transfer function of this circuit is calculated by SPICE (attachment1). Then it is multiplied by the measured transfer function from the output of the MC board to the input of the MC board (attachment 2) to get the overall transfer function.

The result is shown in the attachment 3. The blue curve is the OPLTF measured with the traditional method. The red curve is the combination method described above. There are some discrepancies between the two curves. The ratio of the two curves (Traditional)/(Combination) is plotted in attachment 4. It seems there is a pole(s) missing from my model of the MC board at around 1MHz. This may come from the omitted op-amps in the MC board model (there are so many op-amps which have flat responses below 1MHz and I omitted most of those). Also the MC board includes many generic filter stages to customize the frequency response. I will open the MC board box to examine what is actually implemented on the board. 

At low frequencies, the two curves are similar but the slope is still different.

I also had to add 83dB of gain to the combined TF to match with the traditional one. I will check where does it come from.

The MC board model (Altium project) is attached as attachment 6. The schematic is attachment 5.

 I took out the MC board. Unfortunately, most of the components are surface mounted. So the values of the capacitors are not legible.

I will try my best to guess what is implemented on the board.

 I noticed that the IFO restore scripts have some problems. They use burt request files to store and restore the settings. However, the request files contain old channel names.

Especially channels with _TRIG_THRES_ON/OFF are now _TRIG_THRESH_ON/OFF, note the extra "H".

These scripts reside in /opt/rtcds/caltech/c1/burt/c1ifoconfigure/.

I fixed the PRMI_SBres and MI scripts. Someone should fix all other files.

Tonight, I worked on the X-arm locking again. I did not have any significant progress, but observed several issues and will give some suggestions for future work here.

What I did tonight was basically re-alignment of the X-arm (because Rana touched the PZT mirrors for the Y-arm alignment, the X-arm alignment was screwed up). Then I measured the open loop gain. Of course it was almost identical to the one posted in this entry. It reminded myself of how small the phase bubble is. This means we have to finely adjust the gain to set the UGF at the right frequency, i.e. 100Hz. So I decided to do the signal normalization using the TRX power. Using the MC path method described here,  the appropriate normalization coefficient was determined to be 1.6, when the XARM gain is set to 0.05. Using burtgooey, I updated the burt snapshot used by the X-arm restore script.

Now I observed the following things:

When the normalization is used, the lock itself is stable, but the lock acquisition takes loner (i.e. fails more often).

I don't know the exact reason, but here is my guess: Usually, the error signal is divided by the square root of the transmitted power to widen the linear range of the PDH error signal. However, what I'm doing here is dividing the error signal with the power itself, not the sqrt. This might distort the error signal in a not-friendly-for-lock way ? I don't know.

I checked the c1lsc FE code. There seems to be the sqrt(TRX) and sqrt(TRY) signals computed in the code. However, these are not used for the normalization. 

Now, there are two requirements. When dragging the mirrors into the resonance, we want to normalize the error signal with sqrt(TRX). When the mirrors reach the resonance, the gain of the loop must be normalized by TRX. How do we smoothly connect those two states ? Someone should spend some time on this. Maybe I will work on this in Japan.  

We really need a time delay in the filter trigger

The automatic filter trigger is awesome. However, the [0^2:5^2] filter, which is an integrator, takes time to switch on and off. Every time the cavity passes by a resonance, this filter gets turned on and off slowly, giving some large transients. This transient combined with the bad coil balance of ETMX sometimes made the optical lever of ETMX crazy. This can be avoided by turning on this filter a few seconds after the power reaches the threshold. As Rana suggested, we should be able to put an arbitrary time delay to the filter trigger.

Someone should balance the coils

The coil balance of ETMX is bad and causing the above mentioned problem. I tweaked the coil balance by injecting a sinusoidal signal (10Hz) into ETMX pos and trying to minimizing the spectral peak in the optical lever signals. Of course, this is a cheesy work. Someone should put more serious effort on this.

A civilized interferometer should have an auto-alignment capability

After my alignment work, the X-arm power got to about 0.7. (This is probably because the MC transmission power has been low for the past 5 hours or so (attachment 1)).

In anyway, after the cavity locked to the TEM00 mode, the alignment has to be automatically improved by dithering. It is anachronism to sit down and click on the MEDM screen until the power gets big enough.