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ID Date Authorup Type Category Subject
  1409   Thu Mar 19 02:45:36 2009 YoichiConfigurationIOOA loose wire found for MC1
I found a loose connection of a wire in the cross-connect between an ADC and the MC1 coil driver's UL bias input.
I tightened it.
To see if this fixes the MC1 drift problem, I will do another round of MC1 drift measurement.
You can lock the MC if you need to use the IFO but please note it in the elog.

Thanks.
  1410   Thu Mar 19 10:45:43 2009 YoichiConfigurationIOOA loose wire found for MC1
I attached a 6-hour trend of the MC mirror OSEM signals with the MC unlocked.
The drift of the MC1 is within 20 counts (0.6um in terms of each OSEM).
This is comparable to the other MC mirrors.
Attachment 1: AfterWireFix-1.pdf
AfterWireFix-1.pdf
  1412   Fri Mar 20 12:07:19 2009 YoichiConfigurationASCETMY beam centering
I forgot to put this in the elog.
Last Sunday night, I centered the beam on the ETMY because it was too low.
To do so, I wrote scripts (beamCenterETMY-P and beamCenterETMY-Y) to continuously align the Y-arm while I'm moving the beam on the end QPD.
These scripts will continuously do the dithering servo and QPD centering in one direction (pitch for beamCenterETMY-P, yaw for the other).
So if you move the steering mirror in front of the end QPD, the servo will eventually move the beam spot on the ETM.
I centered the beam just by looking at the camera image.
No coupling measurements from Pitch/Yaw to length was done.
  1419   Tue Mar 24 03:05:25 2009 YoichiUpdateLockingLocking tonight
MC1 issue:
The MC1 seems to be drifting still. I found it was off from the SUS drift-mon reference values and restored the alignment using the SUS drift-mon before I went home for dinner.
But when I came back being happy with the Japanese victory over S-Korea at the WBC final, the MC was unhappy again.
I restored the alignment of the MC1 using the SUS drift-mon once again and centered the WFS QPDs.
I will leave the MC unlocked again tonight to see the drift. You are welcome to lock the MC in the morning as I will have corrected enough data by the time people come in.

Computer overloads:
I removed some filters from suspensions to off load susvme computers.
Nonetheless, both susvme1 and susvme2 are still over loaded during the dither alignment. The alignment results are in general ok. So this is not a too serious problem.
But still it would be nice to resolve.

3.8kHz hunting:
I made several measurements of the AO path loop gains (using the SR785) and the transfer functions from the CARM excitation (actuation to the ETMs) to the PO_DC signal as the arm powers are increased.
There is a similar structure as in the AO loop found also in the CARM->PO_DC transfer functions. This implies that the problem is likely to be in the PO_DC sensor not in the MC->VCO actuator. But the MC and the VCO could still be the
cause of the problem because they were in the control loop when the CARM->PO_DC TF were measured.
The peak frequency does not seem to depend on the arm power, but the conclusion is not definite because I was only able to measure the TFs from arm power 5 to 10 (not much difference).
I will make plots and post them later.

To Do for tomorrow:
Tonight the CARM error signal was noisier than the reference spectra (broad band white noise appeared). I should check the beam centering of the SPOB PD.
Also someone should center the oplevs of the mirrors as some of them are off.
Continue to measure the TFs at various power levels.
Try to put another (Thorlabs?) PD at the POB port to get PO_DC from it.
  1426   Wed Mar 25 04:18:28 2009 YoichiUpdateLockingTuesday Locking
After the new PO_DC PD was installed, I tweaked several gains to make the locking scripts work right.
First of all, I increased the gain of PD12 (PD12_I is SPOB) by a factor of 1.4 to compensate for the power decrease
by the insertion of the BS. SPOB is used by the PRM alignment script. I was too lazy to modify the scripts.

Then I optimized the SRC DD signal which is taken from the POB.

I also had to do some gain adjustments for the CARM loop.

The attachment (AO path open loop TF) shows a depressing fact that the 3.8kHz peak is still there with the new PO_DC PD. So it was not a problem of the SPOB PD.
Next, I will check the cross over frequencies of the PZT and PC paths in the FSS and the VCO/MCL cross over.
Attachment 1: AO-Loop-p9.png
AO-Loop-p9.png
  1428   Wed Mar 25 17:22:58 2009 YoichiUpdateIOOMC lock without FSS
I made 40k:4k passive filter in a POMONA box and connected it to IN1 (not TEST IN1) of the FSS box.
With this modification and cut-and-tries with the gain sliders, I was able to lock the MC with 80kHz bandwidth by feeding back directory to the laser frequency.
The attached figure shows the open loop transfer function.
The phase margin is thin at 80kHz. Because of this, I could not turn on the MC super boost filters.
But I believe that we can increase the gain further by modifying the filter shape.

I used the following settings:
[MC Board]
C1:IOO-MC_REFL_GAIN 14
C1:IOO-MC_REFL_OFFSET -4.2381
C1:IOO-MC_BOOST1 0   (You can turn it on if you want, but turn it off for locking)
C1:IOO-MC_BOOST2 0
C1:IOO-MC_POL 1   (Minus)
C1:IOO-MC_VCO_GAIN 4
C1:IOO-MC_LIMITER 1 (Disable)

[FSS box]
C1:PSL-FSS_SW1 0 (Test1 ON)
C1:PSL-FSS_INOFFSET 0.1467
C1:PSL-FSS_MGAIN 30
C1:PSL-FSS_FASTGAIN 14 (Do not increase it, at least while locking. Otherwise the phase lag from the PZT loop gets significant and the MC loop will be conditionally stable).
I also turned down the FSS slow servo's RC transmission threshold to zero so that the slow servo works even without the RC locked.
Attachment 1: MC-loop-gain.png
MC-loop-gain.png
  1431   Thu Mar 26 04:01:24 2009 YoichiUpdatePSLFSS Open Loop Gain
Yoichi, Peter, Jenne

Attached is the open loop transfer function of the FSS as of today with the common gain = 12dB and the fast gain = 16dB.
The UGF is only 250kHz. If we increase the common gain, the PC goes crazy. Exactly the same symptom as before I fixed the oscillating op-amp.

I wanted to check the cross over frequency but there is no excitation point in the fast path nor PC path. Therefore, it is not easy.
Attachment 1: OpenLoopTF.png
OpenLoopTF.png
  1432   Thu Mar 26 04:09:38 2009 YoichiUpdateIOOSingle X arm lock spectra with different MC lock schemes
The attached plots show MC_F, FSS_FAST_F and XARM IN/OUT spectra with different MC locking modes.
The conventional locking means the FSS is used. The direct frequency lock is the new way.
You can see that at low frequencies, the frequency actuator is working hard to suppress the MC pendulum motions.
The X-arm also sees a lot of frequency noise at low frequencies because of this.
The transmitted power of the X-arm fluctuates a lot making it difficult to align the mirrors.

The zoomed plots show that the structures in the kHz band are also present in the case of the direct frequency lock, although the frequencies are somewhat different.
Attachment 1: XarmSpectra.pdf
XarmSpectra.pdf
Attachment 2: XarmSpectraZoom.pdf
XarmSpectraZoom.pdf
  1433   Thu Mar 26 04:27:26 2009 YoichiUpdateLocking3.8kHz peak as a function of the arm power
During the power ramp-up, I actuated CARM using ETMs and measured the transfer functions to the PO_DC at several arm powers.
The peak grows rapidly with the power. It also seems like the frequency shifts slightly as the power goes up, but not much.

Some sort of an RSE peak ? An offset in the PRC lock point ?
Attachment 1: CARM-PODC.pdf
CARM-PODC.pdf
  1436   Fri Mar 27 02:50:54 2009 YoichiUpdateLockingDD demodulation phase suspicious
I noticed that the gain of PD6_Q (before the phase rotation) was 0 whereas PD6_I gain was 15.
This means the demodulation phase of the PD6 had no meaning other than changing the gain.
According to the conlog, it has been zero since March 2nd. I don't know how it happened.

While I was re-adjusting the DD phase, the MC started to unlock frequently (every 10 minutes or so).
MC1 is again drifting a lot (it is getting step-function like alignment changes intermittently).
This practically made it impossible to work on locking. So I decided to fix the MC first.
See Peter's elog entry for the MC work.
  1437   Fri Mar 27 15:05:42 2009 YoichiUpdateIOOMC glitch investigation
Attached plots are the result of the MC1 trend measurement.
See the attachment #1. The first two plots show the drift of the MC1 alignment as seen by the OSEMs. It is terrible. Other MC mirrors also drifted but the scale is smaller than the MC1.
From the VMon channels, you can see that the control voltages were quiet.
 
The monitor channels we added were:
 
MC_TMP1 = UL coil bias. Input to the coil driver board.
MC_DRUM1 = UL coil bias. Output of the current buffer.
OSA_APTEMP = LR coil bias. Input to the coil driver board.
OSA_SPTEMP = LR coil bias. Output of the current buffer.
 
The bias voltages show no drift except for a glitch around 7AM. This glitch did not show up in the SPTEMP channel (LR coil bias output). This was because the probe was connected to the coil side of the output resistor by mistake.
 
The second attachment shows a zoomed plot of MC1 OSEM signals along with the bias monitor channels (signals were appropriately scaled so that they all fit in +/-1).
There is no correlation between the OSEM signals and the bias voltages.
 
Since we were only monitoring UL and LR coils, I changed the monitor points as follows.
 
MC_TMP1 = LL coil bias. Output of the current buffer.
MC_DRUM1 = UL coil bias. Output of the current buffer.
OSA_APTEMP = UR coil bias. Output of the current buffer.
OSA_SPTEMP = LR coil bias. Output of the current buffer.
 
I will leave the MC unlocked for a while.

Quote:

Yoichi, Pete

The MC loses lock due to glitches in the MC1 coils. 
We do not know which coil for sure, and we do not know if it is a problem going into the board, or a problem on the board. 
We suspect either the UL or LR coil bias circuits (Pete would bet on UL).  If you look at the bottom 4 plots in the attached file, you can see a relatively large 3 minute dip in the UL OSEM output, with a corresponding bump in the LR (and smaller dips in the other diagonal).  
These bumps do not show up in the VMONS which is why we are suspicious of the bias.
To test we are monitoring 4 points in test channels, for UL and UR, both going into the bias driver circuit, and coming out of the current buffer before going into the coils. 
 

We ran cable from the suspension rack to the IOO rack to record the signals with DAQ channels.

The test channels:

UL coil      C1:IOO-MC_DRUM1  (Caryn was using, we will replace when we are done)

UL input   C1:IOO-MC_TMP1 (Caryn was using, we will replace when we are done)

LR coil      C1:PEM-OSA_SPTEMP

LR input   C1:PEM-OSA_APTEMP

We will leave these overnight; we intend to remove them tomorrow or Monday.

We closed the PSL shutter and killed the MC autolocker.

 

Attachment 1: MC1_Drift.pdf
MC1_Drift.pdf
Attachment 2: MC2_Drift.pdf
MC2_Drift.pdf
  1438   Fri Mar 27 17:52:16 2009 YoichiUpdateIOOMC glitch investigation
Per Rob's suggestion, I put the probes across the output resistors of the bias current buffers instead of measuring the output voltage with respect to the ground.
This way, we can measure the current flowing the resistor. The change was made around 17:30.

Quote:
Attached plots are the result of the MC1 trend measurement.
See the attachment #1. The first two plots show the drift of the MC1 alignment as seen by the OSEMs. It is terrible. Other MC mirrors also drifted but the scale is smaller than the MC1.
From the VMon channels, you can see that the control voltages were quiet.
 
The monitor channels we added were:
 
MC_TMP1 = UL coil bias. Input to the coil driver board.
MC_DRUM1 = UL coil bias. Output of the current buffer.
OSA_APTEMP = LR coil bias. Input to the coil driver board.
OSA_SPTEMP = LR coil bias. Output of the current buffer.
 
The bias voltages show no drift except for a glitch around 7AM. This glitch did not show up in the SPTEMP channel (LR coil bias output). This was because the probe was connected to the coil side of the output resistor by mistake.
 
The second attachment shows a zoomed plot of MC1 OSEM signals along with the bias monitor channels (signals were appropriately scaled so that they all fit in +/-1).
There is no correlation between the OSEM signals and the bias voltages.
 
Since we were only monitoring UL and LR coils, I changed the monitor points as follows.
 
MC_TMP1 = LL coil bias. Output of the current buffer.
MC_DRUM1 = UL coil bias. Output of the current buffer.
OSA_APTEMP = UR coil bias. Output of the current buffer.
OSA_SPTEMP = LR coil bias. Output of the current buffer.
 
I will leave the MC unlocked for a while.

 

 

 

  1440   Sun Mar 29 17:54:41 2009 YoichiUpdateSUSMC1 drift investigation continued
The attached plots show the trend of the MC OSEM signals along with the voltages across the output resistors of the bias current buffers.
The channel assignments are:
MC_TMP1 = LL coil
MC_DRUM1 = UL coil
OSA_APTEMP = UR coil
OSA_SPTEMP = LR coil

Although the amplitude of the drift of MC1 is much larger than that of MC2 and MC3, the shape of the drift looks like a daily cycle (temperature ?).
This time, I reduced the MC1 bias currents to avoid saturation of the ADCs for the channels measuring the voltages across the output resistors.
This may be the reason the MC1 has been non-glitchy for the last day.

OSA_APTEMP (UR Coil) shows a step function like behavior, although it did not show up in the OSEM signals.
This, of course, should not happen.

Today, I went to the MC1 satellite box and found that the 64-pin IDE like connector was broken.
The connector is supposed to sandwich the ribbon cable, but the top piece was loose.
The connector is on the cable connecting the satellite box and the SUS rack.
I replaced the broken connector with a new one. I also swapped the MC1 and MC3 satellite boxes to see if the glitches show up in the MC3.

I restored the bias currents of the MC1 to the original values.

The probes to monitor the voltages across the output resistors are still there. For OSA_SPTEMP, which was saturating the ADC, I put a voltage divider before the ADC. Other channels were very close to saturation but still within the ADC range.

Please leave the MC unlocked at least until the Monday morning.
Also please do not touch the Pomona box hanging in front of the IOO rack. It is the voltage divider. The case is connected to the coil side of the output resistor. If you touch it, the MC1 bias current will change.

Attachment 1: Drift1.pdf
Drift1.pdf
  1442   Mon Mar 30 12:29:17 2009 YoichiConfiguration MC1 glitches not seen during the weekend
The attached is the MC trend for the past 12 hours.
There is no MC1 glitches in the OSEM signals. Moreover, the total amplitude of the drift is smaller than it used to be (now the amplitude is less than 100 but it used to be a few hundreds).
There still is a small step in the OSEM signals at around 6AM this morning, but the amount of the jump is very insignificant.
The cause of the glitch in the TMP1, DRUM1 and APTEMP (LL, UL and UR coils respectively) at 7AM is not known.
Since the MC1 has been behaving OK during the weekend, I removed the probes from the MC1 coil driver board and locked the MC.
Hopefully the replacement of the broken connector fixed the problem, but I'm not sure.
Attachment 1: MC_drift.pdf
MC_drift.pdf
  1443   Mon Mar 30 12:46:36 2009 YoichiConfigurationIOOIOO QPDs were missing the beam
When I re-locked the MC, I wanted to check the trend of the IOO QPDs to see if the input beam pointing has changed.
Then I found that the QPDs were not receiving light.
The attached trend plots show that the QPDs missed the beam on March 23rd.
The IOO-QPD_ANG was installed on Mar 11th by Kiwamu and Kakeru. Since then, they were serving as a reference of the PSL beam pointing.
But there is no record of the past week. This is very bad because then I cannot tell if I should relieve the MC WFS to make the mirrors follow the input beam or not.
I found that someone has moved the beam splitter which picks up the beam going to those QPDs. But there is no elog entry on this around March 23rd.
I re-centered the beam on the QPDs.

Since the X-arm locked to TEM00 with the MC WFS on (i.e. the MC beam axis is following the input beam axis), I guessed that the input beam has not drifted that much. So I relieved the WFS and centered the WFS QPDs.
Attachment 1: IOO-QPDs.pdf
IOO-QPDs.pdf
  1444   Mon Mar 30 13:29:40 2009 YoichiUpdateSUSMC1 drift investigation continued

Quote:
Maybe we can temporarily just disconnect the bias and just use the SUS sliders for bias if there's enough range?


We could do this, but I'm suspicious of the cables between the coil driver and the coils (including the satellite box). In this case, disabling the bias won't help.
Since the MC1 has been quiet recently, I will just lock the MC and resume the locking.
  1446   Mon Mar 30 17:02:46 2009 YoichiConfigurationGeneralAP OSA aligned
I aligned the AP OSA, which had been mis-aligned for a while.
  1449   Wed Apr 1 15:47:48 2009 YoichiUpdateLocking3.8kHz peak looks like a real optical response of the interferometer
Yoichi, Peter

To see where the 3.8kHz peak comes from, we locked the interferometer with the CARM fed back only to ETM and increased the arm power to 4.
The CARM error signal was taken from the transmission DC (not PO_DC).
The attached plots show the CARM transfer functions taken in this state (called ETM lock in the legends) compared with the ones taken when the CARM is locked by the feedback to the laser frequency (called "Frequency lock").
The first attachment is the TFs from the CARM excitation (i.e. the ETMs were actuated) to the TR_DC and PO_DC signals.

The second attachment is the AO path loop TFs. This is basically the TF from the frequency actuator to the PO_DC error signal.
I injected a signal into the B-excitation channel of the common mode board (with SR785) and measured the TF from TP2B to TP2A of the board.
For the ETM lock case, the AO loop was not closed because I disabled the switch between TP2A and TP1B.

The observation here is that even with no feedback to the laser frequency, the 3.8kHz peak is still present.
This strongly suggests that the peak is a real optical response of the interferometer.

To realize the ETM lock with arm_power=4, I had to tweak the CM loop shape.
I wrote a script to do this (/cvs/cds/caltech/scripts/CM/ETM_CARM_PowerUp).
You can run this script after drstep_bang has finished.
Attachment 1: CARM-ETM-EXC.png
CARM-ETM-EXC.png
Attachment 2: AOpath-TFs.png
AOpath-TFs.png
  1450   Wed Apr 1 16:14:36 2009 YoichiUpdateLocking3.8kHz peak does not change with SRC offset
Yoichi, Peter

We suspected that maybe the 3.8kHz peak is the DARM RSE somehow coupled to the CARM.
So we added an offset to the SRC error signal to see if the peak moves by changing the offset.
It didn't (at least by changing the SRC offset by +/-1000).
(I had a nice plot showing this, but dtt corrupted the data when I saved it. So no plot attached.)

I also played with the PRC, DARM offsets which did not have any effect on the peak.
The only thing, I could find so far, having some effect on the peak is the arm power. As the arm power is increased, the peak height goes up and the frequency shifts slightly towards lower frequencies.
  1454   Fri Apr 3 17:20:05 2009 YoichiUpdateLockingThe 3.8kHz peak seems like the DARM RSE (not 100% sure though)
Yoichi, Kentaro,

Last night, we took several measurements of the AO path loop TFs with various offsets/demod. phases tweaked.
The first attachment shows the AO path loop TF as a function of the offset (in counts) added to the DARM error signal.
Though it is a bit crowded plot, you can see a general tendency that the peak becomes lower in height and higher in frequency as
the DARM offset goes from negative to positive. Since the peak height also depends on the arm power and it fluctuates during the measurements,
the change is not monotonic function of the offset though.

Being suspicious of the demodulation phase of the DARM error signal (AS166), we scanned it (see the second attachement).
But there is no significant change.
Note that the phase of the TF is 180 degrees different from the first attachment. This is because I changed the measurement point of the returning signal
on the CM board from TP2A to OUT2 to see POX_1I signal as well. These points should give the same signal for PO_DC except for the sign.

We also took the AO path TFs by changing the MICH offset (the third attachment). Again, there is no big change.

With the CARM locked with the PO_DC signal, we took the transfer function from the AO path actuation signal to the response of the POX_1I (4th attachment).
There is a huge 3.8kHz peak.

Finally, we measured the DARM response by exciting the ETMs differentially (the PDF attachment).
The shape of the 3.8kHz resonance looks like the DARM RSE peak.

It is speculated that somehow the DARM RSE resonance is coupled into the CARM loop. Don't know how though.
I'm now working on an Optickle simulation to get an insight into this issue.
Attachment 1: AO-TF-DARM-OFFSET.png
AO-TF-DARM-OFFSET.png
Attachment 2: AO-TF-DARM-DEMOD-PHASE.png
AO-TF-DARM-DEMOD-PHASE.png
Attachment 3: AO-TF-MICH-OFFSET.png
AO-TF-MICH-OFFSET.png
Attachment 4: POX_1I.png
POX_1I.png
Attachment 5: DARM-Loop.pdf
DARM-Loop.pdf
  1457   Tue Apr 7 21:39:57 2009 YoichiConfigurationComputersLSC code recompiled with a fix for denormalization problem
This is not my work but I will put it for the record.

A few days ago, Rob recompiled the LSC code with the fix of the denormalization problem provided by Alex.
Since then, the LSC code has been working fine. I recognize that c1lsc is now less loaded.

I believe Rob only recompiled the LSC code, so there could still be the problem in the suspension controllers.
  1458   Wed Apr 8 02:47:42 2009 YoichiUpdateLockingLocking status
This is a summary of activities in the last few nights, although there is not much progress.

The attachment 1 and 2 show the CARM and DARM responses around 3.8kHz at different arm power levels.
The CARM error signal was PO_DC and the DARM error signal was AS2Q.
The excitations were both applied to the ETMs (I temporarily modified the output matrix so that the unsed XARM filter bank can be used to excite CARM and DARM).
DARM and CARM show very similar behavior as the power goes up.

The third attachment shows transfer functions to various signals from CARM and DARM excitations (ETMs).
Though the plot contains many curves, look at PO_DC curves (green and black).
PO_DC is used as CARM error signal but it has a larger response to DARM than CARM (by 10dB or so).
This is not good.

Although the 3.8kHz problem still exists, tonight I was able to go up to arm power = 80 a couple of times, where we are ready to hand off from PO_DC to the RF CARM signal. The hand off failed. I'm now optimizing the hand off gain, but it is difficult because the interferometer is unstable at this power level.
Attachment 1: CARM_TFs.pdf
CARM_TFs.pdf
Attachment 2: DARM_TFs.pdf
DARM_TFs.pdf
Attachment 3: DARM-CARM-Coupling.pdf
DARM-CARM-Coupling.pdf
  1464   Thu Apr 9 20:56:12 2009 YoichiHowToGeneralRestore the alignment. Write elog entries.
I often find that the mirrors are left mis-aligned (like in X-arm mode) when I come in for the locking, including tonight.
As Rob stated repeatedly in the past elog, leaving the mirrors mis-aligned for a long time without a reason is an abomination.
It will cause a slow drift of the mirrors and the lock acquisition work is severely slowed down as I have to run the alignment script many times.

I also found that the GPIB-Ethernet box (named teofila) was taken away from the SR785 hooked up to the CM board.
I found it connected to Alberto's setup. Instead, another GPIB box was left on the SR785 but not connected.
I couldn't find any elog entry about this.
This is totally unacceptable.
The SR785 has been used as a very important tool for monitoring the AO path loop gain during the power up.
You can use it if you need, but you have to note it in elog.

The other GPIB box left on the SR785 had a wrong name labeled on it. It had a name "ERMINIA", but the IP address written next to the name was actually assigned to "crocetta" in the DNS server on linux1. I don't know who made the label. I put a new and correct label on it.
Now I'm using crocetta for the SR785 so Alberto can keep using teofila.

Anyway, I think recently people are lazy about elog.
Whatever work you did, please put it in the elog even if you think it is trivial.
I also would like to see more detailed elog entries from people. Many of the recent elog entries are too simple or superficial that it is hard for other people to figure out what was really done.
  1469   Fri Apr 10 04:54:24 2009 YoichiUpdateLockingREFL_DC for CARM
Suggested by Rob and Rana's simulation works, I tried to use REFL_DC for the CARM error signal.

My current guess for the cause of the 3.8kHz peak is the following.
The AF sidebands created by the laser frequency drive are reflected by the IFO to the symmetric port if the arms are perfectly symmetric.
However, if there is asymmetry in the arm cavities (such as loss imbalance, ITM transmission difference etc) the sidebands are scattered from the common mode to the differential mode. If our CARM error signal has a large response also to the differential mode (i.e. DARM), the loop is closed. At the DARM RSE frequency, the AF sideband in the differential mode is enhanced and creates a peak in the CARM response.
What Rob's plots show is that PO_DC has a larger response to DARM than REFL_DC has. You can see this from the curves of CARM offset = 0 (black ones).
When the CARM offset is zero, the CARM signal should go to zero. Therefore, the black curves show the residual DARM response. In the case of PO_DC, the black curve is very large suggesting a large DARM coupling.

Now I changed the cabling at the LSC rack to put REFL_DC into the REFL2 input of the CM board.
The REFL_DC signal is put through a 160kHz RC LPF and split to the ADC and the CM board (AC coupled by a large capacitor).
I modified the cm_step script to use PD4_DC as CARM error signal. (The old script is saved as cm_step.podc).
Since the polarity of the REFL_DC signal is opposite to the PO_DC, I flipped the polarity switch of the CM board.
This will flip the sign of the RF CARM signal because this switch flips the polarity of the both inputs.
We have to flip the sign of the RF CARM signal with the SR560 sitting on the LSC rack, which I haven't done yet.

With some tweaks of the gains and addition of two lag-lead filters to PD4_DC, I was able to completely hand off the CARM error signal to REFL_DC.
The attached plot shows the AO path loop gain at arm power = 7. The 3.8kHz is gone, although there is some phase ripple around 3.8kHz.

Since the gain behavior of the REFL_DC is different from the PO_DC, I'm now working on the power up part of the script, adjusting the gains as the power goes up.
Attachment 1: AO-loop-gain-CARM-REFL_DC.png
AO-loop-gain-CARM-REFL_DC.png
  1473   Sat Apr 11 00:45:41 2009 YoichiUpdatePSLPMC LO Calibration

Quote:

I then changed the RF Output Adjust slider in increments of 0.5, and measured the peak-to-peak values on the scope. In the table and on the plots, I've taken into account the 12dB attenuation. i.e I actually measured 964mV, so 964mV*10^.6 = 3838mV.


3.8Vpp is about 16dBm.
The mixer for the PMC demodulator is level 23. So 16dBm is insufficient.
What is the level of the new mixer Steve ordered ? 13 ?
  1474   Sun Apr 12 01:19:30 2009 YoichiConfigurationComputersNew FE codes for suspensions not successful
Alex recompiled the suspension FE codes for c1susvme1 and c1susvme2 to fix the denormalization problem.
The new modules are in
/cvs/cds/caltech/users/alex/cds/rts/src/fe/40m/losLinux1.o
/cvs/cds/caltech/users/alex/cds/rts/src/fe/40m/losLinux2.o

I tried them today, but c1susvme1 did not work with the new code while c1susvme2 seemed to run ok.
So I reverted the modules (losLinux1.o and losLinux2.o) to the original ones.
The original modules are also backed up as losLinux1.o.11Apr09 and losLinux2.o.11Apr09 in the corresponding target directories.

I reported the problem to Alex.
  1480   Tue Apr 14 02:59:02 2009 YoichiUpdateLockingPower up until 26
Yoichi, Peter,

With careful adjustments of the common mode gains, we were able to go up to arm power = 26, sort of robustly (more 50% chance).
At this arm power level, the common mode loop shape still looks good. But the interferometer loses lock easily.
I have to check other DOFs, but the interferometer does not stay locked long enough.
Today, lock losses of the IFO were associated with the lock loss of the PMC whereas the FSS stayed locked.
Probably the AO path got large kicks, which could not be handled by the PMC PZT.

The cause for the IFO lock loss is under investigation.
  1482   Tue Apr 14 17:20:36 2009 YoichiUpdateComputer Scripts / ProgramsParallel Optickle
I wrote a parallel version of tickle() function for Optickle.
The attached ptickle.m, which provides ptickle() command, can be used as a drop-in replacement of tickle() command.
Just download it and place it in the @Optickle directory.
This command will run multiple instances of Matlab to calculate the frequency responses in parallel.
The speed gain is roughly proportional to the number of CPU cores you use.

To use multiple cores, you have to run matlabpool() command first. See the comment at the beginning of ptickle.m for more detail.
The progress bar is disabled at this moment because it is not clear for me how to make a single progress bar from multiple instances of Matlab.

I sent the code to Matt, so this may be included in the next release of Optickle.
Attachment 1: ptickle.m
% Compute DC fields, and DC signals, and AC transfer functions
%
% This is a parallelized version of tickle. You have to run matlabpool(n)
% command before using this command. matlabpool(n) will invoke n instances
% of matlab workers in your computer. Once you have started those workers,
% you can reuse them many times (i.e. you don't have to run matlabpoo(n)
% every time you use ptickle). Usually n should be equal to the number of
% CPU cores in your computer, but the Matlab parallel computing toolbox has
% the limit of maximum 4 workers for a local computer. If you use a cluster 
% of computers across a network, this limit does not apply. But I haven't
... 393 more lines ...
  1492   Thu Apr 16 17:48:00 2009 YoichiConfigurationComputer Scripts / ProgramsAutoDTT
As Peter mentioned in his entry on the last night's locking, I imported AutoDTT from Hanford.
It resides in /cvs/cds/caltech/scripts/AutoDTT/.
The main script is restoreRunSave, which takes three arguments, templete_file_name, result_file_name and log_file_name.
This script opens a template xml file and execute it. Then saves the result in the result file.
You can open the result file in a normal DTT.
You can call restoreRunSave from watch scripts, such as c1_watch_dr_bang.

watchLockLoss is a standalone watch script to detect a lock loss and call restoreRunSave.
It runs both on Linux and Solaris. However on Linux, diag fails 50% of the time with some glibc error.
So it is probably better to run it on op440m.
  1493   Fri Apr 17 11:05:22 2009 YoichiUpdateLockingThursday night locking status
The last night, it was sort of robust to go up until arm power = 26.
The REFL_DC gain seems to change a lot around this region. So I did fine adjustments of the gain with small incremental steps of the arm power.
This work will continue.
The AutoDTT shows that the lock loss happens with an oscillation of CARM at around 100Hz. This indicates that the cross-over is the culprit.
I was also able to increase the CM UGF up to 10kHz.
  1494   Fri Apr 17 11:37:32 2009 YoichiConfigurationComputer Scripts / ProgramsAutoDTT
In order to get test point data with AutoDTT, you have to pre-trigger test points you want to use.
This is done by starting a DTT measurement with necessary test points for a few second, then stop it but keep the DTT opened.
I made prepTP script which does this job.
It takes a file name of an XML file, which should include a DTT measurement setup with test point channels you want to open and the trigger time set to "now".
The script will open an xterm and run diag with the XML file. Unlike restoreRunSave script, it does not save the result nor quit diag. Therefore, you can keep the test points as long as you keep the xterm opened. You can manually exit the diag (Ctrl-D) when you no longer need the test points.
watchLockLoss script now calls prepTP at the beginning. Therefore, you have to be able to open an xterm. If you run the script through SSH, make sure that you give -X option to ssh.
  1495   Sun Apr 19 03:34:05 2009 YoichiUpdateLockingSaturday night lock
Tonight I was able to go up to arm power = 33, by mainly tweaking the DARM gain. A small progress.
In order to give more phase margin to the CARM MC_L path, I added a 300:100 filter to C1:LSC-MC.
To reduce the load to the lsc computer I deleted several filters from the filter bank, which were not used in the locking scripts.
Before I deleted the filters, I checked in the current chans directory into the svn repository.
If you want to restore the deleted filters, go back to the revision 36142.
  1498   Mon Apr 20 05:18:42 2009 YoichiConfigurationLockingFM6 and FM10 of LSC-MC were restored
During tonight's locking work, I realized that FM6 and FM10 (both resonant gains around 20Hz) were actually activated by cm_step.
So I restored those filters from the svn history.
Instead, I removed a bunch of unused filters from LSC-DEMOD and LSC-DEMOD_A (moving zero filters) to off load c1lsc.

As for the locking itself, the DARM loop becomes unstable at around arm power = 30. I may have to add a filter to give a broader phase bubble.
  1509   Thu Apr 23 16:27:24 2009 YoichiUpdateLockingLocking with the cryo-pump
The last night, the IFO was unstabler than usual and the locking script often failed before reaching the power up stage.
The failure happened at random points.
I'm not sure if this is related to the operation of the cryo-pump.
The mode cleaner reflection image seemed to move around more than usual. Maybe it was just a high seismic night.
  1510   Thu Apr 23 16:35:23 2009 YoichiSummaryComputer Scripts / ProgramsrestoreWatchdog script
When the IFO loses lock during the lock acquisition steps, it often kicks the MC2 (through the CM servo) and trips the watchdog.
I wrote a script to restore the tripped watchdog (/cvs/cds/caltech/scripts/SUS/restoreWatchdog).
The script takes the name of a mirror (such as MC2) as an argument.
It will enable the coils and temporarily increase the watchdog threshold to a value higher than the current OSEM RMS signals.
Then it will bring the watchdog back to the normal state and wait for the mirror to be damped. After the mirror is damped enough, the
watchdog threshold will be restored to the original value.
The script will do nothing if the watchdog is not tripped.
I put this script in the drdown_bang so that the MC2 watchdog will be automatically restored when a lock loss kicks out the MC2.
  1512   Thu Apr 23 18:09:11 2009 YoichiUpdateEnvironmentEffect of cryopump
The attached is the trend plot of the MC1 accelerometer for 3 days.
It is evident that the seismic level increased by a factor of two on Wednesday morning (when Steve started the cryopump).
Attachment 1: SeisTrend.pdf
SeisTrend.pdf
  1513   Thu Apr 23 21:13:37 2009 YoichiSummaryEnvironmentMag. 4 earthquake in LA tripped the watchdogs of the most optics
So far, no damage is noticeable.
restoreWatchdog script was useful Smile
-------------------------------------------------------
Magnitude    4.0
Date-Time    * Friday, April 24, 2009 at 03:27:50 UTC
             * Thursday, April 23, 2009 at 08:27:50 PM at epicenter 
Location     33.910N, 117.767W
Depth	     0 km (~0 mile) (poorly constrained)
Region	     GREATER LOS ANGELES AREA, CALIFORNIA
-------------------------------------------------------
  1514   Fri Apr 24 03:57:30 2009 YoichiUpdateLockingDARM demod phase
Tonight, I was able to go up to arm power = 40 by tweaking the DARM demodulation phase.
I think the DARM loop became unstable because the demodulation phase was not right and the error signal contained some junk from I-phase.
I did not do any sophisticated demodulation phase optimization. Rather I just tweaked the phase so that the dark port image becomes stable.
I will do more careful demodulation phase tuning next time.
  1515   Fri Apr 24 04:38:49 2009 YoichiUpdateLockingDARM demod phase

Quote:
Tonight, I was able to go up to arm power = 40 by tweaking the DARM demodulation phase.
I think the DARM loop became unstable because the demodulation phase was not right and the error signal contained some junk from I-phase.
I did not do any sophisticated demodulation phase optimization. Rather I just tweaked the phase so that the dark port image becomes stable.
I will do more careful demodulation phase tuning next time.


In the next try, I was actually able to go up to arm power = 70 stably.
At this power level we are ready for the RF CARM hand off.
  1519   Fri Apr 24 17:26:57 2009 YoichiUpdateLockingDARM demod phase

Quote:

There's actually code in place in the LSC to dynamically adjust the demod phase for AS1. I've never made much use of it, because it's possible to get around the problem with some gain tweaking if you start at the right phase, or because I did the DC readout handoff earlier.

Attached is a cartoon showing how the demod phase at the dark port changes as the CARM offset is decreased.


The cartoon is very nice.
I actually changed the demod phase continuously as the CARM offset was reduced to get up to arm power = 70.
As the CARM offset is changed, not only the DARM signal gain but also the phase margin around 100Hz changes if you use a fixed demodulation phase.
So it was necessary to change the demodulation phase to keep the DARM loop stable.
  1520   Sat Apr 25 00:45:31 2009 YoichiConfigurationVACReflector for the cryopump temperature monitor changed
The temperature of the cryopump head is monitored by a photo switch looking at an aluminum foil reflector attached to the needle of the temperature gauge.
If the needle moves out of the 14K position, the photo switch will be triggered to close the cryopump gate valve.
However, this photo switch system has been touchy.
Tonight, the switch falsely tripped several times and closed the gate valve, which caused lock losses as the motion of the valve generates a lot of vibrations.
Seems to me, it was caused by the poor/irregular reflection from the wrinkled aluminum foil on the needle.
So I replaced the aluminum foil with a brand-new shiny one.
  1521   Sat Apr 25 02:54:25 2009 YoichiConfigurationVACReflector for the cryopump temperature monitor changed

Quote:
The temperature of the cryopump head is monitored by a photo switch looking at an aluminum foil reflector attached to the needle of the temperature gauge.
If the needle moves out of the 14K position, the photo switch will be triggered to close the cryopump gate valve.
However, this photo switch system has been touchy.
Tonight, the switch falsely tripped several times and closed the gate valve, which caused lock losses as the motion of the valve generates a lot of vibrations.
Seems to me, it was caused by the poor/irregular reflection from the wrinkled aluminum foil on the needle.
So I replaced the aluminum foil with a brand-new shiny one.


The photo switch still trips randomly. We need a better interlock.
  1522   Sat Apr 25 03:27:34 2009 YoichiUpdateLockingLocking status
Yoichi, Peter,

We are working on the final step of the lock acquisition, RF CARM hand off.
I was able to hand off the CARM error signal to RF once, but lost lock when decreasing the CARM offset to zero (it was too rapid).
I will try to make the process more robust tomorrow.
  1523   Sun Apr 26 02:13:18 2009 YoichiUpdateLockingTwo more successes of RF CARM handoff
Tonight, the RF CARM hand off (mostly) succeeded twice.
But still, the IFO lost lock when I reduced the REFL_DC gain in the AO path to zero.

At the beginning of tonight's work, MICH DD hand off failed several times. This was because the the PD9 gains were set to zero.
I found that the offset script, which I called before starting the locking, fails to restore the gain values sometimes.
This happens when ezcaread fails to read the current gain. We have to be careful when running the LSCoffsets script.
  1526   Tue Apr 28 04:30:16 2009 YoichiUpdateLockingRF full lock
Yoichi, Peter

I believe we have succeeded in the full lock of the interferometer with the RF signals.
The lock process is reasonably robust and repeatable.

I did a scan of the RF CARM offset and plotted the arm power as a function of the CARM offset (see the attachment).
The arm power goes maximum at non-zero CARM offset. I guess the RF CARM error signal has some offset.
Maybe the demodulation phase is wrong ? I will tweak this tomorrow.
The script to do this scan can be found at /cvs/cds/caltech/scripts/CM/CARMSweep.

I haven't tried DC readout yet.
Attachment 1: Sweep1.png
Sweep1.png
  1531   Wed Apr 29 04:03:51 2009 YoichiUpdateLockingCARM RF changed to REFL_2I
Yoichi, Peter

As Rob suggested, the optimal demodulation phase is easier to find for REFL_2I than POX_1I.
Moreover, for 166MHz LO, we have a phase shifter (delay line) already installed. So we can easily change the demodulation phase of REFL_2I.
Tonight, we switched the RF CARM signal to REFL_2I.
To do so, I changed the signal going to the REFL1 input of the common mode board from POX_1I to REFL_2I.
I moved a BNC-T installed at the output of POX_1I to the REFL_2I output to split the REFL_2I signal and send it to the CM board.
Since the gain of the REFL_2I was about 20dB lower than that of POX_1I, I increased the gain of the SR560, which is installed between the REFL_2 demodulation board and the CM board, from 1 to 10.

With some gain tweaks, we were able to hand off the CARM from REFL_DC to REFL_2I. We also succeeded in switching the REFL_2I ADC channel from PD11 to PD2_DC (the output of the length path from the CM board). This switching is necessary in order to engage the boost on the CM board.

There remains some offset in the CARM when the arm power is maximized. This is expected because the REFL_2I demodulation phase is probably not exactly right.
I will optimize the demodulation phase tomorrow.
  1534   Thu Apr 30 05:49:06 2009 YoichiUpdateLocking166MHz LO phase changed
In order to optimize the REFL_2I demod phase, I changed the delay line setting for the 166MHz LO.
Right now, the delay is not yet optimal.
Since the AS166 shares the same LO, the digital demodulation phase of the AS166 had to be changed too.
The DD demod phases and the DD hand off script were also tweaked to improve the resonant condition of the central part.
Now we have more 166MHz coming out of the AS port and the SPOB is larger (more 33MHz resonant in PRC).

Since REFL166 and AS166 demodulation phases are not yet optimized, the cm_step script won't work at this moment.
  1536   Fri May 1 01:32:43 2009 YoichiUpdateLocking166MHz LO phase adjustment
I continued to adjust the REFL_2I demodulation phase.
I first optimized the demod phase for SRCL in the DRMI configuration (the error signals were DDs).
Then I restored the full IFO and offset locked it.
Before handing the DARM to RF, I adjusted the 166MHz delay line to maximize the SRCL signal at REFL_2I.
I did this before the DARM RF hand off because changing the delay line setting also changes the AS166 demodulation phase.
After this, I adjusted the digital phase shifter for AS166 to maximize the DARM signal for this port.

I also adjusted the digital demodulation phase of PD11 (REFL_2I) because the optimal demodulation phase for the initial lock acquisition is somewhat (15deg)
different from the optimal demodulation phase for the SRCL when the central part is locked with the DD signals.
This happens because the resonant condition of the central part (lock points of the recycling cavities) changes when the error signals are switched to the DD signals,
due to the offset in the DD signals. This is not good and should be fixed by the optimization of the DD demodulation phases.

Finally, I reduced the CARM offset to zero and tweaked the delay line a bit to maximize the arm power.

Right now, the locking script runs fine until the end.
At the end of the script, I was able to engage the boost on the CM board.
  1541   Sun May 3 22:48:12 2009 YoichiUpdateLockingSome measurements at the lock point
I attached some measurement results at when the IFO is at the full lock point.

The first plot shows the trend of the arm powers after the interferometer was locked.
The arm powers slowly increased after the lock. This increase is observed every time the IFO is locked.
Probably this is some sort of a thermal effect (mirror lensing, PD efficiency etc).

The second plot is a CARM offset sweep. Even after the demodulation phase optimization, the lock point is not exactly at the resonance.

The third plot is the open loop TF of the AO path. The CM loop UGF is about 20kHz.
The boost and the superboost1 were turned on when this TF was measured. The IFO loses lock if the superboost2 is turned on.

TO DO LIST
Measured the DARM loop shape.
I could not turn on the dewhitening filter for ETMY. ETMX had no trouble. I will check the dewhitening circuit.
Attachment 1: ArmPowerTrend.png
ArmPowerTrend.png
Attachment 2: CARMSweep.png
CARMSweep.png
Attachment 3: CM-AO-Loop-SB1.png
CM-AO-Loop-SB1.png
  1544   Tue May 5 05:16:12 2009 YoichiUpdateLockingDC Readout and DARM response
Tonight, I was able to switch the DARM to DC readout a couple of times.
But the lock was not as stable as the RF DARM. It lost lock when I tried to measure the DARM loop gain.

I also measured DARM response when DARM is on RF.
The attached plot shows the DARM optical gain (from the mirror displacement to the PD output).
The magnitude is in an arbitrary unit.

I measured a transfer function from DARM excitation to the DARM error signal. Then I corrected it for the DARM open loop gain and the pendulum response to get the plot below.

There is an RSE peak at 4kHz as expected. The origin of the small bump and dip around 2.5kHz and 1.5kHz are unknown.
I will consult with the Optickle model.
I don't know why the optical gain decreases below 50Hz (I don't think it actually decreases).
Seems like the DARM loop gain measured at those frequencies are too low.
I will retry the measurement.
Attachment 1: DARM-TF.png
DARM-TF.png
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