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ID Date Author Type Category Subject
13862   Fri May 18 09:13:41 2018 PoojaUpdateSUSColored GigE image

To obtain a colored version with good contrast of the grayscale image of scattering of light by dust particles on the surface of test mass, got using GigE camera. The original and colored images are attached here.

Attachment 1: Image__2017-11-14__08-25-13_100k100g1V_colored.png
Attachment 2: Image__2017-11-14__08-25-13_100k100g1V.tiff
13901   Thu May 31 10:19:42 2018 gautamUpdateSUSMC3 glitchy

Seems like as a result of my recent poking around at 1X6, MC3 is more glitchy than usual (I've noticed that the IMC lock duty cycle seems degraded since Tuesday). I'll try the usual cable squishing voodo.

gautam 8.15pm: Glitches persisted despite my usual cable squishing. I've left PSL shutter closed and MC watchdog shutdown to see if the glitches persist. I'll restore the MC a little later in the eve.

Attachment 1: MC3_glitchy.png
13988   Tue Jun 19 23:27:27 2018 gautamUpdateSUSETMX coil driver work in AM tomorrow

Per discussion today eve, barring objections, I will do the following tomorrow morning:

1. Remove ETMX coil driver board from 1X9
• Change series resistances on the fast path to 2x4k in parallel. One will be snipped off once we are happy we can still lock.
• Thick film-->thin film for important components.
2. Remove ETMX de-whitening board from 1X9
• Remove x3 analog gain.
• Thick film-->thin film for important components.
13992   Thu Jun 21 00:14:01 2018 gautamUpdateSUSETMX coil driver out

I finished the re-soldering work today, and have measured the coil driver noise pre-Mods and post-Mods. Analysis tomorrow. I am holding off on re-installing the board tonight as it is likely we will have to tune all the loops to make them work with the reduced range. So ETMX will remain de-commissioned until tomorrow.

13993   Thu Jun 21 03:13:37 2018 gautamUpdateSUSETMX coil driver noise

I decided to take a quick look at the data. Changes made to the ETMX coil driver board:

1. Fast path series resistances: 400 ohm ---> 2.25 kOhm (= 2x 4.5 kohm in parallel). Measured (with DMM) resistance in all 5 paths varied by less than 3 ohms (~0.2%).
2. All thick film resistors in signal (fast and bias) paths changed to thin film.
3. AD797 ---> Op27 for monitor output.
4. Above-mentioned mon output (30Hz HPF-ed) routed to FP LEMO mon via 100ohm for diagnostic purposes.
5. 4x Trim-pots in analog path removed.

I also took the chance to check the integrity of the LM6321 ICs. In the past, a large DC offset on the output pin of these has been indicative of a faulty IC. But I checked all the ICs with a DMM, and saw no anomalies.

Measurement condition was that (i) the Fast input was terminated to ground via 50ohm, (ii) the Bias input was shorted to ground. SR785 was used with G=100 Busby preamp (in which Steve installed new batteries today, for someone had left it on for who knows how long) for making the measurement. The voltage measurement was made at the D-Sub connector on the front panel which would be connected to the Sat. Box, with the coil driver not connected to anything downstream.

Summary of results:

[Attachment #1] - Noise measurement out to 800 Hz. The noise only seems to agree with the LISO model above 300 Hz. Not sure if the low-frequency excess is real or a measurement artefact. Tomorrow, I plan to make an LPF pomona box to filter out the HF pickup and see if the low-frequency characteristics change at all. Need to think about what this corner freq. needs to be. In any case, such a device is probably required to do measurements inside the VEA.

[Attachment #2] - Noise measurement for full SR785 span. The 19.5 kHz harmonics are visible. I have a theory about the origin of these, need to do a couple of more tests to confirm and will make a separate log.

[Attachment #3] - zip of LISO file used for modeling coil driver. I don't have the ASCII art in this, so need to double check to make sure I haven't connected some wrong nodes, but I think it's correct.

Measurements seem to be consistent with LISO model predictions.

*Note: Curves labelled "LISO model ..." are really quad sum of liso pred + busby box noise.

My main finding tonight is: With the increased series resistance (400 ohm ---> 2.25 kohm), LISO modeling tells me that even though the series resistance (Johnson noise) used to dominate the voltage noise at the output to the OSEM, the voltage noise of the LT1125 in the bias path now dominates. Since we are planning to re-design the entire bias path anyways, I am not too worried about this for the moment.

I will upload more details + photos + data + schematic + LISO model breakdown tomorrow to a DCC page

gautam noon 21 June 2018: I was looking at the wrong LISO breakdown curves. So the input stage Op27 voltage noise used to dominate. Now the Bias path LT1125 voltage noise dominates. None of the conclusions are affected... I've uploaded the corrected plots and LISO file here now.

Attachment 1: ETMXsticthced.pdf
Attachment 2: ETMXFullSpan.pdf
Attachment 3: ETMXCoilDriver.fil.zip
13999   Thu Jun 21 18:25:57 2018 gautamUpdateSUSETMX coil driver re-installed

Initial tests look promising. Local damping works and I even locked the X arm using POX, although I did it in a fake way by simply inserting a x5.625 (=2.25 kohm / 400 ohm) gain in the coil driver filter banks. I will now tune the individual loop gains to account for the reduced actuation range.

Now I have changed the loop gains for local damping loops, Oplev loops, and POX locking loop to account for the reduced actuation range. The dither alignment servo (X arm ASS) has not been re-commissioned yet...

14004   Fri Jun 22 08:50:33 2018 SteveUpdateSUSITMY_UL sensor

We may lost the UL magnet or LED

Attachment 1: ITMY_UL.png
14009   Fri Jun 22 18:30:21 2018 gautamUpdateSUSITMY_UL sensor

I think if the magnet fell off, we would see high DC signal, and not 0 as we do now. I suspect satellite box or PD readout board/cabling. I am looking into this, tester box is connected to ITMY sat. box for now. I will restore the suspension later in the evening.

Suspension has now been restored. With combination of multimeter, octopus cable and tester box, the problem is consistent with being in the readout board in 1X5/1X6 or the cable routing the signals there from the sat. box.

• Tester box hooked up to sat box ---> UL coil still shows 0 in CDS.
• Tester box hooked up to sat box ---> Mon D-sub on sat box shows expected voltages on DMM. So tester box LEDs are being powered and seem to work.
• Sat box re-connected to test mass ---> Mon D-sub on sat box shows expected voltages on DMM. So OSEM LEDs are being powered and seem to work.
• Sat box remains connected to TM ---> Front panel LEMO monitor points on readout board shows 0 for UL channel, other channels are okay.
 Quote: We may lost the UL magnet or LED

14012   Sun Jun 24 20:02:07 2018 gautamUpdateSUSSome notes about coil driver noise

Summary:

For a series resistance of 4.5 kohm, we are suffering from the noise-gain amplified voltage noise of the Op27 (2*3.2nV/rtHz), and the Johnson noise of the two 1 kohm input and feedback resistances. As a result, the current noise is ~2.7 pA/rtHz, instead of the 1.9 pA/rtHz we expect from just the Johnson noise of the series resistance. For the present EX coil driver configuration of 2.25 kohm, the Op27 voltage noise is actually the dominant noise source. Since we are modeling small amounts (<1dB) of measurable squeezing, such factors are important I think.

Details:

[Attachment #1] --- Sketch of the fast signal path in the coil driver board, with resistors labelled as in the following LISO model plots. Note that as long as the resistance of the coil itself << the series resistance of the coil driver fast and slow paths, we can just add their individual current noise contributions, hence why I have chosen to model only this section of the overall network.

[Attachment #2] --- Noise breakdown per LISO model with top 5 noises for choice of Rseries = 2.25 kohm. The Johnson noise contributions of Rin and Rf exactly overlap, making the color of the resulting line a bit confusing, due to the unfortunate order of the matplotlib default color cycler. I don't want to make a custom plot, so I am leaving it like this.

[Attachment #3] --- Noise breakdown per LISO model with top 5 noises for choice of Rseries = 4.5 kohm. Same comments about color of trace representing Johnson noise of Rin and Rf.

Possible mitigation strategies:

1. Use an OpAmp with lower voltage noise. I will look up some candidates. LT1028/LT1128? LISO library warns of a 400 kHz noise peak though...
2. Use lower Rin and Rf. The values of these are set by the current driving capability of the immediately preceeding stage, which is the output OpAmp of the De-Whitening board, which I believe is a TLE2027. These can source/sink 50 mA according to the datasheet . So for +/-10V, we could go to 400 ohm Ri and Rf, source/sink a maximum of 25mA, and reduce the Johnson noise contribution by 40%.

I've chosen to ignore the noise contribution of the high current buffer IC that is inside the feedback loop. Actually, it may be interesting to compare the noise measurements (on the electronics bench) of the circuit as drawn in Attachment #1, without and with the high current buffer, to see if there is any difference.

This study also informs about what level of electronics noise is tolerable from the De-Whitening stage (aim for ~factor of 5 below the Rseries Johnson noise).

Finally, in doing this model, I understand that the observation the voltage noise of the coil driver apparently decreased after increasing the series resistance, as reported in my previous elog. This is due to the network formed by the fast and slow paths (during the measurement, the series resistance in the slow path makes a voltage divider to ground), and is consistent with LISO modeling. If we really want to measure the noise of the fast path alone, we will have to isolate it by removing the series resistance of the slow bias path.

Comment about LISO breakdown plots: for the OpAmp noises, the index "0" corresponds to the Voltage noise, "1" and "2" correspond to the current noise from the "+" and "-" inputs of the OpAmp respectively. In future plots, I'll re-parse these...

 Quote: I will upload more details + photos + data + schematic + LISO model breakdown tomorrow to a DCC page.

Attachment 1: CoilDriverSchematic.pdf
Attachment 2: D010001_2k_fastOnly_2.25k.pdf
Attachment 3: D010001_4k_fastOnly_4.5k.pdf
14019   Tue Jun 26 16:28:00 2018 gautamUpdateSUSCoil driver protoboard characterization

I wanted to investigate my coil driver noise measurement technique under more controlled circumstances, so I spent yesterday setting up various configurations on a breadboard in the control room. The overall topology was as sketched in Attachment #1 of the previous elog, except for #4 below. Summary of configurations tried (series resistance was 4.5k ohm in all cases):

1. Op 27 with 1kohm input and feedback resistors.
2. LT1128 with 1kohm input and feedback resistors.
3. LT1128 with 400 ohm input and feedback resistors.
4. LT1128 with 400 ohm input and feedback resistors, and also the current buffer IC LM6321 implemented.

Attachments:

Attachment #1: Picture of the breadboard setup.

Attachment #2: Noise measurements (input shorted to ground) with 1 Hz linewidth from DC to 4 kHz.

Attachment #3: Noise measurements for full SR785 span.

Attachment #4: Apparent coupling due to PSRR.

Attachment #5: Comparison of low frequency noise with and without the LM6321 part of the fast DAC path implemented.

All SR785 measurements were made with input range fixed at -42dBVpk, input AC coupled and "Floating", with a Hanning window.

Conclusions:

• I get much better agreement between LISO and measurement at a few hundred Hz and below with this proto setup. So it would seem like the excess noise I measure at ~200 Hz in the Eurocrate card version of the coil driver could be real and not simply a measurement artefact.
• I am puzzled about the 10 Hz comb in all these measurements:
• I have seen this a few times before - e.g. elog13655.
• It is not due to the infamous GPIB issue - the lines persist even though I disconnect both power adaptor and GPIB prologix box from the SR785.
• It does not seem to be correlated with the position of the analyzer w.r.t. the DC power supply (Tektronix PS280) used to power the circuit (I moved the SR785 around 1m away from the supply).
• It persists with either of the two LN preamp boxes available.
• It persists with either "Float" or "Ground" input setting on the SR785.
• All this pointed to some other form of coupling - perhaps conductive EMI.
• The only clue I have is the apparent difference between the level of the coupling for Op27 and LT1128 - it is significantly lower for the latter compared to the former.
• I ruled out position on the breadboard: simply interchanging the Op27 and LT1128 positions on the breadboard, I saw higher 10 Hz harmonics for the Op27 compared to the LT1128. In fact, the coupling was higher for the DIP Op27 compared to an SOIC one I attached to the breadboard via an SOIC to DIP adapter (both were Op27-Gs, with spec'ed PSRR of 120 dB typ).
• To test the hypothesis, I compared the noise for the Op27 config, on the one hand with regulated (via D1000217) DC supply, and on the other, directly powered by the Tektronix supply. The latter configuration shows much higher coupling.
• I did have 0.1uF decoupling capacitors (I guess I should've used ceramic and not tantala) near the OpAmp power pins, and in fact, removing them had no effect on the level of this coupling
• As a quick check, I measured the spectrum of the DC power used to run the breadboard - it is supplied via D1000217. I used an RC network to block out the DC, but the measurement doesn't suggest a level of noise in the supply that could explain these peaks.
• The regulators are LM2941 and LM2991. They specify something like 0.03% of the output voltage as AC RMS, though I am not sure over what range of frequencies this is integrated over.
• But perhaps the effect is more subtle, some kind of downconversion of higher frequency noise, but isn't the decoupling cap supposed to protect against this?
• The 19.5 kHz harmonics seem to originate from the CRT display of the SR785 (SVGA).
• The manual doesn't specify the refresh rate, but from a bit of googling, it seems like this is a plausible number.
• The coupling seems to be radiative. The box housing the Busby preamp provides ~60dB attentuation of this signal, and the amplitude of the peaks is directly correlated to where I position the Busby box relative to the CRT screen.
• This problem can be avoided by placing the DUT and preamp sufficiently far from the SR785.

Punchlines:

1. The actual coildriver used, D010001, doesn't have a regulated power supply, it just draws the +/- 15V directly from Sorensens. I don't think this is good for low noise.
2. The LM6321 part of the circuit doesn't add any excess noise to the circuit, consistent with it being inside the unity gain feedback loop. In any case, with 4.5 kohm series resistance with the coil driver, we would be driving <2.5 mA of current, so perhaps we don't even need this?
Attachment 1: IMG_7060.JPG
Attachment 2: ETMXstitchced.pdf
Attachment 3: ETMXfullSpan.pdf
Attachment 4: PSRR.pdf
14032   Thu Jun 28 16:48:27 2018 gautamUpdateSUSSOS cage towers

For the upcoming vent, we'd like to rotate the SOS towers to correct for the large YAW bias voltages used for DC alignment of the ITMs and ETMs. We could then use a larger series resistance in the DC bias path, and hence, reduce the actuation noise on the TMs.

Today, I used the calibrated Oplev error signals to estimate what angular correction is needed. I disabled the Oplev loops, and drove a ~0.1 Hz sine wave to the EPICS channel for the DC yaw bias. Then I looked at the peak-to-peak Oplev error signal, which should be in urad, and calibrated the slider counts to urad of yaw alignment, since I know the pk-to-pk counts of the sine wave I was driving. With this calibration, I know how much DC Yaw actuation (in mrad) is being supplied by the DC bias. I also know the directions the ETMs need to be rotated, I want to double check the ITMs because of the multiple steering mirrors in vacuum for the Oplev path. I will post a marked up diagram later.

Steve is going to come up with a strategy to realize this rotation - we would like to rotate the tower through an axis passing through the CoM of the suspended optic in the vertical direction. I want to test out whatever approach we come up with on the spare cage before touching the actual towers.

Here are the numbers. I've not posted any error analysis, but the way I'm thinking about it, we'd do some in air locking so that we have the cavity axis as a reference and we'd use some fine alignment adjust (with the DC bias voltages at 0) until we are happy with the DC alignment. Then hopefully things change by so little during the pumpdown that we only need small corrections with the bias voltages.

SoS tower DC bias correction
Optic

EPICS excitation

[V pk-pk]

ETMX 0.06 110 1.83 -5.5305 -10.14
ITMX 0.02 180 9 -1.4500 -13.05
ITMY 0.02 120 6 -0.3546 -2.13
ETMY 0.06 118 1.97 0.5532 1.09

Some remarks:

1. Why the apparent difference between ITMs and ETMs? I think it's because the bias path resistors are 400 ohms on the ETMs, but 100 ohms on the ITMs
2. If we want the series resistance for the bias path to be 10 kohm, we'd only have ~800 urad actuation (for +10V DC), so this would be an ambitious level of accuracy.
14034   Mon Jul 2 09:01:11 2018 SteveUpdateSUSITMY_UL sensor

This bad connection is coming back

 Quote: We may lost the UL magnet or LED

Attachment 1: ITMY_ULcripingback.png
14038   Thu Jul 5 10:15:30 2018 gautamUpdateSUSPRM watchdog tripped

PRM watchdog was tripped around 7:15am PT today morning. I restored it.

Attachment 1: PRM_watchdogTrip.png
14075   Tue Jul 17 01:07:40 2018 gautamUpdateSUSETMY EQ stops

For the heater setup on EY table, I EQ-stopped ETMY. Only the face EQ stops (3 on HR face, 2 on AR face) were engaged. The EY Oplev HeNe was also shutdown during this procedure.

14090   Fri Jul 20 07:43:54 2018 SteveSummarySUSETMY

Attachment 1: ETMY_leveling.png
Attachment 2: ETMY.png
14108   Fri Jul 27 10:48:57 2018 SteveUpdateSUSBS oplev window

Yesterday I inspected this BS oplev viewport. The heavy connector tube was shorting to table so It was moved back towards the chamber. The connection is air tight with kapton tape temporarly.

The beam paths are well centered. The viewport is dusty on the inside.

The motivation was to improve the oplev noise.

Attachment 1: BSOw_.jpg
Attachment 2: dustInsideBSO.jpg
14115   Mon Jul 30 11:05:44 2018 gautamUpdateSUSIFO SUS wonky

When I came in this morning:

• PMC was unlocked.
• Seis BLRMS were off scale.
• ITMX OSEM LEDs were dark on the CRT monitor even though Sat Box was plugged in.

Checking status of slow machines, it looked like c1sus, c1aux, and c1iscaux needed reboots, which I did. Still PMC would not lock. So I did a burtrestore, and then PMC was locked. But there seemed to be waaaaay to much motion of MCREFL, so I checked the suspension. The shadow sensor EPICS channels are reporting ~10,000 cts, while they used to be ~1000cts. No unusual red flags on the CDS side. Everything looked nominal when I briefly came in at 6:30pm PT yesterday, not sure if anything was done with the IFO last night.

Pending further investigation, I'm leaving all watchdogs shutdown and the PSL shutter closed.

A quick look at the Sorensens in 1X6 revealed that the +/- 20V DC power supplies were current overloaded (see Attachment #1). So I set those two units to zero until we figure out what's going on. Possibly something is shorted inside the ITMX satellite box and a fuse is blown somewhere. I'll look into it more once Steve is back.

Attachment 1: IMG_7102.JPG
14117   Mon Jul 30 16:11:54 2018 gautamUpdateSUSTrillium interface box is broken

[koji, steve, gautam]

We debugged this in the following way:

1. Disconnect all fuses in the terminal blocks coming from the +/- 20 VDC Sorensens.
2. Check that they are indeed isolated using DMM.
3. Test blocks of fuses in order to identify where the problem is happening (i.e. plug fuses in, turn up Sorensen voltage knobs, look for current overload). We did things in the following order:
• MC suspensions
• BS, PRM and SRM
• ITMY
• ITMX
• Trillium interface box.
4. Turns out that the Trillium box is the culprit.
5. Confirmed that the problem is in the trillium interface box and not in the seismometer itself by unplugging all cables leading out of the interface box, and checking that the problem persists when the box is powered on.

So for now, the power cable to the box is disconnected on the back end. We have to pull it out and debug it at some point.

Apart from this, megatron was un-sshable so I had to hard reboot it, and restart the MCautolocker, FSSslowPy and nds2 processes on it. I also restarted the modbusIOC processes for the PSL channels on c1auxex (for which the physical Acromag units sit in 1X5 and hence were affected by our work), mainly so that the FSS_RMTEMP channel worked again. Now, IMC autolocker is working fine, arms are locked (we can recover TRX and TRY~1.0), and everything seems to be back to a nominal state. Phew.

14118   Mon Jul 30 18:19:03 2018 KojiUpdateSUSTrillium interface box was fixed and reinstalled

The trillium interface box was removed from the rack.

The problem was the incorrect use of an under-spec TVS (Transient Voltage Suppression) diodes (~ semiconductor fuse) for the protection circuit.
The TVS diodes we had had the breakdown voltages lower than the supplied voltages of +/-20V. This over-voltage eventually caused the catastrophic breakdown of one of the diodes.

I don't find any particular reason to have these diodes during the laboratory use of the interface. Therefore, I've removed the TVS diodes and left them unreplaced. The circuit was tested on the bench and returned to the rack. All the cables are hooked up, and now the BRLMs look as usual.

Details

- The board version was found to be D1000749-v2

- There was an obvious sign of burning or thermal history around the components D17 and D14. The solder of the D17 was so brittle that just a finger touch was enough to remove the component.

- These D components are TVS diodes (Transient Voltage Suppression Diodes) manufactured by Littelfuse Inc. It is sort of a surge/overvoltage protector to protect rest of the circuit to be exposed to excess voltage. The specified component for D17/D14 was 5.0SMMDJ20A with reverse standoff voltage (~operating voltage) of 20V and the breakdown voltage of 22.20V(min)~24.50V(max). However, the spec sheet told that the marking of the proper component must be "5BEW" rather than "DEM," which is visible on the component. Some search revealed that the used component was SMDJ15A, which has the breakdown voltage of 16.70V~18.50V. This spec is way too low compared to the supplied voltage of +/-20V.

Attachment 1: P_20180730_173134.jpg
Attachment 2: P_20180730_180151.jpg
14119   Tue Jul 31 08:17:55 2018 SteveUpdateSUSTrillium interface box was fixed,reinstalled & working

Attachment 1: all_OK.png
14129   Fri Aug 3 15:53:25 2018 gautamUpdateSUSLow noise bias path idea

Summary:

The idea we are going with to push the coil driver noise contribution down is to simply increase the series resistance between the coil driver board output and the OSEM coil. But there are two paths, one for fast actuation and one that provides a DC current for global alignment. I think the simplest way to reduce the noise contribution of the latter, while preserving reasonable actuation range, is to implement a precision DC high-voltage source. A candidate that I pulled off an LT application note is shown in Attachment #1.

Requirements:

• The series resistance in the bias path should be $10 k\Omega$, such that the noise from this stage is dominated by the Johnson noise of said resistor, and hence, the current noise contribution is negligible compared to the series resistance in the fast actuation path ($4.5 k\Omega$).
• Since we only really need this for the test masses, what actuation range do we want?
• Currently, ETMY has a series resistance of $400\Omega$ and has a pitch DC bias voltage of -4 V.
• This corresponds to 10 mA of DC current.
• To drive this current through $10 k\Omega$, we need 100 V.
• I'm assuming we can manually correct for yaw misalignments such that 10mA of DC current will be sufficient for any sort of corrective alignment.
• So +/- 120 V DC should be sufficient.
• The current noise of this stage should be negligible at 100 Hz.
• The noise of the transistors and the HV supply should be suppressed by the feedback loop and so shouldn't be a significant contribution (I'll model to confirm).
• The input noise of the LT1055 is ~20nV/rtHz at 100 Hz, while the Johnson noise of $10 k\Omega$ is ~13nV/rtHz so maybe the low-passing needs to be tuned, but I think if it comes to it, we can implement a passive RC network at the output to achieve additional filtering.
• To implement this circuit, we need +/- 125V DC.
• At EX and EY, we have a KEPCO HV supply meant to be used for the Green Steering PZTs.
• I'm not sure if these can do bipolar outputs, if not, for temporary testing, we can transport the unit at EY to EX.

If all this seems reasonable, I'd like to prototype this circuit and test it with ETMX, which already has the high series resistance for the fast path. So I will ask Steve to order the OpAmp and transistors.

Attachment 1: LT1055_precOpAmp.pdf
14130   Fri Aug 3 16:27:40 2018 ranaUpdateSUSLow noise bias path idea

Bah! Too complex.

14131   Fri Aug 3 18:54:58 2018 gautamUpdateSUSGlitchy MC1

The wall StripTool indicated that the IMC wasn't too happy when I came in today. Specifically:

• MC1 watchdog was tripped.
• Even in the tripped state, MC REFL spot on the camera showed spot motion that was too large to be explained as normal seismic driven motion (i.e. with local damping supposedly disabled).
• Strange excursions were observed in the MC1 shadow sensor signal levels as well, see Attachment #1 - negative values don't make any sense for this readout.

The last time this happened, it was due to the Sorensens not spitting out the correct voltages. This time, there were no indications on the Sorensens that anything was funky. So I just disabled the MCautolocker and figured I'd debug later in the evening.

However, around 5pm, the shadow sensor values looked nominal again, and when I re-enabled the local damping, the MC REFL spot suggested that the local damping was working just fine. I re-enabled the MCautolocker, MC re-locked almost immediately. To re-iterate, I did nothing to the electronics inside the VEA. Anyways, this enabled us to work on the X arm ASS (next elog).

Attachment 1: MC1_sensorAnomaly.png
14134   Sun Aug 5 13:45:00 2018 gautamUpdateSUSETMX tripped

Independent from the problems the vertex machine has been having (I think, unless it's something happening over the shared memory network), I noticed on Friday that the ETMX watchdog was tripped. Today, once again, the ETMX watchdog was tripped. There is no evidence of any abnormal seismic activity around that time, and anyways, none of the other watchdogs tripped. Attachment #1 shows that this happened ~838am PT today morning. Attachment #2 shows the 2k sensor data around the time of the trip. If the latter is to be believed, there was a big impulse in the UL shadow sensor signal which may have triggered the trip. I'll squish cables and see if that helps - Steve and I did work at the EX electronics rack (1X9) on Friday but this problem precedes our working there...

Attachment 1: ETMX_tripped.png
Attachment 2: ETMX_tripped_zoom.png
14135   Sun Aug 5 15:43:50 2018 gautamUpdateSUSAnother low noise bias path idea

• Attachment #1 shows the proposed schematic.
• It consists of a second order section with Gain x10 to map the +/-10V DC range of the DAC to +/- 100V DC such that we preserve roughly the same amount of DC actuation range.
• Corner frequency of the SOS is set to ~0.7 Hz. In hindsight, maybe this is more aggressive than necessary, we can tune this.
• DC gain is 20 dB (typo in the text where I say the DC gain is x15, though we could go with this option as well I think if we want a larger series resistance).
• A first order passive low-pass stage is added to filter out the voltage noise of the PA91, which dominates the output voltage noise (next bullet).
• Attachment #2 shows the transfer function from input to output
• The two traces compare having just a single SOS filtering stage vs the current topology of having two SOS stages.
• The passive output RC network is necessary in either case to filter the voltage noise of the PA91 OpAmp.
• For the DAC noise, I just assumed a flat noise level of $5 \mu V / \sqrt{\mathrm{Hz}}$, I don't actually know what this is for the Acromag DACs.
• Attachments #3 shows a breakdown of the top 5 noise contributions.
• The PA91 datasheet doesn't give current noise information so I just assumed $1 fA / \sqrt{\mathrm{Hz}}$, which was what was used for the PA85 in the existing opamp.lib file.
• The voltage noise is modelled as $4.5 \sqrt{1+\frac{80}{f}} nV / \sqrt{\mathrm{Hz}}$, which seems to line up okay with the plot on Pg4 of the datasheet.
• So the model suggests we will be dominated by the voltage noise of the PA91.
• Attachment #4 translates the noise into current noise seen by the actuator.
• I add the Johnson noise contribution of the series resistance for this path, which is assumed to be $10 k \Omega$.
• For comparison, I add the filtered DAC noise contribution, and Johnson noise of the proposed series resistance in the fast path.
• For the bias path, we are dominated by the Johnson noise of the series resistor from ~60 Hz upwards.
• It's not quite fair to say that the Johnson noise of the resistance in the fast path dominates, the quadrature sum of fast and bais paths will be ~1.2 times of the former alone.
• Bottom line: we will be in the regime of total current noise of ~2.2 pA/rtHz, where I think Kevin's modeling suggests we can see some squeezing.

The question still remains of how to combine the fast and bias paths in this proposed scheme. I think the following approach works for prototyping at least:

• Remove the series resistance on the existing coil driver boards' bias path, hence isolating this from the coil.
• Route the DB15 output connector from the coil driver board (which is now just the fast actuation signals) into a sub-sattelite box housing the bias path electronics.
• Sum the two signals as it is done now, by simply having a conductor (PCB trace) merge the two paths after their respective series resistances.

In the longer term, perhaps the Satellite Box revamp can accommodate a bias voltage summation connector.

 Quote: Bah! Too complex.

I have neglected many practical concerns. Some things that come to mind:

1. Is it necessary to protect the upstream DAC from some potential failure of the PA91 in which the high voltage appears at the input?
2. What is the correct OpAmp for this purpose? This chart on Apex's page suggests that PA15, PA85, PA91 and PA98 are all comparable in terms of drive capability, and the spec sheets don't suggest any dramatic differences. Some LIGO circuits use PA85, some use PA90, but I can't find any that use PA91. Perhaps Rana/Koji can comment about this.
3. What kind of protection is necessary for the PA91 power?
4. What is the correct way to do heat management? Presumably we need heatsinks, and in fact, there is a variant of the packaging style that has "formed" legs, which from what I can figure out, allow the heat sink plane on the PA91 to be parallel to the PCB surface. But I think the heat-sink wisdom suggests vertical fins are the most efficient (not sure if this holds if the PCB is inside a box though). What about the PCB itself? Are some kind of special traces needed?
5. Can we use the current-limiting resistor feature on the PA91? The datasheet seems to advice against it for G>10 configurations, which is what we need, although our requirement is only at DC so I don't know if that table is applicable to this circuit.
6. Are 3W resistors sufficient? I think we require only 10mA maximum current to preserve the current actuation range, so 100 V * 10mA = 1W, so 3W leaves some safety margin.
7. All capacitors should be rated for 500 V per the datasheet.
Attachment 1: HV_Bias_schematic.pdf
Attachment 2: TF.pdf
Attachment 3: bias.pdf
Attachment 4: HVbias_currentNoise.pdf
14147   Wed Aug 8 23:06:59 2018 gautamUpdateSUSAnother low noise bias path idea

Today while Rich Abbott was here, Koji and I had a brief discussion with him about the HV amplifier idea for the coil driver bias path. He gave us some useful tips, perhaps most useful being a topology that he used and tested for an aLIGO ITM ESD driver which we can adapt to our application. It uses a PA95 high voltage amplifier which differs from the PA91 mainly in the output voltage range (up to 900V for the former, "only" 400V for the former. He agrees with the overall design idea of

• Having a LN opamp with the HV amp inside the feedback loop for better voltage noise at low frequencies.
• Having a passive RC network at the output of the HV amp to filter out noise at high frequencies.

He also gave some useful suggestions like

• Using the front panel of the box that as a heatsink for the HV amps.
• Testing the stability of the nested opamp loop by "pinging" the output of the opamp with some pulses from a function generator and monitoring the response to this perturbation on a scope.

I am going to work on making a prototype version of this box for 5 channels that we can test with ETMX. I have been told that the coupling from side coil to longitudinal motion is of the order of 1/30, in which case maybe we only need 4 channels.

14150   Thu Aug 9 12:40:14 2018 gautamUpdateSUSETMX trip follow-up

A brief follow-up on this since we discussed this at the meeting yesterday: the attached DV screenshot shows the full 2k data for a period of 2 seconds starting just before the watchdog tripped. It is clear that the timescale of the glitch in the UL channel is much faster (~50 ms) compared to the (presumably mechanical) timescale seen in the other channels of ~250 ms, with the step also being much smaller (a few counts as opposed to the few thousand counts seen in the UL channel, and I guess 1 OSEM count ~ 1 um). All this supports the hypothesis that the problem is electrical and not mechanical (i.e. I think we can rule out the Acromag sending a glitchy signal to the coil and kicking the optic). The watchdog itself gets tripped because the tripping condition is the RMS of the shadow sensor outputs, which presumably exceeds the set threshold when UL glitches by a few thousand counts.

Attachment 1: ETMXglitch.png
14156   Mon Aug 13 09:56:23 2018 SteveUpdateSUSETMX trip follow-up

Here is an other big one

 Quote: A brief follow-up on this since we discussed this at the meeting yesterday: the attached DV screenshot shows the full 2k data for a period of 2 seconds starting just before the watchdog tripped. It is clear that the timescale of the glitch in the UL channel is much faster (~50 ms) compared to the (presumably mechanical) timescale seen in the other channels of ~250 ms, with the step also being much smaller (a few counts as opposed to the few thousand counts seen in the UL channel, and I guess 1 OSEM count ~ 1 um). All this supports the hypothesis that the problem is electrical and not mechanical (i.e. I think we can rule out the Acromag sending a glitchy signal to the coil and kicking the optic). The watchdog itself gets tripped because the tripping condition is the RMS of the shadow sensor outputs, which presumably exceeds the set threshold when UL glitches by a few thousand counts.

Attachment 1: ETMXglitch.png
Attachment 2: ETMXgltch.png
14165   Wed Aug 15 19:18:07 2018 gautamUpdateSUSAnother low noise bias path idea

I took another pass at this. Here is what I have now:

Attachment #1: Composite amplifier design to suppress voltage noise of PA91 at low frequencies.

Attachment #2: Transfer function from input to output.

Attachment #3: Top 5 voltage noise contributions for this topology.

Attachment #4: Current noises for this topology, comparison to current noise from fast path and slow DAC noise.

Attachment #5: LISO file for this topology.

Looks like this will do the job. I'm going to run this by Rich and get his input on whether this will work (this design has a few differences from Rich's design), and also on how to best protect from HV incidents.

Attachment 1: HV_Bias.pdf
Attachment 2: HVamp_TF.pdf
Attachment 3: HVamp_noises.pdf
Attachment 4: currentNoises.pdf
Attachment 5: HVamp.fil.zip
14169   Thu Aug 16 23:06:50 2018 gautamUpdateSUSAnother low noise bias path idea

I had a very fruitful discussion with Rich about this circuit today. He agreed with the overall architecture, but made the following suggestions (Attachment #1 shows the circuit with these suggestions incorporated):

1. Use an Op27 instead of LT1128, as it is a more friendly part especially in these composite amplifier topologies. I confirmed that this doesn't affect the output voltage noise at 100 Hz, we will still limited by Johnson noise of the 15kohm series resistor.
2. Take care of voltage distribution in the HV feedback path
• I overlooked the fact that the passive filtering stage means that the DC current we can drive in the configuration I posted earlier is 150V / 25kohm = 6mA, whereas we'd like to be able to drive at least 10 mA, and probably want the ability to do 12 mA to leave some headroom.
• At the same time, the feedback resistance shouldn't be too small such that the PA91 has to drive a significant current in the feedback path (we'd like to save that for the coil).
• Changing the supply voltage of the PA91 from 150 V to 320 V, and changing the gain to x30 instead of x15 (by changing the feedback resistor from 14kohm to 29kohm), we can still drive 12 mA through the 25 kohms of series resistance. This will require getting new HV power supplies, as the KEPCO ones we have cannot handle these numbers.
• The current limiting resistor is chosen to be 25ohms such that the PA91 is limited to ~26 mA. Of this, 300V / 30kohm ~ 10 mA will flow in the feedback path, which means under normal operation, 12 mA can safely flow through the coils.
• Rich recommended using metal film resistors in the high voltage feedback path. However, these have a power rating, and also a voltage rating. By using 6x 5kohm resistors, the max power dissipated in each resistor is 50^2 / 5000 ~ 0.5 W, so we can get 0.6 W (or 1W?)  rated resistors which should do the job. I think the S102K or S104K series will do the job.
3. Add a voltage monitoring capability.
• This is implemented via a resistive voltage divider at the output of the PA91.
• We can use an amplifier stage with whitening if necessary, but I think simply reading off the voltage across the terminating resistor in the ladder will be sufficient since this circuit will only have DC authority.
4. Make a Spice model instead of LISO, to simulate transient effects.
• I've made the model, investigating transients now.
5. High voltage precautions:
• When doing PCB layout, ensure the HV points have more than the default clearance. Rich recommends 100 mils.
• Use a dual-diode (Schottky) as input protection for the Op27 (not yet implemented in Spice model).
• Use a TVS diode for the moniotring circuit (not yet implemented in Spice model).
• Make sure resistors and capacitors that see high voltage are rated with some safety margin.
6. Consider using the PA95 (which Rich has tested and approves of) instead of the PA91. Does anyone have any opinions on this?

If all this sounds okay, I'd like to start making the PCB layout (with 5 such channels) so we can get a couple of trial boards and try this out in a couple of weeks. Per the current threat matrix and noises calculated, coil driver noise is still projected to be the main technical noise contribution in the 40m PonderSqueeze NB (more on this in a separate elog).

 Quote: Looks like this will do the job. I'm going to run this by Rich and get his input on whether this will work (this design has a few differences from Rich's design), and also on how to best protect from HV incidents.
Attachment 1: HVamp_schem.PDF
Attachment 2: Hvamp.zip
14178   Thu Aug 23 08:24:38 2018 SteveUpdateSUSETMX trip follow-up

Glitch, small amplitude, 350 counts  &  no trip.

Quote:

Here is an other big one

 Quote: A brief follow-up on this since we discussed this at the meeting yesterday: the attached DV screenshot shows the full 2k data for a period of 2 seconds starting just before the watchdog tripped. It is clear that the timescale of the glitch in the UL channel is much faster (~50 ms) compared to the (presumably mechanical) timescale seen in the other channels of ~250 ms, with the step also being much smaller (a few counts as opposed to the few thousand counts seen in the UL channel, and I guess 1 OSEM count ~ 1 um). All this supports the hypothesis that the problem is electrical and not mechanical (i.e. I think we can rule out the Acromag sending a glitchy signal to the coil and kicking the optic). The watchdog itself gets tripped because the tripping condition is the RMS of the shadow sensor outputs, which presumably exceeds the set threshold when UL glitches by a few thousand counts.

Attachment 1: ETMX-UL_glitch.png
Attachment 2: PEM_4d.png
14184   Fri Aug 24 14:58:30 2018 SteveUpdateSUSETMX trips again

The second big glich trips ETMX sus. There were small earth quakes around the glitches. It's damping recovered.

Quote:

Glitch, small amplitude, 350 counts  &  no trip.

Quote:

Here is an other big one

 Quote: A brief follow-up on this since we discussed this at the meeting yesterday: the attached DV screenshot shows the full 2k data for a period of 2 seconds starting just before the watchdog tripped. It is clear that the timescale of the glitch in the UL channel is much faster (~50 ms) compared to the (presumably mechanical) timescale seen in the other channels of ~250 ms, with the step also being much smaller (a few counts as opposed to the few thousand counts seen in the UL channel, and I guess 1 OSEM count ~ 1 um). All this supports the hypothesis that the problem is electrical and not mechanical (i.e. I think we can rule out the Acromag sending a glitchy signal to the coil and kicking the optic). The watchdog itself gets tripped because the tripping condition is the RMS of the shadow sensor outputs, which presumably exceeds the set threshold when UL glitches by a few thousand counts.

Attachment 1: glitches.png
14188   Wed Aug 29 09:20:27 2018 SteveUpdateSUSlocal 4.4M earth quake

All suspension tripped. Their damping restored. The MC is locked.

ITMX-UL & side magnets are stuck.

Attachment 1: 4.4_La_Verne.png
Attachment 2: 3.4_&_4.4M_EQ.png
14190   Wed Aug 29 11:46:27 2018 JonUpdateSUSlocal 4.4M earth quake

I freed ITMX and coarsely realigned the IFO using the OPLEVs. All the alignments were a bit off from overnight.

The IFO is still only able to lock in MICH mode currently, which was the situation before the earthquake. This morning I additionally tried restoring the burt state of the four machines that had been rebooted in the last week (c1iscaux, c1aux, c1psl, c1lsc) but that did not solve it.

 Quote: All suspension tripped. Their damping restored. The MC is locked. ITMX-UL & side magnets are stuck.

14201   Thu Sep 20 08:17:14 2018 SteveUpdateSUSlocal 3.4M earth quake

M3.4 Colton shake did not trip sus.

Attachment 1: local_3.4M.png
14223   Mon Oct 1 22:20:42 2018 gautamUpdateSUSPrototyping HV Bias Circuit

Summary:

I've been plugging away at Altium prototyping the high-voltage bias idea, this is meant to be a progress update.

Details:

I need to get footprints for some of the more uncommon parts (e.g. PA95) from Rich before actually laying this out on a PCB, but in the meantime, I'd like feedback on (but not restricted to) the following:

1. The top-level diagram: this is meant to show how all this fits into the coil driver electronics chain.
• The way I'm imagining it now, this (2U) chassis will perform the summing of the fast coil driver output to the slow bias signal using some Dsub connectors (existing slow path series resistance would simply be removed).
• The overall output connector (DB15) will go to the breakout board which sums in the bias voltage for the OSEM PDs and then to the satellite box.
• The obvious flaw in summing in the two paths using a piece of conducting PCB track is that if the coil itself gets disconnected (e.g. we disconnect cable at the vacuum flange), then the full HV appears at TP3 (see pg2 of schematic). This gets divided down by the ratio of the series resistance in the fast path to slow path, but there is still the possibility of damaging the fast-path electronics. I don't know of an elegant design to protect against this.
2. Ground loops: I asked Johannes about the Acromag DACs, and apparently they are single ended. Hopefully, because the Sorensens power Acromags, and also the eurocrates, we won't have any problems with ground loops between this unit and the fast path.
3. High-voltage precautons: I think I've taken the necessary precautions in protecting against HV damage to the components / interfaced electronics using dual-diodes and TVSs, but someone more knowledgable should check this. Furthermore, I wonder if a Molex connector is the best way to bring in the +/- HV supply onto the board. I'd have liked to use an SHV connector but can't find a comaptible board-mountable connector.
4.  Choice of HV OpAmp: I've chosen to stick with the PA95, but I think the PA91 has the same footprint so this shouldn't be a big deal.
5.  Power regulation: I've adapted the power regulation scheme Rich used in D1600122 - note that the HV supply voltage doesn't undergo any regulation on the board, though there are decoupling caps close to the power pins of the PA95. Since the PA95 is inside a feedback loop, the PSRR should not be an issue, but I'll confirm with LTspice model anyways just in case.
6. Cost:
• ​​Each of the metal film resistors that Rich recommended costs ~$15. • The voltage rating on these demand that we have 6 per channel, and if this works well, we need to make this board for 4 optics. • The PA95 is ~$150 each, and presumably the high voltage handling resistors and capacitors won't be cheap.
• Steve will update about his HV supply investigations (on a secure platform, NOT the elog), but it looks like even switching supplies cost north of \$1200.
• However, as I will detail in a separate elog, my modeling suggests that among the various technical noises I've modeled so far, coil driver noise is still the largest contribution which actually seems to exceed the unsqueezed shot noise of ~ 8e-19 m/rtHz for 1W input power and PRG 40 with 20ppm RT arm losses, by a smidge (~9e-19 m/rtHz, once we take into account the fast and slow path noises, and the fact that we are not exactly Johnson noise limited).

I also don't have a good idea of what the PCB layer structure (2 layers? 3 layers? or more?) should be for this kind of circuit, I'll try and get some input from Rich.

*Updated with current noise (Attachment #2) at the output for this topology of series resistance of 25 kohm in this path. Modeling was done (in LTspice) with a noiseless 25kohm resistor, and then I included the Johnson noise contribution of the 25k in quadrature. For this choice, we are below 1pA/rtHz from this path in the band we care about. I've also tried to estimate (Attachment #3) the contribution due to (assumed flat in ASD) ripple in the HV power supply (i.e. voltage rails of the PA95) to the output current noise, seems totally negligible for any reasonable power supply spec I've seen, switching or linear.

Attachment 1: CoilDriverBias.pdf
Attachment 2: currentNoise.pdf
Attachment 3: PSRR.pdf
14261   Thu Oct 18 00:27:37 2018 KojiUpdateSUSSUS PD Whitening board inspection

[Gautam, Koji]

As a part of the preparation for the replacement of c1susaux with Acromag, I made inspection of the coil-osem transfer function measurements for the vertex SUSs.

The TFs showed typical f^-2 with the whitening on except for ITMY UL (Attachment 1). Gautam told me that this is a known issue for ~5 years.
We made a thorough inspection/replacement of the components and identified the mechanism of the problem.
It turned out that the inputs to MAX333s are as listed below.

 Whitening ON Whitening OFF UL ~12V ~8.6V LL 0V 15V UR 0V 15V LR 0V 15V SD 0V 15V

The switching voltage for UL is obviously incorrect. We thought this comes from the broken BIO board and thus swapped the corresponding board. But the issue remained. There are 4 BIO boards in total on c1sus, so maybe we have replaced a wrong board?

Initially, we thought that the BIO can't drive the pull-up resistor of 5KOhm from 15V to 0V (=3mA of current). So I have replaced the pull-up resistor to be 30KOhm. But this did not help. These 30Ks are left on the board.

Attachment 1: 43.png
14319   Mon Nov 26 17:16:27 2018 gautamUpdateSUSEY chamber work

[steve, rana, gautam]

• PSL and EY 1064nm laser (physical) shutters on the head were closed so that we and sundance crew could work without laser safety goggles. EY oplev laser was also turned off.
• Cylindrical heater setup removed:
• heater wiring meant the heater itself couldn't be easily removed from the chamber
• two lenses and Al foil cylinder removed from chamber, now placed on the mini-cleanroom table.
• Parabolic heater is untouched for now. We can re-insert it once the test mass is back in, so that we can be better informed about the clipping situation.
• ETMY removed from chamber.
• EQ stops were engaged.
• Pictures were taken
• OSEMs were removed from cage, placed in foil holders.
• Cage clamps were removed after checking that marker clamps were in place.
• Optic was moved first to NW corner of table, then out of the vacuum onto the mini-cleanroom desk Chub and I had setup last week.
• Hoepfully there isn't an earthquake. EY has been marked as off-limits to avoid accidental bumping / catasrophic wire/magnet/optic breaking.
• We sealed up the mini cleanroom with tape. F.C. cleaning tomorrow or at another opportune moment.
• Light door was put back on for the evening.

Rana pointed out that the OSEM cabling, because of lack of a plastic shielding, is grounded directly to the table on which it is resting. A glass baking dish at the base of the seismic stack prevents electrical shorting to the chamber. However, there are some LEMO/BNC cables as well on the east side of the stack, whose BNC ends are just lying on the base of the stack. We should use this opportunity to think about whether anything needs to be done / what the influence of this kind of grounding is (if any) on actuator noise.

Steve also pointed out that we should replace the rubber pads which the vacuum chamber is resting on (Attachment #1, not from this vent, but just to indicate what's what). These serve the purpose of relieving small amounts of strain the chamber may experience relative to the beam tube, thus helping preserve the vacuum joints b/w chamber and tube. But after (~20?) years of being under compression, Steve thinks that the rubber no longer has any elasticity, and so should be replaced.

Attachment 1: IMG_5251.JPG
14399   Tue Jan 15 10:52:38 2019 gautamUpdateSUSEY door opened

[chub, bob, gautam]

We took the heavy door off the EY chamber at ~930am.

Chamber work:

• ETMY suspension cage was returned to its nominal position.
• Unused hardware from the annular heater setup was removed.
• The unused heater had its leads snipped close to the heater crimp point, and the exposed part of the bare wires was covered with Kapton tape (we should remove the source leads as well in air to avoid any accidental shorting)

Waiting for the table to level off now. Plan for later today / tomorrow is as follows:

1. Lock the Y arm, recover good cavity alignment.
2. Position parabolic heater such that clipping issue is resolved.
3. Move optic to edge of table for FC cleaning
4. Clean optic
5. Return suspension cage to nominal position.
14401   Tue Jan 15 15:49:47 2019 gautamUpdateSUSEY door opened

While restoring OSEMs on ETMY, I noticed that the open voltages for the UR and LL OSEMs had significantly (>30%) changed from their values from ~2 years ago. The fact that it only occurred in 2 coils seemed to rule out gradual wear and tear, so I looked up the trends from Nov 25 - Nov 28 (Sundance visited on Nov 26 which is when we removed the cage). Not surprisingly, these are the exact two OSEMs that show a decrease in sensor voltage when the OSEMs were pulled out. I suspect that when I placed them in their little Al foil boats, I shorted out some contacts on the rear (this is reminiscent of the problem we had on PRM in 2016). I hope the problem is with the current buffer IC in the satellite box and not the physical diode, I'll test with the tester box and evaluate the problem further.

Chamber work by Chub and gautam:

1. Table leveling was checked with a clean spirit level
• Leveling was substantially off in two orthogonal directions, along the beam axis as well as perpendicular to it.
• We moved almost all the weights available on the table.
• Managed to get the leveling correct to within 1 tick on the level.
• We are not too worried about this for now, the final leveling will be after heater repositioning, ETMY cleaning etc.
2. ETMY OSEM re-insertion
• OSEMs were re-inserted till their mean voltage was ~ half the open values.
• Local damping seems to work just fine.
Attachment 1: EY_OSEMs.png
14403   Wed Jan 16 16:25:25 2019 gautamUpdateSUSYarm locked

[chub, gautam]

Summary:

Y arm was locked at low power in air.

Details:

1. ITMY chamber door was removed at ~10am with Bob's help.
2. ETMY table leveling was found to have drifted significantly (3 ticks on the spirit level, while it was more or less level yesterday, should look up the calib of the spirit level into mrad). Chub moved some weights around on the table, we will check the leveling again tomorrow.
3. IMC was locked.
4. TT2 and brass alignemnt tool was used to center beam on ETMY.
5. TT1 and brass alignment tool was used to center beam on ITMY. We had to do a c1susaux reboot to be able to move ITMY. Usual precautions were taken to avoid ITMX getting stuck.
6. ETMY was used to make return beam from the ETM overlap with the in-going beam near ITMY, using a holey IR card.
7. At this point, I was confident we would see IR flashes so I decided to do the fine alignment in the control room.

We are operating with 1/10th the input power we normally have, so we expect the IR transmission of the Y arm to max out at 1 when well aligned. However, it is hovering around 0.05 right now, and the dominant source of instability is the angular motion of ETMY due to the Oplev loop being non-functional. I am hesitant to do in-chamber work without an extra pair of eyes/hands around, so I'll defer that for tomorrow morning when Chub gets in. With the cavity axis well defined, I plan to align the green beam to this axis, and use the two to confirm that we are well clear of the Parabola.

* Paola, our vertex laptop, and indeed, most of the laptops inside the VEA, are not ideal to work on this kind of alignmment procedure, it would be good to set up some workstations on which we can easily interact with multiple MEDM screens,

Attachment 1: Yarm_locked.png
14407   Fri Jan 18 21:34:18 2019 gautamUpdateSUSUnused optic on EY table

Does anyone know what the purpose of the indicated optic in Attachment #1 is? Can we remove it? It will allow a little more space around the elliptical reflector...

Attachment 1: IMG_5408.JPG
14408   Sat Jan 19 05:07:45 2019 KojiUpdateSUSUnused optic on EY table

I don't think it was used. It is not on the diagram too. You can remove it.

14409   Sat Jan 19 15:33:18 2019 gautamUpdateSUSETMY OSEMs faulty

After diagnosis with the tester box, as I suspected, the fully open DC voltages on the two problematic channels, LL and UR, were restored once I replaced the LM6321 ICs in those two channel paths. However, I've been puzzled by the inability to turn on the Oplev loops on ETMY. Furthermore, the DC bias voltages required to get ETMY to line up with the cavity axis seemed excessively large, particularly since we seemed to have improved the table levelling.

I suspected that the problem with the OSEMs hasn't been fully resolved, so on Thursday night, I turned off the ETMY watchdog, kicked the optic, and let it ringdown. Then I looked at the time-series (Attachment #1) and spectra (Attachment #2) of the ringdowns. Clearly, the LL channel seems to saturate at the lower end at ~440 counts. Moreover, in the time domain, it looks like the other channels see the ringdown cleanly, but I don't see the various suspension eigenmodes in any of the sensor signals. I confirmed that all the magnets are still attached to the optic, and that the EQ stops are well clear of the optic, so I'm inclined to think that this behavior is due to an electrical fault rather than a mechanical one.

For now, I'll start by repeating the ringdown with a switched out Satellite Box (SRM) and see if that fixes the problem.

 Quote: While restoring OSEMs on ETMY, I noticed that the open voltages for the UR and LL OSEMs had significantly (>30%) changed from their values from ~2 years ago. The fact that it only occurred in 2 coils seemed to rule out gradual wear and tear, so I looked up the trends from Nov 25 - Nov 28 (Sundance visited on Nov 26 which is when we removed the cage). Not surprisingly, these are the exact two OSEMs that show a decrease in sensor voltage when the OSEMs were pulled out. I suspect that when I placed them in their little Al foil boats, I shorted out some contacts on the rear (this is reminiscent of the problem we had on PRM in 2016). I hope the problem is with the current buffer IC in the satellite box and not the physical diode, I'll test with the tester box and evaluate the problem further.
Attachment 1: Screen_Shot_2019-01-19_at_3.32.35_PM.png
Attachment 2: ETMY_sensors_1231832635.pdf
14411   Tue Jan 22 20:36:53 2019 gautamUpdateSUSETMY OSEMs faulty

Short update on latest Satellite box woes.

1. I checked the resistance of all 5 OSEM coils on ETMY using a DB25 breakout board and a multimeter - all were between 16-17 ohms (mesured from the cable to the Vacuum flange), which I think is consistent with the expected value.
2. Checked the bias voltage (aka slow path) from the coil driver board was reaching the coils
• The voltages were indeed being sent out of the coil driver board - I confirmed by driving a slow sine wave and measuring at the output of the coil driver board, with all the fast outputs disabled.
• The voltage is arriving at the 64 pin IDC connector at the Satellite box - Chub and I verified this using some mini-grabbers and leads from wirewound resistors (we don't have a breakout board for this kind of connector, would be handy to get some!)
• However, the voltages are not being sent out through the DB25 connectors on the side of the Satellite box, at least for the LL and UR channels. UL seems to work okay.
• This behavior is consistent with the observation that we had to apply way larger bias voltages to get the cavity axis to line up than was the nominal values - if one or more coils weren't getting their signals, it would also explain the large PIT->YAW coupling I observed using the Oplev spot and the slow bias alignment EPICS sliders.
• This behavior is puzzling - the Sat box is just supposed to be a feed-through for the coil driver signals, and we measured resistances between the 64 pin IDC connector and the corresponding DB25 pins, and measured in the range of 0.2-0.3 ohms. However, the voltage fails to make it through - not sure what's going on here.. We will investigate further on the electronics bench.

What's more - I did some Sat box switcheroo, swapping the SRM and ETM boxes back and forth in combination with the tester box. In the process, I seem to have broken the SRM sat box - all the shadow sensors are reporting close to 0 volts, and this was confirmed to be an electronic problem as opposed to some magnet skullduggery using the tester box. Once we get to the bottom of the ETMY sat box, we will look at SRM. This is more or less the last thing to look at for this vent - once we are happy the cavity axis can be recovered reliably, we can freeze the position of the elliptical reflector and begin the F.C.ing.

14413   Wed Jan 23 12:39:18 2019 gautamUpdateSUSEY chamber work

While Chub is making new cables for the EY satellite box...

1. I removed the unused optic on the NW corner of the EY table. It is stored in a clean Al-foil lined plastic box, and will be moved to the clean hardware section of the lab (along the South arm, south of MC2 chamber).
2. Checked table leveling - Attachment #1, looked good, and has been stable over the weekend.
3. I moved the two oversized washers on the reflector, which I believe are only used because the screw is long and wouldn't go in all the way otherwise. As shown in Attachment #2, this reduces the risk of clipping the main IFO beam axis.
4. Yesterday, I pulled up the 40m CAD drawing, and played around with a rectangular box that approximates the extents of the elliptical reflector, to see what would be a good place to put it. I chose to go ahead with Attachment #3. Also shown is the eventually realized layout. Note that we'd actually like the dimension marked ~7.6 inches to be more like 7.1 inches, so the optic is actually ~0.5 inch ahead of the second focus of the ellipse, but I think this is good enough.
5. Attachment #4 shows the view of the optic as seen from the aperture on the back of the elliptical reflector. Looks good to me.
6. Having positioned the reflector, I then inserted the heater into the aperture such that it is ~2/3rds the way in, which was the best position found by Annalisa last summer. I then ran 0.9 A of current through the heater for ~ 5 minutes. Attachment #5 shows the optic as seen with the FLIR with no heating, and after 5 minutes of heating. I'd say this is pretty unambiguous evidence that we are indeed heating the mirror. The gradient shown is significantly less pronounced than in Annalisa's simulations (~3K as opposed to 10K), but maybe the FLIR calibration isn't so great.
7. For completeness, Attachment #6 shows the leveling of the table after this work. Nothing has chanegd significantly.

While the position of the reflector could possibly be optimized further, since we are already seeing a temperature gradient on the optic, I propose pushing on with other vent activities. I'm almost certain the current positioning places the optic closer to the second focus, and we already saw shifts of the HOM resonances with the old configuration, so I'd say we run with this and revisit if needed.

If Chub gives the Sat. Box the green flag, we will work on F.C.ing the mirrors in the evening, with the aim of closing up tomorrow/Friday.

All raw images in this elog have been uploaded to the 40m google photos.

Attachment 1: leveling.pdf
Attachment 2: IMG_5930.jpg
Attachment 3: Ellipse_layout.pdf
Attachment 4: IMG_5932.jpg
Attachment 5: hotMirror.pdf
Attachment 6: EY_leveling_after.pdf
14415   Wed Jan 23 23:12:44 2019 gautamUpdateSUSPrep for FC cleaning

In preparation for the FC cleaning, I did the following:

1. Set up mini-cleanroom at EY - this consists of the mobile HEPA unit put up against the chamber door, with films draped around the setup.
2. After double-checking the table leveling, I EQ-stopped ETMY and moved it to the NE corner of the EY table, where it will be cleaned.
3. Checked leveling of IY table - see Attachment #1.
4. Took pictures of IY table, OSEM arrangement on ITMY.
5. EQ-stopped ITMY and SRM.
6. Removed the face OSEMs from ITMY (this required clipping off the copper wire used to hold the OSEM wires against the suspension cage). The side OSEM has not yet been removed because I left the allen key that is compatible with that particular screw inside the EY chamber.
7. To position ITMY at the edge of the IY table where we can easily clean it, we will need to move the OSEM cabling tower as we did last time. I've taken photos of its current position for now.

Tomorrow, I will start with the cleaning of ETMY HR. While the FC is drying, I will position ITMY at the edge of the IY cable for cleaning (Chub will setup the mini-cleanroom at the IY table). The plan is to clean both HR surfaces and have the optics back in place by tomorrow evening. By my count, we have done everything listed in the IY and EY chambers. I'd like to minimize the time between cleaning and pumpdown, so if all goes well (Sat Box problems notwithstanding), we will check the table leveling on Friday morning, and put on the heavy doors and at least rough the main volume down to 1 torr on Friday.

Attachment 1: IY_level_before.pdf
14416   Thu Jan 24 15:32:31 2019 gautamUpdateSUSY arm cavity side first contact applied

EY:

• A clean cart was setup adjacent to the HEPA-enclosed mini cleanroom area (it cannot be inside the mini cleanroom, because of lack of space).
• The FC tools (first contact, acetone, beakers, brushes, PEEK mesh, clean scissors, clean tweezers, Canon camera, green flashlight) were laid out on this cart for easy access.
• I inspected the optic - the barrel had a few specks of dust, and the outer 1.5" annular region of the HR face looked to have some streak marks
• I was advised not to pre-wipe the HR side with any solvents
• The FC was only applied to the centran ~1-1.5" of the optic
• After applying the FC, I spent a few minutes inspecting the status of the OSEMs
• Three out of the four face OSEMs, as well as the side OSEM, did not have a filter in
• I inserted filters into them.
• Closed up the chamber with light door, left HEPA unit on and the mini cleanroom setup intact for now. We will dismantle everything after the pumpdown.

IY:

• Similar setup to EY was implemented
• Removed side OSEM from ITMY.
• Double-checked that EQ stops were engaged.
• Moved the OSEM cable tower to free up some space for accommodating ITMY.
• Undid the clamps of ITMY, moved it to the NE corner of the IY table.
• Inspected the optic - it was much cleaner than the 2016 inspection, although the barrel did have some specks of dust.
• Once again, I applied first contact to the central ~1.5" of the HR surface.
• Checked status of filters on OSEMs - this time, only the UL coil required a filter.
• Attachment #3 shows the sensor voltage DC level before and after the insertion of the filter. There is ~0.1% change.
• The filters were found in a box that suggests they were made in 2002 - but Steve tells me that it is just stored in a box with that label, and that since there are >100 filters inside that box, he thinks they are the new ones we procured in 2016. The coating specs and type of glass used are different between the two versions.

The attached photo shows the two optics with FC applied.

My original plan was to attempt to close up tomorrow. However, we are still struggling with Satellite box issues. So rather than rush it, we will attempt to recover the Y arm cavity alignment on Monday, satellite box permitting. The main motivation is to reduce the deadtime between peeling off the F.C and starting the pumpdown. We will start working on recovering the cavity alignment once the Sat box issues are solved.

Attachment 1: Yarm_FC.pdf
Attachment 2: OSEMfilter.png
14422   Tue Jan 29 22:12:40 2019 gautamUpdateSUSAlignment prep

Since we may want to close up tomorrow, I did the following prep work:

1. Cleaned up Y-end suspension eleoctronics setup, connected the Sat Box back to the flange
• The OSEMs are just sitting on the table right now, so they are just seeing the fully open voltage
• Post filter insertion, the four face OSEMs report ~3-4% lower open-voltage values compared to before, which is compatible with the transmission spec for the filters (T>95%)
• The side OSEM is reporting ~10% lower - perhaps I just didn't put the filter on right, something to be looked at inside the chamber
2. Suspension watchdog restoration
• I'd shutdown all the watchdogs during the Satellite box debacle
• However, I left ITMY, ETMY and SRM tripped as these optics are EQ-stopped / don't have the OSEMs inserted.
3. Checked IMC alignment
• After some hand-alignment of the IMC, it was locked, transmission is ~1200 counts which is what I remember it being
4. Checked X-arm alignment
• Strictly speaking, this has to be done after setting the Y-arm alignment as that dictates the input pointing of the IMC transmission to the IFO, but I decided to have a quick look nevertheless
• Surprisingly, ITMX damping isn't working very well it seems - the optic is clearly swinging around a lot, and the shadow sensor RMS voltage is ~10s of mV, whereas for all the other optics, it is ~1mV.
• I'll try the usual cable squishing voodoo

Rather than try and rush and close up tomorrow, I propose spending the day tomorrow cleaning the peripheral areas of the optic, suspension cage, and chamber. Then on Thursday morning, we can replace the Y-arm optics, try and recover the cavity alignment, and then aim for a Thursday afternoon pumpdown. The main motivation is to reduce the time the optics spend in air after F.C. peeling and going to vacuum.

14423   Wed Jan 30 11:54:24 2019 gautamUpdateSUSMore alignment prep

[chub, gautam]

1. ETMY cage was wiped down
• Targeted potential areas where dust could drift off from and get attracted to a charged HR surface
• These areas were surprisingly dusty, even left a grey mark on the wipe [Attachment #1] - we think we did a sufficiently thorough job, but unclear if this helps the loss numbers
• More pictures are on gPhoto
2. Filters on SD and LR OSEMs were replaced - the open shadow sensor voltages with filters in/out are consistent with the T>95% coating spec.
3. IPANG beam position was checked
• It is already too high, missing the first steering optic by ~0.5 inch, not the greatest photo but conclusion holds [Attachment #2].
• I think we shouldn't worry about it for this pumpdown, we can fix it when we put in the new PR3.
4. Cage wiping procedure was repeated on ITMY
• The cage was much dustier than ETMY
• However, the optic itself (barrel and edge of HR face) was cleaner
• All accessible areas were wiped with isopropanol
• Before/after pics are on gPhoto (even after cleaning, there are some marks on the suspension that looks like dust, but these are machining marks)

Procedure tomorrow [comments / suggestions welcome]:

• Peel first contact with TopGun jet flowing
• Inspect optic face with green flashlight to check for residual First Contact
• Replace ITMY suspension cage in its position, clamp it down
• Release ITMY from its EQ stops
• Replace OSEMs in ITMY cage, best effort to recover previous alignment of OSEMs in their holders (I have a photo before removal of OSEMs), which supposedly minimized the coupling of the B-R modes into the shadow sensor signals
• Best effort to have shadow sensor PD outputs at half their fully open voltages (with DC bias voltage applied)
• Quick check that we are hitting the center of the ITM with the alignment tool
• Check that the Oplev HeNe is reasonably centered on steering mirrors
• Tie down OSEM cabling to the ITMY cage with clean copper wire
• Replace the OSEM wiring tower
• Release the SRM from its EQ stops
• Check table leveling
• Take pictures of everything, check that we have not left any tools inside the chamber
• Heavy doors on
2. Next, EY chamber
• Repeat first seven bullets from the IY chamber, :%s/ITMY/ETMY/g
• Confirm sufficient clearance between IFO beam axis and the elliptical reflector
• Check Oplev beam path
• Check table leveling
• Take pictures of everything, check that we have not left any tools inside the chamber
• Heavy doors on
3. IFO alignment checks - basically follow the wiki, we want to be able to lock both arms (or at least see TEM00 resonances), and see that the PRC and SRC mode flashes look reasonable.
4. Tighten all heavy doors up
5. Pump down

Attachment 1: IMG_5958.JPG
Attachment 2: IMG_5962.JPG
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