40m QIL Cryo_Lab CTN SUS_Lab TCS_Lab OMC_Lab CRIME_Lab FEA ENG_Labs OptContFac Mariner WBEEShop
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ID Date Authorup Type Category Subject
  14126   Thu Aug 2 20:54:18 2018 gautamSummaryComputersc1omc model looks stable

Actually, c1lsc had crashed again sometime last night so I had to reboot everything this morning. I used the reboot script again, but I increased the sleep time between trying to start up the models again so that I could walk into the VEA and power cycle the c1lsc expansion chassis, as this kind of frequent model crash has been fixed by doing so in the past. Sure enough, there have been no issues since I rebooted everything at ~1030 in the morning. 

The c1omc model itself has been stable as well, though of course, there is nothing in there at the moment. I may do a check of the newly installed DAC tomorrow just to see that we can put out a sine wave.

Steve has ordered the D-sub cabling that will allow us to route signals between AA/AI boards in 1X1/1X2 to the HV PZT electronics in the OMC rack. Things look setup for a measurement next week. Aaron will post a block diagram + photoz of what box goes where in the electronics racks.

  14128   Fri Aug 3 14:35:56 2018 gautamSummaryElectronicsEX AUX electronics power restored

Steve and I restored the power to the EX AUX electronics rack. The power strip on the lowest shelf of the AUX rack now goes to another power strip laid out vertically along the NW corner of 1X9. The EX green locks to the arm just fine now.

  14129   Fri Aug 3 15:53:25 2018 gautamUpdateSUSLow noise bias path idea


The idea we are going with to push the coil driver noise contribution down is to simply increase the series resistance between the coil driver board output and the OSEM coil. But there are two paths, one for fast actuation and one that provides a DC current for global alignment. I think the simplest way to reduce the noise contribution of the latter, while preserving reasonable actuation range, is to implement a precision DC high-voltage source. A candidate that I pulled off an LT application note is shown in Attachment #1.


  • The series resistance in the bias path should be 10 k\Omega, such that the noise from this stage is dominated by the Johnson noise of said resistor, and hence, the current noise contribution is negligible compared to the series resistance in the fast actuation path (4.5 k\Omega).
  • Since we only really need this for the test masses, what actuation range do we want?
    • Currently, ETMY has a series resistance of 400\Omega and has a pitch DC bias voltage of -4 V. 
    • This corresponds to 10 mA of DC current.
    • To drive this current through 10 k\Omega, we need 100 V. 
    • I'm assuming we can manually correct for yaw misalignments such that 10mA of DC current will be sufficient for any sort of corrective alignment.
    • So +/- 120 V DC should be sufficient.
  • The current noise of this stage should be negligible at 100 Hz. 
    • The noise of the transistors and the HV supply should be suppressed by the feedback loop and so shouldn't be a significant contribution (I'll model to confirm).
    • The input noise of the LT1055 is ~20nV/rtHz at 100 Hz, while the Johnson noise of 10 k\Omega is ~13nV/rtHz so maybe the low-passing needs to be tuned, but I think if it comes to it, we can implement a passive RC network at the output to achieve additional filtering.
  • To implement this circuit, we need +/- 125V DC. 
    • At EX and EY, we have a KEPCO HV supply meant to be used for the Green Steering PZTs. 
    • I'm not sure if these can do bipolar outputs, if not, for temporary testing, we can transport the unit at EY to EX.

If all this seems reasonable, I'd like to prototype this circuit and test it with ETMX, which already has the high series resistance for the fast path. So I will ask Steve to order the OpAmp and transistors.

Attachment 1: LT1055_precOpAmp.pdf
  14131   Fri Aug 3 18:54:58 2018 gautamUpdateSUSGlitchy MC1

The wall StripTool indicated that the IMC wasn't too happy when I came in today. Specifically:

  • MC1 watchdog was tripped.
  • Even in the tripped state, MC REFL spot on the camera showed spot motion that was too large to be explained as normal seismic driven motion (i.e. with local damping supposedly disabled).
  • Strange excursions were observed in the MC1 shadow sensor signal levels as well, see Attachment #1 - negative values don't make any sense for this readout.

The last time this happened, it was due to the Sorensens not spitting out the correct voltages. This time, there were no indications on the Sorensens that anything was funky. So I just disabled the MCautolocker and figured I'd debug later in the evening.

However, around 5pm, the shadow sensor values looked nominal again, and when I re-enabled the local damping, the MC REFL spot suggested that the local damping was working just fine. I re-enabled the MCautolocker, MC re-locked almost immediately. To re-iterate, I did nothing to the electronics inside the VEA. Anyways, this enabled us to work on the X arm ASS (next elog).

Attachment 1: MC1_sensorAnomaly.png
  14132   Fri Aug 3 19:02:11 2018 gautamUpdateASSX arm ASS recovery

[koji, gautam]

After I effected the series resistance change for ETMX, the X arm ASS didn't work (i.e. IR transmission would degrade if the servo was run). Today, we succeeded in recovering a functional ASS servo yes.

So both arms have working dither alignment servos now. But remember that the Y arm ASS gains have been set for locking the Y arm with MC2 as the actuator, not ETMY.


  • Koji pointed out that the demodulated signals from the ETM dither are only used to center the spot on the ETM, and that we should first run the servo with existing settings with the ETM pitch and yaw spot centering loops disabled.
    • This improved TRX level from ~0.8 to 1.1
  • Next, we tried increasing the LO amplitudes by x5 to account for the reduced actuation of the dither on ETMX
    • We then re-enabled the two loops that were earlier disabled.
    • This resulted in TRX degrading very quickly.
  • So we decided to try going back to the nominal LO gains, and reducing the gain of the two ETM spot centering loops.
    • This did the trick, TRX went from 1.1 --> ~1.23, which is the nominal maximum pre-vent value.
  • The snap file used to recover the correct settings to run the dither alignment servos have been updated, the old one has been backed up with today's datestamp.

We then tried to maximize GTRX using the PZT mirrors, but were only successful in reaching a maximum of 0.41. The value I remember from before the vent was 0.5, and indeed, with the IR alignment not quite optimized before we began this work, I saw GTRX of 0.48. But the IR dither servo signals indicate that the cavity axis may have shifted (spot position on the ITM, which is uncontrolled, seems to have drifred significantly, the Pitch signal doesn't stay on the StripTool scale anymore). So we may have to double check that the transmitted beam isn't falling off the GTRX DC PD.

  14133   Sun Aug 5 13:28:43 2018 gautamUpdateCDSc1lsc flaky

Since the lab-wide computer shutdown last Wednesday, all the realtime models running on c1lsc have been flaky. The error is always the same:

[58477.149254] c1cal: ADC TIMEOUT 0 10963 19 11027
[58477.149254] c1daf: ADC TIMEOUT 0 10963 19 11027
[58477.149254] c1ass: ADC TIMEOUT 0 10963 19 11027
[58477.149254] c1oaf: ADC TIMEOUT 0 10963 19 11027
[58477.149254] c1lsc: ADC TIMEOUT 0 10963 19 11027
[58478.148001] c1x04: timeout 0 1000000 
[58479.148017] c1x04: timeout 1 1000000 
[58479.148017] c1x04: exiting from fe_code()

This has happened at least 4 times since Wednesday. The reboot script makes recovery easier, but doing it once in 2 days is getting annoying, especially since we are running many things (e.g. ASS) in custom configurations which have to be reloaded each time. I wonder why the problem persists even though I've power-cycled the expansion chassis? I want to try and do some IFO characterization today so I'm going to run the reboot script again but I'll get in touch with J Hanks to see if he has any insight (I don't think there are any logfiles on the FEs anyways that I'll wipe out by doing a reboot). I wonder if this problem is connected to DuoTone? But if so, why is c1lsc the only FE with this problem? c1sus also does not have the DuoTone system set up correctly...

The last time this happened, the problem apparently fixed itself so I still don't have any insight as to what is causing the problem in the first place frown. Maybe I'll try disabling c1oaf since that's the configuration we've been running in for a few weeks.

  14134   Sun Aug 5 13:45:00 2018 gautamUpdateSUSETMX tripped

Independent from the problems the vertex machine has been having (I think, unless it's something happening over the shared memory network), I noticed on Friday that the ETMX watchdog was tripped. Today, once again, the ETMX watchdog was tripped. There is no evidence of any abnormal seismic activity around that time, and anyways, none of the other watchdogs tripped. Attachment #1 shows that this happened ~838am PT today morning. Attachment #2 shows the 2k sensor data around the time of the trip. If the latter is to be believed, there was a big impulse in the UL shadow sensor signal which may have triggered the trip. I'll squish cables and see if that helps - Steve and I did work at the EX electronics rack (1X9) on Friday but this problem precedes our working there...

Attachment 1: ETMX_tripped.png
Attachment 2: ETMX_tripped_zoom.png
  14135   Sun Aug 5 15:43:50 2018 gautamUpdateSUSAnother low noise bias path idea

OK, how about this:

  • Attachment #1 shows the proposed schematic.
    • It consists of a second order section with Gain x10 to map the +/-10V DC range of the DAC to +/- 100V DC such that we preserve roughly the same amount of DC actuation range.
    • Corner frequency of the SOS is set to ~0.7 Hz. In hindsight, maybe this is more aggressive than necessary, we can tune this.
    • DC gain is 20 dB (typo in the text where I say the DC gain is x15, though we could go with this option as well I think if we want a larger series resistance).
    • A first order passive low-pass stage is added to filter out the voltage noise of the PA91, which dominates the output voltage noise (next bullet).
  • Attachment #2 shows the transfer function from input to output
    • The two traces compare having just a single SOS filtering stage vs the current topology of having two SOS stages.
    • The passive output RC network is necessary in either case to filter the voltage noise of the PA91 OpAmp.
    • For the DAC noise, I just assumed a flat noise level of 5 \mu V / \sqrt{\mathrm{Hz}}, I don't actually know what this is for the Acromag DACs.
  • Attachments #3 shows a breakdown of the top 5 noise contributions.
    • The PA91 datasheet doesn't give current noise information so I just assumed 1 fA / \sqrt{\mathrm{Hz}}, which was what was used for the PA85 in the existing opamp.lib file.
    • The voltage noise is modelled as 4.5 \sqrt{1+\frac{80}{f}} nV / \sqrt{\mathrm{Hz}}, which seems to line up okay with the plot on Pg4 of the datasheet.
    • So the model suggests we will be dominated by the voltage noise of the PA91.
  • Attachment #4 translates the noise into current noise seen by the actuator.
    • I add the Johnson noise contribution of the series resistance for this path, which is assumed to be 10 k \Omega.
    • For comparison, I add the filtered DAC noise contribution, and Johnson noise of the proposed series resistance in the fast path.
    • For the bias path, we are dominated by the Johnson noise of the series resistor from ~60 Hz upwards.
    • It's not quite fair to say that the Johnson noise of the resistance in the fast path dominates, the quadrature sum of fast and bais paths will be ~1.2 times of the former alone. 
    • Bottom line: we will be in the regime of total current noise of ~2.2 pA/rtHz, where I think Kevin's modeling suggests we can see some squeezing.

The question still remains of how to combine the fast and bias paths in this proposed scheme. I think the following approach works for prototyping at least:

  • Remove the series resistance on the existing coil driver boards' bias path, hence isolating this from the coil.
  • Route the DB15 output connector from the coil driver board (which is now just the fast actuation signals) into a sub-sattelite box housing the bias path electronics.
  • Sum the two signals as it is done now, by simply having a conductor (PCB trace) merge the two paths after their respective series resistances.

In the longer term, perhaps the Satellite Box revamp can accommodate a bias voltage summation connector.


Bah! Too complex.

I have neglected many practical concerns. Some things that come to mind:

  1. Is it necessary to protect the upstream DAC from some potential failure of the PA91 in which the high voltage appears at the input?
  2. What is the correct OpAmp for this purpose? This chart on Apex's page suggests that PA15, PA85, PA91 and PA98 are all comparable in terms of drive capability, and the spec sheets don't suggest any dramatic differences. Some LIGO circuits use PA85, some use PA90, but I can't find any that use PA91. Perhaps Rana/Koji can comment about this.
  3. What kind of protection is necessary for the PA91 power?
  4. What is the correct way to do heat management? Presumably we need heatsinks, and in fact, there is a variant of the packaging style that has "formed" legs, which from what I can figure out, allow the heat sink plane on the PA91 to be parallel to the PCB surface. But I think the heat-sink wisdom suggests vertical fins are the most efficient (not sure if this holds if the PCB is inside a box though). What about the PCB itself? Are some kind of special traces needed?
  5. Can we use the current-limiting resistor feature on the PA91? The datasheet seems to advice against it for G>10 configurations, which is what we need, although our requirement is only at DC so I don't know if that table is applicable to this circuit.
  6. Are 3W resistors sufficient? I think we require only 10mA maximum current to preserve the current actuation range, so 100 V * 10mA = 1W, so 3W leaves some safety margin.
  7. All capacitors should be rated for 500 V per the datasheet.  
Attachment 1: HV_Bias_schematic.pdf
Attachment 2: TF.pdf
Attachment 3: bias.pdf
Attachment 4: HVbias_currentNoise.pdf
  14136   Mon Aug 6 00:26:21 2018 gautamUpdateCDSMore CDS woes

I spent most of today fighting various CDS errors.

  • I rebooted c1lsc around 3pm, my goal was to try and do some vertex locking and figure out what the implications were of having only ~30% power we used to have at the AS port.
  • Shortly afterwards (~4pm), c1lsc crashed.
  • Using the reboot script, I was able to bring everything back up. But the DC lights on c1sus models were all red, and a 0x4000 error was being reported.
  • This error is indicative of some timing issue, but all the usual tricks (reboot vertex FEs in various order, restart the mx_streams etc) didn't clear this error.
  • I checked the Tempus GPS unit, that didn't report any obvious problems (i.e. front display was showing the correct UTC time).
  • Finally, I decided to shut down all watchdogs, soft reboot all the FEs, soft reboot FB, power cycle all expansion chassis.
  • This seems to have done the trick - I'm leaving c1oaf disabled for now.
  • The remaining red indicators are due to c1dnn and c1oaf being disabled.

Let's see how stable this configuration is. Onto some locking now...

Attachment 1: CDSoverview.png
  14139   Mon Aug 6 14:38:38 2018 gautamUpdateCDSMore CDS woes

Stability was short-lived it seems. When I came in this morning, all models on c1lsc were dead already, and now c1sus is also dead (Attachment #1). Moreover, MC1 shadow sensors failed for a brief period again this afternoon (Attachment #2). I'm going to wait for some CDS experts to take a look at this since any fix I effect seems to be short-lived. For the MC1 shadow sensors, I wonder if the Trillium box (and associated Sorensen) failure somehow damaged the MC1 shadow sensor/coil driver electronics.


Let's see how stable this configuration is. Onto some locking now...

Attachment 1: CDScrash.png
Attachment 2: MC1failures.png
  14140   Mon Aug 6 19:49:09 2018 gautamUpdateCDSMore CDS woes

I've left the c1lsc frontend shutdown for now, to see if c1sus and c1ioo can survive without any problems overnight. In parallel, we are going to try and debug the MC1 OSEM Sensor problem - the idea will be to disable the bias voltage to the OSEM LEDs, and see if the readback channels still go below zero, this would be a clear indication that the problem is in the readback transimpedance stage and not the LED. Per the schematic, this can be done by simply disconnecting the two D-sub connectors going to the vacuum flange (this is the configuration in which we usually use the sat box tester kit for example). Attachment #1 shows the current setup at the PD readout board end. The dark DC count (i.e. with the OSEM LEDs off) is ~150 cts, while the nominal level is ~1000 cts, so perhaps this is already indicative of something being broken but let's observe overnight.

Attachment 1: IMG_7106.JPG
  14142   Tue Aug 7 11:30:46 2018 gautamUpdateCDSMore CDS woes

Overnight, all models on c1sus and c1ioo seem to have had no stability issues, supporting the hypothesis that timing issues stem from c1lsc. Moreover, the MC1 shadow sensor readouts showed no negative values over a ~12hour period. I think we should just observe this for another day, in any case I don't think there is any urgent IFO related activity scheduled.

  14143   Tue Aug 7 22:28:23 2018 gautamUpdateCDSMore CDS woes

I am starting the c1x04 model (IOP) on c1lsc to see how it behaves overnight.

Well, there was apparently an immediate reaction - all the models on c1sus and c1ioo reported an ADC timeout and crashed. I'm going to reboot them and still have c1x04 IOP running, to see what happens.

[97544.431561] c1pem: ADC TIMEOUT 3 8703 63 8767
[97544.431574] c1mcs: ADC TIMEOUT 1 8703 63 8767
[97544.431576] c1sus: ADC TIMEOUT 1 8703 63 8767
[97544.454746] c1rfm: ADC TIMEOUT 0 9033 9 8841

Overnight, all models on c1sus and c1ioo seem to have had no stability issues, supporting the hypothesis that timing issues stem from c1lsc. Moreover, the MC1 shadow sensor readouts showed no negative values over a ~12hour period. I think we should just observe this for another day, in any case I don't think there is any urgent IFO related activity scheduled.

  14146   Wed Aug 8 23:03:42 2018 gautamUpdateCDSc1lsc model started

As part of this slow but systematic debugging, I am turning on the c1lsc model overnight to see if the model crashes return.

  14147   Wed Aug 8 23:06:59 2018 gautamUpdateSUSAnother low noise bias path idea

Today while Rich Abbott was here, Koji and I had a brief discussion with him about the HV amplifier idea for the coil driver bias path. He gave us some useful tips, perhaps most useful being a topology that he used and tested for an aLIGO ITM ESD driver which we can adapt to our application. It uses a PA95 high voltage amplifier which differs from the PA91 mainly in the output voltage range (up to 900V for the former, "only" 400V for the former. He agrees with the overall design idea of 

  • Having a LN opamp with the HV amp inside the feedback loop for better voltage noise at low frequencies.
  • Having a passive RC network at the output of the HV amp to filter out noise at high frequencies.

He also gave some useful suggestions like 

  • Using the front panel of the box that as a heatsink for the HV amps.
  • Testing the stability of the nested opamp loop by "pinging" the output of the opamp with some pulses from a function generator and monitoring the response to this perturbation on a scope.

I am going to work on making a prototype version of this box for 5 channels that we can test with ETMX. I have been told that the coupling from side coil to longitudinal motion is of the order of 1/30, in which case maybe we only need 4 channels.

  14148   Thu Aug 9 02:12:13 2018 gautamUpdateCOCSouth East or West?


For operating the SRC in the "Signal-Recycled" tuning, the SRC macroscopic length needs to be ~4.04m (compared to the current value of ~5.399m), assuming we don't do anything fancy like change the modulation frequencies and not transmit through the IMC. We're putting together a notebook with all the calculations, but today I was thinking about what the signal extraction path should be, specifically which chamber the SRM should be in. Just noting down the thoughts I had here while they're fresh in my head, all this has to be fleshed out, maybe I'm making this out to be more of a problem than it actually is.


  • For the current modulation frequencies, if we want the reosnance conditions such that the f2 sideband is resonant in the SRC (but not f1, i.e. small Schnupp asymmetry regime) while the carrier is resonant in the arms (required for good sensing of the SRC length), the macroscopic length of the SRC needs to be changed to ~4.04m.
  • Practically, this means that the folded SRC would only have one folding mirror (SR2).
  • There is a shorter SRC length of ~1.something metres which would work, but that would involve changing the relative position between ITMs and BS (currently ~2.3m) so I reject that option for now.
  • So the SR2 would be roughly where it is right now, ~20cm from the BS.
  • The question then becomes, where do we direct the reflection from the SR2? We need an optical path length of ~1.5m from SR2. So options are 
    • ITMY table (East)
    • ITMX table (South)
    • IMC table (West)
  • Moreover, after the SRM, we have to accommodate:
    • Some kind of pickoff for in-air PDs.
    • OFI.
    • OMC MMT.
    • OMC.
  • Some kind of CBA (as of now I think going to the ITMY table is the best option):
Option Advantages Disadvantages
  • Easy to direct beam from BS/PRM chamber to the ITMY table (i.e. we don't have to worry too much about avoiding other optics in the path etc).
  • Ease of access to chamber, ease of working in there.
  • ITMY table probably has the most room to work out an OFI + OMC MMT + OMC solution.
  • AS beam extraction to air will be more complicated, possibly have to do it on ITMY optical table.
  • Not sure if the ITMY table can accommodate all of the output optics subsystems I listed above.
  • Routing the LO beam to this table would be tricky I guess.
  • Routing the LO beam for homodyne detection is probably easiest in this chamber.
  • Allows for small AoI on folding mirror, reducing the impact of astigmatism.
  • Pain to work in this chamber because of IMC tube.
  • Steering beam from SR2 to ITMX table means threading the needle between PRM and PR3 possibly.
  • Probably allows the use of (almost) the entire existing OMC chamber for the output optics (OFI, OMC MMT, OMC).
  • IMC table is crowded (2 SOS towers, several steering optics for the input beam, input faraday).
  • Not sure what is the performance of the seismic isolation stacks on these tables vs the larger optical tables.
  • Painful to work in these smaller chambers.
  14149   Thu Aug 9 12:31:13 2018 gautamUpdateCDSCDS status update

The model seems to have run without issues overnight. Not completely related, but the MC1 shadow sensor signals also don't show any abnormal excursions to negative values in the last 48 hours. I'm thinking about re-connecting the satellite box (but preserving the breakout setup at 1X6 for a while longer) and re-locking the IMC. I'll also start c1ass on the c1lsc frontend. I would say that the other models on c1lsc (i.e. c1oaf, c1cal, c1daf) aren't really necessary for basic IFO operation.


As part of this slow but systematic debugging, I am turning on the c1lsc model overnight to see if the model crashes return.

  14150   Thu Aug 9 12:40:14 2018 gautamUpdateSUSETMX trip follow-up

A brief follow-up on this since we discussed this at the meeting yesterday: the attached DV screenshot shows the full 2k data for a period of 2 seconds starting just before the watchdog tripped. It is clear that the timescale of the glitch in the UL channel is much faster (~50 ms) compared to the (presumably mechanical) timescale seen in the other channels of ~250 ms, with the step also being much smaller (a few counts as opposed to the few thousand counts seen in the UL channel, and I guess 1 OSEM count ~ 1 um). All this supports the hypothesis that the problem is electrical and not mechanical (i.e. I think we can rule out the Acromag sending a glitchy signal to the coil and kicking the optic). The watchdog itself gets tripped because the tripping condition is the RMS of the shadow sensor outputs, which presumably exceeds the set threshold when UL glitches by a few thousand counts.

Attachment 1: ETMXglitch.png
  14151   Thu Aug 9 22:50:13 2018 gautamUpdateCDSAlignSoft script modified

After this work of increasing the series resistance on ETMX, there have been numerous occassions where the insufficient misalignment of ETMX has caused problems in locking vertex cavities. Today, I modified the script (located at /opt/rtcds/caltech/c1/medm/MISC/ifoalign/AlignSoft.py) to avoid such problems. The way the misalign script works is to write an offset value to the "TO_COIL" filter bank (accessed via "Output Filters" button on the Suspension master MEDM screen - not the most intuitive place to put an offset but okay). So I just increased the value of this offset from 250 counts to 2500 counts (for ETMX only). I checked that the script works, now when both ETMs are misaligned, the AS55Q signal shows a clean Michelson-like sine wave as it fringes instead of having the arm cavity PDH fringes as well yes.

Note that the svn doesn't seem to work on the newly upgraded SL7 machines: svn status gives me the following output.

svn: E155036: Please see the 'svn upgrade' command
svn: E155036: Working copy '/cvs/cds/rtcds/userapps/trunk/cds/c1/medm/MISC/ifoalign' is too old (format 10, created by Subversion 1.6)

 Is it safe to run 'svn upgrade'? Or is it time to migrate to git.ligo.org/40m/scripts?

Attachment 1: MichelsonFringing.png
  14152   Fri Aug 10 01:10:56 2018 gautamUpdateLSCSome vertex locking restored

For the first time after the whirlwind vent, I managed to lock the PRMI.

  • First, I did POX/POY locking, dither aligned the arms to maximize TRX and TRY.
  • Next, I misaligned the ETM and tested the Michelson locking
    • Since we've lost ~70% of power on the AS55 PD, I set the whitening gain for AS55 I and Q channels to +6dB (old value was 0dB).
    • worked alright. In this new config, the peak-to-peak Michelson fringe count is ~80 cts, while I reported ~60cts-pp a couple of months ago, so all seems good on that front.
    • But the config script in the IFOconfigure MEDM screen somehow doesn't set the AS55_Q ----> MICH_A element in the LSC input matrix anymore.
    • I edited the .snap file for this configuration to set the relevant matrix element EPICS channel to +1.0.
    • I also edited the overall loop gain for this configuration from +30 to +2 (for bright fringe, use -2 for dark fringe).
  • Feeling adventerous, I decided to try PRMI in the carrier resonant tuning (to be clear, PRCL on REFL11_I, MICH on AS55_Q).
    • Finding the REFL spot on the camera took a while since the PRM has been macroscopically misaligned for the mode-scanning
    • Went out to the table and centered the REFL beam onto REFL11 and REFL55 PDs - didn't need much tweaking, which is a good sign, since we shouldn't have screwed anything up on the symmetric side by any of the vent activities.
    • Restored PRMI locking using the IFOconfigure MEDM screen - lock caught almost immediately.
    • Ran the dither alignment servos for MICH and PRCL - BS needed a bit of encouragement to make the dark spot dark, but POP has been pretty stable over ~15mins.
    • I didn't take any loop transfer functions, to do.

I don't have the energy to make a DRMI attempt tonight - but the signs are encouraging. I'd like to use the IFO in the next few days to try and recover DRMI locking. The main concern is that the optical path on the AS beam has changed by ~0.3m I estimate. So the demod phase for AS55 may need to be adjusted, but the change due to optical path length only should be ~10degrees so the DRMI locking with the old settings should still work. Perhaps we also want to scan the PRC and SRC with the phase information from the Trans/Refl transfer functions as well.

Don't want to jinx it, but the c1lsc FE models have been stable. Tomorrow, I'd like to re-enable c1cal, since it has some useful channels for NBing. Could c1daf/c1oaf which have significant amounts of custom C code be the culprits?

Attachment 1: PRMIcarrier.png
  14154   Fri Aug 10 16:43:50 2018 gautamConfigurationUpgradeParts list for BHD

Can we use the leakage beam from MMT2 on the OMC table as the LO beam? I can't find the spec for this optic, but the leakage beam was clearly visible on an IR card even with the IMC locked with 100 mW input power so presumably there's enough light there, and this is a cavity transmission beam which presumably has some HOM content filtered out.


My current thought is to use the MC reflection, the beam that heads from MC1 to MCR1, as the LO beam

  14157   Mon Aug 13 11:44:32 2018 gautamUpdateComputer Scripts / ProgramsPatch updates on nodus

Larry W said that some security issues were flagged on nodus. So I ran

sudo yum upgrade --exclude=elog-3.1.3-2.el7.x86_64

on nodus. The exclude flag is because there were some conflicts related to that particular package. Hopefully this has fixed the problem. It's been a while since the last update, which was in January of this year.

controls@nodus|~> sudo yum history
Loaded plugins: langpacks
ID     | Command line             | Date and time    | Action(s)      | Altered
    29 | upgrade --exclude=elog-3 | 2018-08-13 11:36 | E, I, U        |  136 EE
    28 | install yum-utils        | 2018-08-13 11:31 | Update         |    1   
    27 | install nmap             | 2018-06-29 01:57 | Install        |    2   
    26 | install grace            | 2018-05-31 16:52 | Install        |   11   
    25 | install https://dl.fedor | 2018-05-31 16:51 | Install        |    1   
    24 | install perl-Digest-SHA1 | 2018-05-31 15:34 | Install        |    1   
    23 | install python-devel     | 2018-01-13 15:33 | Install        |    1   
    22 | install gcc              | 2018-01-13 15:32 | Install        |    6   
    21 | install git              | 2018-01-12 18:11 | Install        |    4   
    20 | update                   | 2018-01-12 18:01 | I, U           |   39   
    19 | install motif            | 2018-01-05 17:35 | Install        |    3   
    18 | install sendmail sendmai | 2017-12-03 05:11 | Install        |    6   
    17 | install vim              | 2017-11-21 18:12 | Install        |    3   
    16 | reinstall mod_dav_svn    | 2017-11-21 17:40 | Reinstall      |    1   
    15 | install mod_dav_svn      | 2017-11-21 17:39 | Install        |    1   
    14 | install subversion       | 2017-11-21 15:36 | Install        |    2   
    13 | -y install php           | 2017-11-20 22:15 | Install        |    4   
    12 | install links            | 2017-11-20 19:10 | Install        |    2   
    11 | install openssl098e.i686 | 2017-11-18 18:28 | Install        |    1   
    10 | install openssl-libs.i68 | 2017-11-18 18:26 | Install        |   11   
history list
  14160   Tue Aug 14 00:27:55 2018 gautamUpdateLSCLocking prep

In preparation for attempting some DRMI locking, I did the following:

  • Slow machine reboots for unresponsive c1psl, c1susaux and c1iscaux. The latter requried a manual burtrestore to recover the usual LSC PD whitening settings.
  • Shuttered AUX laser (which was on Standby anyways) - we should really install a remotely controllable shutter for this on the AS table.
  • Re-aligned PMC (half turn of knob in yaw, full turn in pitch) - IMC transmission 15,000cts ---> 15,600cts.
  • Squished sat. box cables at ITMX and ETMX.

Not related to this work, but I turned the Agilent NA off since we aren't using it immediately.

  14161   Tue Aug 14 00:50:32 2018 gautamUpdateASSX arm ASS still not quite right?

While working on the single arm alignment, I noticed that today, i was able to get the X arm transmission back to ~1.22, and the GTRX to 0.52. These are closer to the values I remember from prior to the vent. Running the dither alignment promptly degrades both the green and IR transmissions. Since the pianosa SL7 upgrade, I can't use the sensoray to capture images, but to me, the spot looks a little off-center in Yaw on ETMX in this configuration, I've tried to show this in the phone grab (Atm #2). Maybe indicative of clipping somewhere upstream of ITMX?

Anyways, I'm pushing onwards for now, something to check out in the daytime.


[koji, gautam]

After I effected the series resistance change for ETMX, the X arm ASS didn't work (i.e. IR transmission would degrade if the servo was run). Today, we succeeded in recovering a functional ASS servo yes.

We then tried to maximize GTRX using the PZT mirrors, but were only successful in reaching a maximum of 0.41. The value I remember from before the vent was 0.5, and indeed, with the IR alignment not quite optimized before we began this work, I saw GTRX of 0.48. But the IR dither servo signals indicate that the cavity axis may have shifted (spot position on the ITM, which is uncontrolled, seems to have drifred significantly, the Pitch signal doesn't stay on the StripTool scale anymore). So we may have to double check that the transmitted beam isn't falling off the GTRX DC PD.

Attachment 1: POXPOY.png
Attachment 2: IMG_7108.JPG
  14162   Tue Aug 14 02:01:12 2018 gautamUpdateLSCDRMI locking - partial success

After tweaking the AS55 demod phase, SRM alignment, triggering settings, I got a few brief DRMI locks in tonight, I'm calling it a success (though this isn't really robust yet). The main things to do now are:

  • turn on all the boosts on the LSC loops - today I only managed to trigger the PRCL boost filters successfully without blowing up the lock.
  • measure all 3 loops, tweak gain as necessary.
  • Run some sensing lines, tune the demod phase.
  • The SRCL triggering is strange to me - SRCL loop is currently triggered on POP22_I, but the 2f1 buildup in the symmetric side does not say anything about the linearity of the SRCL error signal? Or are we just hoping the SRM is in the correct place and engaging the servo? Anyway, this setting seems to work but perhaps once the locking is more robust the triggering can be fixed.
  • do a quick NB - I expect the main change to be that the AS55_Q dark noise contribution would have gone up on account on the reduced amount of light at this port.

I think the main IFO characterization remaining to be done to determine the status of the IFO post vent is to measure the losses of the arm cavities. IMO, we will need to certainly fix the clipping at ETMY before we attempt some serious locking.

Attachment 1: DRMI.png
  14164   Wed Aug 15 12:15:24 2018 gautamUpdateCOCMacroscopic SRC length for SR tuning


It looks like we can have a stable SRC of length 4.044 m without getting any new mirrors, so this is an option to consider in the short-term.


  • The detailed calculations are in the git repo
  • The optical configuration is:
    • A single folding mirror approximately at the current SR3 location.
    • An SRM that is ~1.5m away from the above folding mirror. Which table the SRM goes on is still an open question, per the previous elog in this thread. 
  • The SRC length is chosen to be 4.044 m, which is what the modeling tells us we need for operating in the SR tuning instead of RSE.
  • Using this macroscopic length, I found that we could use a single folding mirror in the SRC, and that the existing (convex) G&H folding mirrors, which have a curvature of -700m, happily combine with our existing SRM (concave with a curvature of 142m) to give reasonable TMS and mode-matching to the arm cavity.
  • The existing SRM transmission of 10% may not be optimal but Kevin's calculations say we should still be able to see some squeezing (~0.8 dB) with this SRM.
  • Attachment #1 - corner plot of the distribution of TMS for the vertical and horizontal modes, as well as the mode-matching (averaged between the two modes) between the SRC and arm cavity.
  • Attachment #2 - histograms of the distributions of RoCs and lengths used to generate Attachment #1. The distributions were drawn from i.i.d Gaussian pdfs.

gautam 245pm: Koji pointed out that the G&H mirrors are coated for normal incidence, but looking at the measurement, it looks like the optic has T~75ppm at 45 degree incidence, which is maybe still okay. Alternatively, we could use the -600m SR3 as the single folding mirror in the SRC, at the expense of slightly reduced mode-matching between the arm cavity and SRC.

Attachment 1: SRC_MCMC_shortTerm.pdf
Attachment 2: SRC_dists_shortTerm.pdf
  14165   Wed Aug 15 19:18:07 2018 gautamUpdateSUSAnother low noise bias path idea

I took another pass at this. Here is what I have now:

Attachment #1: Composite amplifier design to suppress voltage noise of PA91 at low frequencies.

Attachment #2: Transfer function from input to output.

Attachment #3: Top 5 voltage noise contributions for this topology.

Attachment #4: Current noises for this topology, comparison to current noise from fast path and slow DAC noise.

Attachment #5: LISO file for this topology.

Looks like this will do the job. I'm going to run this by Rich and get his input on whether this will work (this design has a few differences from Rich's design), and also on how to best protect from HV incidents.

Attachment 1: HV_Bias.pdf
Attachment 2: HVamp_TF.pdf
Attachment 3: HVamp_noises.pdf
Attachment 4: currentNoises.pdf
Attachment 5: HVamp.fil.zip
  14166   Wed Aug 15 21:27:47 2018 gautamUpdateCDSCDS status update

Starting c1cal now, let's see if the other c1lsc FE models are affected at all... Moreover, since MC1 seems to be well-behaved, I'm going to restore the nominal eurocrate configuration (sans extender board) tomorrow.

  14169   Thu Aug 16 23:06:50 2018 gautamUpdateSUSAnother low noise bias path idea

I had a very fruitful discussion with Rich about this circuit today. He agreed with the overall architecture, but made the following suggestions (Attachment #1 shows the circuit with these suggestions incorporated):

  1. Use an Op27 instead of LT1128, as it is a more friendly part especially in these composite amplifier topologies. I confirmed that this doesn't affect the output voltage noise at 100 Hz, we will still limited by Johnson noise of the 15kohm series resistor.
  2. Take care of voltage distribution in the HV feedback path
    • I overlooked the fact that the passive filtering stage means that the DC current we can drive in the configuration I posted earlier is 150V / 25kohm = 6mA, whereas we'd like to be able to drive at least 10 mA, and probably want the ability to do 12 mA to leave some headroom.
    • At the same time, the feedback resistance shouldn't be too small such that the PA91 has to drive a significant current in the feedback path (we'd like to save that for the coil).
    • Changing the supply voltage of the PA91 from 150 V to 320 V, and changing the gain to x30 instead of x15 (by changing the feedback resistor from 14kohm to 29kohm), we can still drive 12 mA through the 25 kohms of series resistance. This will require getting new HV power supplies, as the KEPCO ones we have cannot handle these numbers.
    • The current limiting resistor is chosen to be 25ohms such that the PA91 is limited to ~26 mA. Of this, 300V / 30kohm ~ 10 mA will flow in the feedback path, which means under normal operation, 12 mA can safely flow through the coils.
    • Rich recommended using metal film resistors in the high voltage feedback path. However, these have a power rating, and also a voltage rating. By using 6x 5kohm resistors, the max power dissipated in each resistor is 50^2 / 5000 ~ 0.5 W, so we can get 0.6 W (or 1W?)  rated resistors which should do the job. I think the S102K or S104K series will do the job.
  3. Add a voltage monitoring capability.
    • This is implemented via a resistive voltage divider at the output of the PA91.
    • We can use an amplifier stage with whitening if necessary, but I think simply reading off the voltage across the terminating resistor in the ladder will be sufficient since this circuit will only have DC authority.
  4. Make a Spice model instead of LISO, to simulate transient effects.
    • I've made the model, investigating transients now.
  5. High voltage precautions:
    • When doing PCB layout, ensure the HV points have more than the default clearance. Rich recommends 100 mils.
    • Use a dual-diode (Schottky) as input protection for the Op27 (not yet implemented in Spice model).
    • Use a TVS diode for the moniotring circuit (not yet implemented in Spice model).
    • Make sure resistors and capacitors that see high voltage are rated with some safety margin.
  6. Consider using the PA95 (which Rich has tested and approves of) instead of the PA91. Does anyone have any opinions on this?

If all this sounds okay, I'd like to start making the PCB layout (with 5 such channels) so we can get a couple of trial boards and try this out in a couple of weeks. Per the current threat matrix and noises calculated, coil driver noise is still projected to be the main technical noise contribution in the 40m PonderSqueeze NB (more on this in a separate elog).


Looks like this will do the job. I'm going to run this by Rich and get his input on whether this will work (this design has a few differences from Rich's design), and also on how to best protect from HV incidents.

Attachment 1: HVamp_schem.PDF
Attachment 2: Hvamp.zip
  14192   Tue Sep 4 10:14:11 2018 gautamUpdateCDSCDS status update

c1lsc crashed again. I've contacted Rolf/JHanks for help since I'm out of ideas on what can be done to fix this problem.


Starting c1cal now, let's see if the other c1lsc FE models are affected at all... Moreover, since MC1 seems to be well-behaved, I'm going to restore the nominal eurocrate configuration (sans extender board) tomorrow.

  14194   Thu Sep 6 14:21:26 2018 gautamUpdateCDSADC replacement in c1lsc expansion chassis

Todd E. came by this morning and gave us (i) 1x new ADC card and (ii) 1x roll of 100m (2017 vintage) PCIe fiber. This afternoon, I replaced the old ADC card in the c1lsc expansion chassis, and have returned the old card to Todd. The PCIe fiber replacement is a more involved project (Steve is acquiring some protective tubing to route it from the FE in 1X6 to the expansion chassis in 1Y3), but hopefully the problem was the ADC card with red indicator light, and replacing it has solved the issue. CDS is back to what is now the nominal state (Attachment #1) and Yarm is locked for Jon to work on his IFOcoupling study. We will monitor the stability in the coming days.


(i) to replace the old generation ADC card in the expansion chassis which has a red indicator light always on and (ii) to replace the PCIe fiber (2010 make) running from the c1lsc front-end machine in 1X6 to the expansion chassis in 1Y3, as the manufacturer has suggested that pre-2012 versions of the fiber are prone to failure. We will do these opportunistically and see if there is any improvement in the situation.

Attachment 1: CDSoverview.png
  14195   Fri Sep 7 12:35:14 2018 gautamUpdateCDSADC replacement in c1lsc expansion chassis

Looks like the ADC was not to blame, same symptoms persist.


The PCIe fiber replacement is a more involved project (Steve is acquiring some protective tubing to route it from the FE in 1X6 to the expansion chassis in 1Y3), but hopefully the problem was the ADC card with red indicator light, and replacing it has solved the issue.

Attachment 1: Screenshot_from_2018-09-07_12-34-52.png
  14198   Mon Sep 17 12:28:19 2018 gautamUpdateIOOPMC and IMC relocked, WFS inputs turned off

The PMC and IMC were unlocked. Both were re-locked, and alignment of both cavities were adjusted so as to maximize MC2 trans (by hand, input alignment to PMC tweaked on PSL table, IMC alignment tweaked using slow bias voltages). I disabled the inputs to the WFS loops, as it looks like they are not able to deal with the glitching IMC suspensions. c1lsc models have crashed again but I am not worrying about that for now.

9pm: The alignment is wandering all over the place so I'm just closing the PSL shutter for now.

  14202   Thu Sep 20 11:29:04 2018 gautamUpdateCDSNew PCIe fiber housed

[steve, yuki, gautam]

The plastic tubing/housing for the fiber arrived a couple of days ago. We routed ~40m of fiber through roughly that length of the tubing this morning, using some custom implements Steve sourced. To make sure we didn't damage the fiber during this process, I'm now testing the vertex models with the plastic tubing just routed casually (= illegally) along the floor from 1X4 to 1Y3 (NOTE THAT THE WIKI PAGE DIAGRAM IS OUT OF DATE AND NEEDS TO BE UPDATED), and have plugged in the new fiber to the expansion chassis and the c1lsc front end machine. But I'm seeing a DC error (0x4000), which is indicative of some sort of timing error (Attachment #1) **. Needs more investigation...

Pictures + more procedural details + proper routing of the protected fiber along cable trays after lunch. If this doesn't help the stability problem, we are out of ideas again, so fingers crossed...

** In the past, I have been able to fix the 0x4000 error by manually rebooting fb (simply restarting the daqd processes on fb using sudo systemctl restart daqd_* doesn't seem to fix the problem). Sure enough, seems to have done the job this time as well (Attachment #2). So my initial impression is that the new fiber is functioning alright yes.


The PCIe fiber replacement is a more involved project (Steve is acquiring some protective tubing to route it from the FE in 1X6 to the expansion chassis in 1Y3)

Attachment 1: PCIeFiberSwap.png
Attachment 2: PCIeFiberSwap_FBrebooted.png
  14203   Thu Sep 20 16:19:04 2018 gautamUpdateCDSNew PCIe fiber install postponed to tomorrow

[steve, gautam]

This didn't go as smoothly as planned. While there were no issues with the new fiber over the ~3 hours that I left it plugged in, I didn't realize the fiber has distinct ends for the "HOST" and "TARGET" (-5 points to me I guess). So while we had plugged in the ends correctly (by accident) for the pre-lunch test, while routing the fiber on the overhead cable tray, we switched the ends (because the "HOST" end of the cable is close to the reel and we felt it would be easier to do the routing the other way. 

Anyway, we will fix this tomorrow. For now, the old fiber was re-connected, and the models are running. IMC is locked.


Pictures + more procedural details + proper routing of the protected fiber along cable trays after lunch. If this doesn't help the stability problem, we are out of ideas again, so fingers crossed...

  14206   Fri Sep 21 16:46:38 2018 gautamUpdateCDSNew PCIe fiber installed and routed

[steve, koji, gautam]

We took another pass at this today, and it seems to have worked - see Attachment #1. I'm leaving CDS in this configuration so that we can investigate stability. IMC could be locked. However, due to the vacuum slow machine having failed, we are going to leave the PSL shutter closed over the weekend.

Attachment 1: PCIeFiber.png
Attachment 2: IMG_5878.JPG
  14207   Fri Sep 21 16:51:43 2018 gautamUpdateVACc1vac1 is unresponsive

Steve pointed out that some of the vacuum MEDM screen fields were reporting "NO COMM". Koji confirmed that this is a c1vac1 problem, likely the same as reported here and can be fixed using the same procedure.

However, Steve is worried that the interlock won't kick in in case of a vacuum emergency, so we are leaving the PSL shutter closed over the weekend. The problem will be revisited on Monday.

  14215   Mon Sep 24 15:06:10 2018 gautamUpdateVACc1vac1 reboot + TP1 controller replacement

[steve, gautam]

Following the procedure in this elog, we effected a reset of the vacuum slow machines. Usually, I just turn the key on these crates to do a power cycle, but Steve pointed out that for the vacuum machines, we should only push the "reset" button.

While TP1 was spun down, we took the opportunity to replace the TP1 controller with a spare unit the company has sent us for use while our unit is sent to them for maintenance. The procedure was in principle simple (I only list the additional ones, for the various valve closures, see the slow machine reset procedure elog):

  • Turn power off using switch on rear.
  • Remove 4 connecting cables on the back.
  • Switch controllers.
  • Reconnect 4 cables on the back panel.
  • Turn power back on using switch on rear.

However, we were foiled by a Philips screw on the DB37 connector labelled "MAG BRG", which had all its head worn out. We had to make a cut in this screw using a saw blade, and use a "-" screwdriver to get this troublesome screw out. Steve suspects this is a metric gauge screw, and will request the company to send us a new one, we will replace it when re-installing the maintaiend controller. 

Attachments #1 and #2 show the Vacuum MEDM screen before and after the reboot respectively - evidently, the fields that were reading "NO COMM" now read numbers. Attachment #3 shows the main volume pressure during this work.


The problem will be revisited on Monday.

Attachment 1: beforeReboot.png
Attachment 2: afterReboot.png
Attachment 3: CC1.png
  14222   Mon Oct 1 20:39:09 2018 gautamConfigurationASCc1asy

We need to set up a copy of the c1asx model (which currently runs on c1iscex), to be named c1asy, on c1iscey for the green steering PZTs. The plan discussed at the meeting last Wednesday was to rename the existing model c1tst into c1asy, and recompile it with the relevant parts copied over from c1asx. However, I suspect this will create some problems related to the "dcuid" field in the CDS params block (I ran into this issue when I tried to use the dcuid for an old model which no longer exists, called c1imc, for the c1omc model).

From what I can gather, we should be able to circumvent this problem by deleting the .par file corresponding to the c1tst model living at /opt/rtcds/caltech/c1/target/gds/param/, and rename the model to c1asy, and recompile it. But I thought I should post this here checking if anyone knows of other potential conflicts that will need to be managed before I start poking around and breaking things. Alternatively, there are plenty of cores available on c1iscey, so we could just set up a fresh c1asy model...

  • (write programming code of making alignment control automatically)
  14223   Mon Oct 1 22:20:42 2018 gautamUpdateSUSPrototyping HV Bias Circuit


I've been plugging away at Altium prototyping the high-voltage bias idea, this is meant to be a progress update.


I need to get footprints for some of the more uncommon parts (e.g. PA95) from Rich before actually laying this out on a PCB, but in the meantime, I'd like feedback on (but not restricted to) the following:

  1. The top-level diagram: this is meant to show how all this fits into the coil driver electronics chain.
    • The way I'm imagining it now, this (2U) chassis will perform the summing of the fast coil driver output to the slow bias signal using some Dsub connectors (existing slow path series resistance would simply be removed). 
    • The overall output connector (DB15) will go to the breakout board which sums in the bias voltage for the OSEM PDs and then to the satellite box.
    • The obvious flaw in summing in the two paths using a piece of conducting PCB track is that if the coil itself gets disconnected (e.g. we disconnect cable at the vacuum flange), then the full HV appears at TP3 (see pg2 of schematic). This gets divided down by the ratio of the series resistance in the fast path to slow path, but there is still the possibility of damaging the fast-path electronics. I don't know of an elegant design to protect against this.
  2. Ground loops: I asked Johannes about the Acromag DACs, and apparently they are single ended. Hopefully, because the Sorensens power Acromags, and also the eurocrates, we won't have any problems with ground loops between this unit and the fast path.
  3. High-voltage precautons: I think I've taken the necessary precautions in protecting against HV damage to the components / interfaced electronics using dual-diodes and TVSs, but someone more knowledgable should check this. Furthermore, I wonder if a Molex connector is the best way to bring in the +/- HV supply onto the board. I'd have liked to use an SHV connector but can't find a comaptible board-mountable connector.
  4.  Choice of HV OpAmp: I've chosen to stick with the PA95, but I think the PA91 has the same footprint so this shouldn't be a big deal.
  5.  Power regulation: I've adapted the power regulation scheme Rich used in D1600122 - note that the HV supply voltage doesn't undergo any regulation on the board, though there are decoupling caps close to the power pins of the PA95. Since the PA95 is inside a feedback loop, the PSRR should not be an issue, but I'll confirm with LTspice model anyways just in case.
  6. Cost: 
    • ​​Each of the metal film resistors that Rich recommended costs ~$15.
    • The voltage rating on these demand that we have 6 per channel, and if this works well, we need to make this board for 4 optics.
    • The PA95 is ~$150 each, and presumably the high voltage handling resistors and capacitors won't be cheap.
    • Steve will update about his HV supply investigations (on a secure platform, NOT the elog), but it looks like even switching supplies cost north of $1200.
    • However, as I will detail in a separate elog, my modeling suggests that among the various technical noises I've modeled so far, coil driver noise is still the largest contribution which actually seems to exceed the unsqueezed shot noise of ~ 8e-19 m/rtHz for 1W input power and PRG 40 with 20ppm RT arm losses, by a smidge (~9e-19 m/rtHz, once we take into account the fast and slow path noises, and the fact that we are not exactly Johnson noise limited).

I also don't have a good idea of what the PCB layer structure (2 layers? 3 layers? or more?) should be for this kind of circuit, I'll try and get some input from Rich.

*Updated with current noise (Attachment #2) at the output for this topology of series resistance of 25 kohm in this path. Modeling was done (in LTspice) with a noiseless 25kohm resistor, and then I included the Johnson noise contribution of the 25k in quadrature. For this choice, we are below 1pA/rtHz from this path in the band we care about. I've also tried to estimate (Attachment #3) the contribution due to (assumed flat in ASD) ripple in the HV power supply (i.e. voltage rails of the PA95) to the output current noise, seems totally negligible for any reasonable power supply spec I've seen, switching or linear.

Attachment 1: CoilDriverBias.pdf
CoilDriverBias.pdf CoilDriverBias.pdf CoilDriverBias.pdf
Attachment 2: currentNoise.pdf
Attachment 3: PSRR.pdf
  14225   Tue Oct 2 23:57:16 2018 gautamUpdatePonderSqueezeSqueezing scenarios

[kevin, gautam]

We have been working on double checking the noise budget calculations. We wanted to evaluate the amount of squeezing for a few different scenarios that vary in cost and time. Here are the findings:

Squeezing scenarios

Sqz [dBvac] fmin [Hz] PPRM [W] PBS [W] TPRM [%] TSRM [%]
-0.41 215 0.8 40 5.637 9.903
-0.58 230 1.7 80 5.637 9.903
-1.05 250 1.7 150 1 17
-2.26 340 10 900 1 17

All calculations done with

  • 4.5kohm series resistance on ETMs, 15kohms on ITMs, 25kohm on slow path on all four TMs.
  • Detuning of SRC = -0.01 deg.
  • Homodyne angle = 89.5 deg.
  • Homodyne QE = 0.9. 
  • Arm losses is 20ppm RT.
  • LO beam assumed to be extracted from PR2 transmission, and is ~20ppm of circulating power in PRC.


  1. Existing setup, new RC folding mirrors for PRG of ~45.
  2. Existing setup, send Innolight (Edwin) for repair (= diode replacement?) and hope we get 1.7 W on back of PRM.
  3. Repair Innolight, new PRM and SRM, former for higher PRG, latter for higher DARM pole.
  4. Same as #3, but with 10 W input power on back of PRM (i.e. assuming we get a fiber amp).


  • The errors on the small dB numbers is large - 1% change in model parameters (e.g. arm losses, PRG, coil driver noise etc) can mean no observable squeezing. 
  • Actually, this entire discussion is moot unless we can get the RIN of the light incident on the PRM lower than the current level (estimated from MC2 transmission, filtered by CARM pole and ARM zero) by a factor of 60dB.
    • This is because even if we have 1mW contrast defect light leaking through the OMC, the beating of this field (in the amplitude quadrature) with the 20mW LO RIN (also almost entirely in the amplitude quad) yields significant noise contribution at 100 Hz (see Attachment #1).
    • Actually, we could have much more contrast defect leakage, as we have not accounted for asymmetries like arm loss imbalance.
    • So we need an ISS that has 60dB of gain at 100 Hz. 
    • The requirement on LO RIN is consistent with Eq 12 of this paper.
  • There is probably room to optimize SRC detuning and homodyne angle for each of these scenarios - for now, we just took the optimized combo for scenario #1 for evaluating all four scenarios.
  • OMC displacement noise seems to only be at the level of 1e-22 m/rtHz, assuming that the detuning for s-pol and p-pol is ~30 kHz if we were to lock at the middle of the two resonances
    • This assumes 0.02 deg difference in amplitude reflectivity b/w polarizations per optic, other parameters taken from aLIGO OMC design numbers.
    • We took OMC displacement noise from here.

Main unbudgeted noises:

  • Scattered light.
  • Angular control noise reinjection (not sure about the RP angular dynamics for the higher power yet).
  • Shot noise due to vacuum leaking from sym port (= DC contrast defect), but we expect this to not be significant at the level of the other noises in Atm #1.
  • Osc amp / phase.
  • AUX DoF cross coupling into DARM readout.
  • Laser frequency noise (although we should be immune to this because of our homodyne angle choice).

Threat matrix has been updated.

Attachment 1: PonderSqueeze_NB_LORIN.pdf
  14233   Fri Oct 5 17:47:55 2018 gautamConfigurationASCY-end table upgrade

What about just copying the Xend layout? I think it has good MM (per calculations), reasonable (in)sensitivity to component positions, good Gouy phase separation, and I think it is good to have the same layout at both ends. Since the green waist has the same size and location in the doubling crystal, it should be possible to adapt the X end solution to the Yend table pretty easily I think.


The setup I designed is here. It can bring 100% mode-matching and good separation of degrees of TEM01, however I found a probrem. The picture of setup is attached #3. You can see the reflection angle at Y7 and Y8 is not appropriate. I will consider the schematic again.

  14235   Sun Oct 7 16:51:03 2018 gautamConfigurationLSCYarm triggering changed

To facilitate Yuki's alignment of the EY green beam into the Yarm cavity, I have changed the LSC triggering and PowNorm settings to use only the reflected light from the cavity to do the locking of Arm Cavity length to PSL. Running the configure script should restore the usual TRY triggering settings. Also, the X arm optics were macroscopically misaligned in order to be able to lock in this configuration.

  14238   Mon Oct 8 18:56:52 2018 gautamConfigurationASCc1asx filter coefficient file missing

While pointing Yuki to the c1asx servo system, I noticed that the filter file for c1asx is missing in the usual chans directory. Why? Backups for it exist in the filter_archive subdirectory. But there is no current file. Clearly this doesn't seems to affect the realtime code execution as the ASX model seems to run just fine. I copied the latest backup version from the archive area into the chans directory for now.

  14239   Tue Oct 9 16:05:29 2018 gautamConfigurationASCc1tst deleted, c1asy deployed.

Setting up c1asy:

  • Backed up old c1tst.mdl as c1tst_old_bak.mdl in /opt/rtcds/userapps/release/cds/c1/models
  • Copied the c1tst model to /opt/rtcds/userapps/release/isc/c1/models/c1asy.mdl as this is where the c1asx.mdl file resides.
  • Backed up original c1rfm.mdl as c1rfm_old.mdl in /opt/rtcds/userapps/release/cds/c1/models (since the old c1tst had an RFM block which is unnecessary).
  • Deleted offending RFM block from c1rfm.mdl.
  • Recompiled and re-installed c1rfm.mdl. Model has not yet been restarted, as I'd like suspension watchdogs to be shutdown, but c1susaux EPICS channels are presently not responsive.
  • Removed c1tst model (C-node91) from /opt/rtcds/caltech/c1/target/gds/param/testpoints.
  • Removed /opt/rtcds/caltech/c1/target/gds/param/tpchn_c1tst.par (at this point, DCUID 91 is free for use by c1asy).
  • Moved c1tst line in /opt/rtcds/caltech/c1/target/daqd/master to "old model definitions models" section.
  • Added /opt/rtcds/caltech/c1/target/gds/param/tpchn_c1asy.par to the master file.
  • Edited/diskless/root.jessie/etc/rtsystab to allow c1asy to be run on c1iscey.
  • Finally, I followed the instructions here to get the channels into frames and make all the indicators green.

Now Yuki can work on copying the simulink model (copy c1asx structure) and implementing the autoalignment servo.

Attachment 1: CDSoverview_ASY.png
  14264   Wed Oct 31 17:54:25 2018 gautamUpdateVACCC1 hornet power connection restored

Steve reported to me that the CC1 Hornet gauge was not reporting the IFO pressure after some cable tracing at EX. I found that the power to the unit had been accidentally disconnected. I re-connected the power and manually turned on the HV on the CC gauge (perhaps this can be automated in the new vacuum paradigm). IFO pressure of 8e-6 torr is being reported now.

Attachment 1: cc1_Hornet.png
  14269   Fri Nov 2 19:25:16 2018 gautamUpdateComputer Scripts / Programsloss measurements

Some facts which should be considered when doing this measurement and the associated uncertainty:

  1. When Johannes did the measurement, there was no light from the AS port diverted to the OMC. This represents ~70% loss in the absolute amount of power available for this measurement. I estimate ~1W*Tprm * Ritm * Tbs * Rbs * Tsrm * OMCsplit ~ 300uW which should still be plenty, but the real parameter of interest is the difference in reflected power between locked/no cavity situations, and how that compares to the RMS of the scope readout. For comparison, the POX DC light level is expected to be ~20uW, assuming a 600ppm AR coating on the ITMs.
  2. Even though the reflection from the arm not being measured may look like it's completely misaligned looking at the AS camera, the PDA520 which is used at the AS port has a large active area and so one must check on the oscilloscope that the other arm is truly misaligned and not hitting the photodiode to avoid interference effects artifically bloating the uncertainty.
  3. The PDA255 monitoring the MC transmission has a tiny active area. I'm not sure the beam has been centered on it anytime recently. If the beam is not well centered on that PD, and you normalize the measurements by "MC Transmission", you're likely to end up with larger error.

This result has about 40% of uncertaintities in XARM and 33% in YARM (so big... no).

  14275   Tue Nov 6 15:23:48 2018 gautamUpdateIOOIMC problematic

The IMC has been misbehaving for the last 5 hours. Why? I turned the WFS servos off. afaik, aaron was the last person to work on the IFO, so i'm not taking any further debugging steps so as to not disturb his setup.

Attachment 1: MCwonky.png
  14279   Tue Nov 6 23:19:06 2018 gautamUpdateVACc1vac1 FAIL lights on (briefly)

Jon and I stuck a extender card into the eurocrate at 1X8 earlier today (~5pm PT), to see if the box was getting +24V DC from the Sorensen or not. Upon sticking the card in, the FAIL LEDs on all the VME cards came on. We immediately removed the extender card. Without any intervention from us, after ~1 minute, the FAIL LEDs went off again. Judging by the main volume pressure (Attachment #1) and the Vacuum MEDM screen (Attachment #2), this did not create any issues and the c1vac1 computer is still responsive.

But Steve can perhaps run a check in the AM to confirm that this activity didn't break anything.

Is there a reason why extender cards shouldn't be stuck into eurocrates?

Attachment 1: Screenshot_from_2018-11-06_23-18-23.png
Attachment 2: Screenshot_from_2018-11-06_23-19-26.png
  14283   Wed Nov 7 19:20:53 2018 gautamUpdateComputersPaola Battery Error

The VEA vertex laptop, paola, has a flashing orange indicator which I take to mean some kind of battery issue. When the laptop is disconnected from its AC power adaptor, it immediately shuts down. So this machine is kind of useless for its intended purpose of being a portable computer we can work at optical tables withno. The actual battery diagnostics (using upower) don't report any errors. 

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