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Message ID: 9016     Entry time: Thu Aug 15 21:42:53 2013
Author: Charles 
Type: Update 
Category: ISS 
Subject: ISS - Schematic + PCB Layout 

 After many, many moons of getting to know exactly how frustrating Altium can be, I have completed the PCB layout for my ISS board (final page of ISS_v3.pdf).

Before I get into detail about the PCB, there is one significant schematic change to note: the comparator circuit was changed (with significant help from Koji) so that the voltage reference for boost triggering is established in a more logical way. Instead of the somewhat convoluted topology I had before, now there are only two feedback resistors, R82 and R83. Because their resistances (500k and 50k respectively) are so much larger than the total resistance of the 1k potentiometer (used to establish a tunable threshold voltage), the current flowing through the feedback loop is negligible compared to the 5 mA current flowing through the potentiometer (the pot is rated for 2 W and with 5 mA -> 25 mW dissapation). This allows one to set the threshold voltage for my schmitt trigger, at pin 2 of both the pot and the comparator, entirely with the pot. This trigger also has hysteresis given by the relation deltaV ~ (R83/R82) * (Voh - Vol) where deltaV is the separation between threshold voltages, Voh is the high-level comparator ouput and Vol is the low-level comparator output. Koji simulated this using CircuitLab and I plan to verify the behavior by making a quick prototype circuit.

Now, on to the PCB. The board itself is of a 'standard' LIGO size (11" x 6") has 3 routing layers and 3 internal planes, one for +15 V, one for -15 V and one for GND. In the attached pdf, red is the top routing layer, blue is the bottom layer and brown is the middle routing layer (used for ±5 V exclusively). The grey circles are pads and vias (drilled through) and anything in black is silkscreen overlay. I placed each component and track by hand, attempting to minimize the signal path and following the general rules below,

  • Headers for power, ±5 V and ±15V, are at the back of the board
  • For sections of the board such as filter stages or buffers, resistors and capacitors were grouped around their respective op-amps.
  • As often as was possible, routing was confined to the top layer. Tracks on the bottom layer were placed mostly out of necessity (i.e. no possible connection on top routing layer).
  • The signal generally proceeds from left to right (directions with respect to the attached printout) in the same logical order as on the schematic sheets. Refer to the global sheet (page 1) of the attached "ISS_v3.pdf".
  • External ports such as the PD input, various monitoring ports and panel mounted switches/LEDs were all connected to the board via headers located along the front edge. These are also ordered following the schematic layout.
  • Occasionally, similar signal paths were grouped together although this was a rarity on my board

Sections of the board have been partitioned and labeled with silkscreen overlay to help in both signal pathway recognition as well as eventual troubleshooting.

On the board, I have also included holes so that it can be mounted inside of an enclosure. There is a DCC number printed as well as a 'barcode' (TrueType font: IDAutomationC39S), although they both contain filler asterisks as I haven't published this to the DCC and thus do not have a number.

Attachment 1: ISS_v3.pdf  862 kB  | Hide | Hide all
ISS_v3.pdf ISS_v3.pdf ISS_v3.pdf ISS_v3.pdf ISS_v3.pdf ISS_v3.pdf
Attachment 2: ISS_v3-Power_Reg.pdf  146 kB  | Hide | Hide all
ISS_v3-Power_Reg.pdf
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