40m QIL Cryo_Lab CTN SUS_Lab TCS_Lab OMC_Lab CRIME_Lab FEA ENG_Labs OptContFac Mariner WBEEShop
  40m Log  Not logged in ELOG logo
 List  |  Find  |  Login  |  Help 
Entry  Fri Nov 12 10:49:34 2010, josephb, valera, Update, CDS, Test of ADC noise ADC_noise.pdf
    Reply  Fri Nov 12 19:24:56 2010, Koji, Update, CDS, Test of ADC noise 
    Reply  Sun Nov 14 11:56:59 2010, valera, Update, CDS, Test of ADC noise 
Message ID: 3915     Entry time: Sun Nov 14 11:56:59 2010     In reply to: 3906
Author: valera 
Type: Update 
Category: CDS 
Subject: Test of ADC noise 

 

We missed a factor of 2 in the ADC calibration: the differential 16 bit ADC with +/-10 V input has 20 V per 32768 counts (1 bit is for the sign). I confirmed this calibration by directly measuring ADC counts per V.

So the ADC input voltage noise with +/-10V range around 100 Hz is 6.5e-3 cts/rtHz x 20V/32768cts =  4.0 uV/rtHz. Bummer. 

The ADC quantization noise limit is 1/sqrt(12 fs/2)=1.6e-3 cts/rtHz. Where the ADC internal sampling frequency is fs=64 kHz. If this would be the limiting digitization noise source then the equivalent ADC input voltage noise would be 1 uV/rtHz with +/-10 V range.

ELOG V3.1.3-