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Entry  Sun Mar 28 17:28:26 2010, matt, kiwamu, Update, Green Locking, frequency discriminator for green PLL 6x
    Reply  Mon Mar 29 15:19:33 2010, mevans, Update, Green Locking, frequency discriminator for green PLL 
       Reply  Wed Mar 31 02:57:48 2010, kiwamu, Update, Green Locking, frequency counter for green PLL FCnoise.png
          Reply  Wed Mar 31 12:30:31 2010, rana, Update, Green Locking, frequency counter for green PLL 
          Reply  Thu Apr 1 15:21:12 2010, rana, Update, Green Locking, frequency counter for green PLL 
Message ID: 2718     Entry time: Sun Mar 28 17:28:26 2010     Reply to this: 2728
Author: matt, kiwamu 
Type: Update 
Category: Green Locking 
Subject: frequency discriminator for green PLL 

Last Friday, Matt made a frequency discriminator circuit on a bread board in order to test the idea and study the noise level. I think it will work for phase lock acquisition of Green locking.

As a result a response of 100kHz/V and a noise level of 2uV/rtHz @ 10Hz are yielded. This corresponds to 0.2Hz/rtHz @ 10Hz.

The motivation of using frequency discriminators is that  it makes a frequency range wider and easier for lock acquisition of PLLs in green locking experiment.

For the other possibility to help phase lock acquisition, Rana suggested to use a commercial discriminator from Miteq.


(principle idea)

The diagram below shows a schematic of the circuit which Matt has built.

FD.png

Basically an input signal is split into two signals right after the input, then one signal goes through directly to a NAND comparator.

On the other hand another split signal goes through a delay line which composed by some RC filters, then arrive at the NAND comparator with a certain amount of delay.

After going through the NAND comparator, the signal looks like a periodic pulses (see below).

If we put a signal of higher frequency we get more number of pulses after passing through the NAND.

pulses.png

Finally the pulse-signal will be integrated at the low pass filter and converted to a DC signal.

Thus the amplitude of DC signal depends on the number of the pulses per unit time, so that the output DC signal is proportional to the frequency of an input signal.

 

 

(result)

By putting a TTL high-low signal, an output of the circuit shows 100kHz/V linear response.

It means we can get DC voltage of 1 V if a signal of 100kHz is injected into the input.

And the noise measurement has been done while injecting a input signal. The noise level of 0.2Hz/rtHz @ 10 Hz was yielded.

Therefore we can lock the green PLL by using an ordinary VCO loop after we roughly guide a beat note by using this kind of discriminator.

 FDnoise.png

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