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Message ID: 17104     Entry time: Thu Aug 25 15:24:06 2022
Author: Paco 
Type: HowTo 
Category: Electronics 
Subject: RFSoC 2x2 board -- fandango 

[Paco, Chris Stoughton, Leo -- remote]

This morning Chris came over to the 40m lab to help us get the RFSoC board going. After checking out our setup, we decided to do a very basic series of checks to see if we can at least get the ADCs to run coherently (independent of the DACs). For this I borrowed the Marconi 2023B from inside the lab and set its output to 1.137 GHz, 0 dBm. Then, I plugged it into the ADC1 and just ran the usual spectrum analyzer notebook on the rfsoc jupyter lab server. Attachment #1 - 2 shows the screen captured PSDs for ADCs 0 and 1 respectively with the 1137 MHz peaks alright.

The fast ADCs are indeed reading our input signals.

Before this simple test, we actually reached out to Leo over at Fermilab for some remote assistance on building up our minimally working firmware. For this, Chris started a new vivado project on his laptop, and realized the rfsoc 2x2 board files are not included in it by default. In order to add them, we had to go into Tools, Settings and add the 2020.1 Vivado Xilinx shop board repository path to the rfsoc2x2 v1.1 files. After a little bit of struggling, uninstalling, reinstalling them, and restarting Vivado, we managed to get into the actual overlay design. In there, with Leo's assistance, we dropped the Zynq MPSoC core (this includes the main interface drivers for the rfsoc 2x2 board). We then dropped an rf converter IP block, which we customized to use the right PLL settings. The settings, from the System Clocking tab were changed to have a 409.6 MHz Reference Clock (default was 122.88 MHz). This was not straightforward, as the default sampling rate of 2.00 GSPS was not integer-related so we had to also update that to 4.096 GSPS. Then, we saw that the max available Clock Out option was 256 MHz (we need to be >= 409.6 MHz), so Leo suggested we dropped a Clocking Wizard block to provide a 512 MHz clock input for the rfdc. The final settings are captured in Attachment # 3. The Clocking Wizard was added, and configured on its Output Clocks tab to provide a Requested Output Freq of 512 MHz. The finall settings of the Clocking wizard are captured in Attachment #4. Finally, we connected the blocks as shown in Attachment #5.

We will continue with this design tomorrow.

Attachment 1: adc0_1137MHz.png  43 kB  Uploaded Thu Aug 25 16:35:21 2022  | Hide | Hide all
Attachment 2: adc1_1137MHz.png  45 kB  Uploaded Thu Aug 25 16:35:27 2022  | Hide | Hide all
Attachment 3: rfdc_PLLsettings.png  31 kB  Uploaded Thu Aug 25 16:42:32 2022  | Hide | Hide all
Attachment 4: clockingwiz_settings.png  25 kB  Uploaded Thu Aug 25 16:42:57 2022  | Hide | Hide all
Attachment 5: blockIPdiag.png  55 kB  Uploaded Thu Aug 25 16:43:27 2022  | Hide | Hide all
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