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40m
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| 40m elog |
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 Wed May 25 16:56:44 2022, Paco, Configuration, BHD, IFO recovery - IMC alignment
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 Wed May 25 17:34:47 2022, yuta, Configuration, BHD, IFO recovery - IFO alignment 
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Thu May 26 19:55:43 2022, yuta, Configuration, BHD, Oplevs centered, BHD DCPDs are now online
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Fri May 27 17:45:53 2022, yuta, Configuration, BHD, BHD camera installed, GRY aligned
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Thu Jun 2 20:05:37 2022, yuta, Configuration, PSL, IMC input power recovered to 1W, some alignment works
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Fri Jun 3 12:13:58 2022, Paco, Configuration, CDS, Fix RFM channels
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Fri Jun 3 15:22:51 2022, yuta, Update, LSC, Both arms locked with POY/POX, IR beam centered on TMs with ASS
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Fri Jun 3 17:42:50 2022, yuta, Update, LSC, MICH locks with AS55_Q
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Sun Jun 5 19:46:40 2022, Paco, Update, LSC, Fixed IMC Trans sum issue
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Mon Jun 6 13:35:11 2022, Paco, Update, LSC, First calibrated spectra of MICH at AS55 Q
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Fri Jun 17 16:22:21 2022, yuta, Update, LSC, Actuator calibration of BS. ITMX, ITMY, updated MICH displacement spectra from c1cal 6x
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Thu Jul 7 18:18:19 2022, yuta, Update, LSC, Actuator calibration of ETMX and ETMX
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Thu Jul 7 18:22:12 2022, yuta, Update, LSC, Actuator calibration of MC2 using Yarm
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Fri Jul 8 16:18:35 2022, rana, Update, LSC, Actuator calibration of MC2 using Yarm
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Mon Jul 18 17:07:12 2022, yuta, Update, LSC, x4.12 added to ETMX coil outputs to balance with ETMY
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Thu Jun 16 18:23:15 2022, Paco, Configuration, BHD, Recovering LO beam in BHD DCPDs
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Tue Jun 21 14:17:50 2022, yuta, Configuration, BHD, BHD DCPDs re-routed to c1sus2
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Tue Jul 19 16:00:34 2022, yuta, Configuration, BHD, Fast channels for BHD DCPDs now available in c1lsc but not in c1hpc
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Thu Jul 21 21:50:47 2022, Tega, Configuration, BHD, c1sus2 IPC update
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Fri Jul 22 15:05:26 2022, Tega, Configuration, BHD, c1sus2 shared memory and ADC fix
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Fri Jul 22 17:46:10 2022, yuta, Configuration, BHD, c1sus2 watchdog update and DCPD ERR channels
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Mon Jul 25 17:58:10 2022, Tega, Configuration, BHD, c1sus2 IPC dolphin issue update
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Mon Aug 1 18:42:39 2022, Tega, Configuration, BHD, c1sus2 IPC dolphin issue update
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Tue Aug 2 17:25:18 2022, Tega, Configuration, BHD, c1sus2 dolphin IPC issue solved
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Mon Jul 25 18:09:41 2022, Tega, Configuration, BHD, BHD Homodyne Phase control MEDM screen
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Message ID: 17026
Entry time: Fri Jul 22 15:05:26 2022
In reply to: 17025
Reply to this: 17028
17034
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| Author: |
Tega |
| Type: |
Configuration |
| Category: |
BHD |
| Subject: |
c1sus2 shared memory and ADC fix |
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[Tega, Yuta]
We were able to fix the shared memory issue by updating the receiver model name from ''SUS' to 'SU2' and the ADC zero issue by including both ADC0 and ADC1 in the c1hpc and c1bac models as well as removing the grounding of the unused ADC channels (including chn#16 and chn#17 which are actually used in c1hpc) in c1su2. We also used shared memory to move the DCPD_A/B error signals (after signal conditioning and mixing A/B; now named A_ERR and B_ERR) from c1hpc to c1bac.
C1:HPC-DCPD_A_IN1 and C1:HPC-DCPD_B_IN1 are now available (they are essentially the same as C1:LSC-DCPD_A_IN1 and C1:LSC-DCPD_B_IN1, except for they are ADC-ed with different ADC; see elog 40m/16954 and Attachment #1).
Dolphin IPC error in seding signal from c1hpc to c1lsc still remains. |
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